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MIPS Instruction Formats are sometimes called MIPS instruction encoding formats. Instruction encoding means the MIPS instruction are translated into binary numbers and then bring back to original format for human understanding (decoding). Encoding should be done in a way that decoding is easy. MIPS ISA has a 32-bit fixed instruction encoding. MIPS instruction formats include: R-Format I-Format J-Format …………………

Simplicity favors regularityConsider the following example:

Category

Instruction

Example

Meaning Comments

Arithmetic add add

a,b,c a=b+c Always 3 operands

Arithmetic subtract sub

a,b,c a=b-c Always 3 operands

Arithmetic Instructions

Instruction Example Meaning Comments

1

add add $1,$2,$3

$1=$2+$3

Always 3 operands

subtract sub $1,$2,$3

$1=$2-$3

Always 3 operands

add immediate addi $1,$2,10

$1=$2+10 add constant

add unsigned addu $1,$2,$3

$1=$2+$3

Always 3 operations

subtract unsigned

subu $1,$2,$3

$1=$2-$3

Always 3 operations

add immed.unsigned

addiu $1,$2,10

$1=$2+10

Always 3 operations

Logical

Instruction Example Meaning Comments

and and $1,$2,$3

$1=$2&$3

3 register operands

or or $1,$2,$3

$1=$2|$3

3 register operands

and immediate

andi $1,$2,10

$1=$2&10 AND constant

or immediate or $1,$2,10

$1=$2|10 OR constant

shift left logical

sll $1,$2,10

$1=$2<<10

Shift left by constant

shift right logical

srl $1,$2,10

$1=$2>>10

Shift right by constant

MIPS Instruction Format TableLet's discuss MIPS instruction formats in details with tables:

2

NAME TOTAL 32-BITSDESCRIPTION

Field Size 6-bits

5-bits

5-bits

5-bits

5-bits

6-bits

total 32-bits

R-Format

opcode rs rt rd

shamt

funct

Arithematic and Logic Instructions

I-Format

opcode rs rt immediate value

Branches, Immediate, Data Transfer

J-Format

opcode Target Address

Jump Instructions

………….

MIPS Instruction R-Format is used for arithmetic and logical instruction. Encoding format used forMIPS R-Formate is given below:

TOTAL 32-BITS6-bits 5-bits 5-bits 5-bits 5-bits 6-bits

opcode rs rt rd shamt funct

Table 5.7. Register Instruction Format

Opcode

Source 1

Source 2

Destination

Shift Amount

Function

00000 5 bits 5 bits 5 bits 5 bits 6 bits

3

Opcode

Source 1

Source 2

Destination

Shift Amount

Function

0

Zeroes in the leftmost six bits indicates to the control unit that this is a register instruction. It then uses the rightmost six bits to distinguish the operation codes. Note that the operands are not necessarily in the same order in assembly language and machine language.

add $t3, $t4, $t1 # Destination first in assembly! # $t3 = $11, $t4 = $12, $t1

= $9 000000 01100 01001 01011 00000 100000 ^^^^^^ ^^^^^ ^^^^^ ^^^^^ ^^^^^

^^^^^^ RI $t4 $t1 $t3 unused add

Opcode (bit 31-bit 26)Opcode stands for "operational code". It is the machine representation of instructions. It's is 6-bit long.rs (bit 25-bit 21)The first source register is rs. The source register contains a value for the operation. It's is 5-bit long.

rt (bit 20-bit 16)This is the second source register. It's is 5-bit long.rd (bit 15-bit 11)The destination register is rd. It stores the result of operations performed or rs and rt. It's is 5-bit long.shamt (bit 10-bit 6)Shamt stands for shift amount. It shows how many bits rs is shifted. It's is 5-bit long.funct (bit 5-bit 0)

4

The function is used in addition to opcode to specify the operation. Its size is 6-bits.R Type Instruction Format ExampleConsider the following subtraction example to understand the use of R-type:[code]sub $t1, $t2, $t3Where SUB is the opcode, $t1 is the destination register $rd, $t2 is the first source and $t3 is the second source register.[/code]MIPS I-FormatI stands for "immediate value". An immediate is a 16-bit value.  The General form of an I-Type instruction is as follows:[code]opcode $rt, $rs, immediate value[/code]Encoding format used for MIPS I-Formate is given below:TOTAL 32-BITS

6-bits 5-bits 5-bits 5-bits 5-bits 6-bits

opcode rs rt immediate value

Opcode (bit 31-bit 26)It is operational code. It is the machine representation of instructions. It's is 6-bit long. i.e. add, sub

rs (bit 25-bit 21)The first source register is rs. The source register contains a value for the operation. It's is 5-bit long.

rt (bit 20-bit 16)

5

Rt is the destination register. It contains the results.

immediate value(bit 15-bit 0)Immediate value is a 16-bit value used with another source register.

addi $t1, $t5, 7 001000 01101 01001 0000000000000111 addi $t5 $t1 7

I-type Instruction Format ExampleConsider the following subtraction example to understand the use of I-type:

[code]

li $t2,30

sub $t1, $t2, 26

Where SUB is the opcode, $t1 is the destination register $rt, $t2 is the first source and 26 is the immediate value.

[/code]

MIPS J-FormatJ stands for "JUMP.". J-type has a jump instruction and a target address. General representation of J-Type is as follows:

[code]

jump          Target_Address

[/code]

6

TOTAL 32-BITS6-bits 5-bits 5-bits 5-bits 5-bits 6-bits

opcode Target AddressOpcode (bit 31-bit 26)In I-format opcode is a 6-bit jump instruction. They are usually j, jal, jar  etcTarget Address (bit 25-bit 0)The target address is 26-bit address in a program where the control is to be transferred.

J-type Instruction Format ExampleConsider the following subtraction example to understand the use of I-type:

[code]

j addition

addition:

add $t1,$t2,$t3

Here we have a 26-bit target address "addition".

[/code]

OpcodesThe following table contains a listing of MIPS instructions and the corresponding opcodes. Opcode and funct numbers are all listed in hexadecimal.

Mnemonic

MeaningType

Opcode

Funct

add Add R 0x00 0x20

7

Mnemonic

MeaningType

Opcode

Funct

addi Add Immediate I 0x08 NA

addiuAdd Unsigned Immediate

I 0x09 NA

addu Add Unsigned R 0x00 0x21

and Bitwise AND R 0x00 0x24

andiBitwise AND Immediate

I 0x0C NA

beq Branch if Equal I 0x04 NA

blezBranch if Less Than or Equal to Zero

I 0x06 NA

bne Branch if Not Equal I 0x05 NA

bgtzBranch on Greater Than Zero

I 0x07 NA

div Divide R 0x00 0x1A

divu Unsigned Divide R 0x00 0x1B

j Jump to Address J 0x02 NA

jal Jump and Link J 0x03 NA

jrJump to Address in Register

R 0x00 0x08

lb Load Byte I 0x20 NA

lbu Load Byte Unsigned I 0x24 NA

lhu Load Halfword I 0x25 NA

8

Mnemonic

MeaningType

Opcode

Funct

Unsigned

luiLoad Upper Immediate

I 0x0F NA

lw Load Word I 0x23 NA

mfhi Move from HI Register R 0x00 0x10

mthi Move to HI Register R 0x00 0x11

mfloMove from LO Register

R 0x00 0x12

mtlo Move to LO Register R 0x00 0x13

mfc0Move from Coprocessor 0

R 0x10 NA

mult Multiply R 0x00 0x18

multu Unsigned Multiply R 0x00 0x19

nor Bitwise NOR (NOT-OR) R 0x00 0x27

xorBitwise XOR (Exclusive-OR)

R 0x00 0x26

or Bitwise OR R 0x00 0x25

ori Bitwise OR Immediate I 0x0D NA

sb Store Byte I 0x28 NA

sh Store Halfword I 0x29 NA

slt Set to 1 if Less Than R 0x00 0x2A

slti Set to 1 if Less Than I 0x0A NA

9

Mnemonic

MeaningType

Opcode

Funct

Immediate

sltiuSet to 1 if Less Than Unsigned Immediate

I 0x0B NA

sltuSet to 1 if Less Than Unsigned

R 0x00 0x2B

sll Logical Shift Left R 0x00 0x00

srlLogical Shift Right (0-extended)

R 0x00 0x02

sraArithmetic Shift Right (sign-extended)

R 0x00 0x03

sub Subtract R 0x00 0x22

subu Unsigned Subtract R 0x00 0x23

sw Store Word I 0x2B NA

10

Example add $s0, $s1, $s2 (registers 16, 17, 18)

op rs rt rd shamt funct0 17 18 16 0 32

000000

10001

10010

10000

00000

100000

NOTE: Order of components in machine code is different from assembly code. Assembly code order is similar to C, destination first. Machine code has destination last.

C: a = b + c

assembly code:

add $s0, $s1, $s2    # add rd, rs, rt

machine code:

000000 10001 10010 10000 0000 100000(op rs rt rd shamt funct)

Example of MIPS assembly language

1. MIPS Tutorial 1 Hello Assembly

2. Printing a character

3. Printing an Integer

11

4. Adding Integer

5. Subtracting Integer

6. Multiplying Integer mul

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