White Paper final - AWR is now Cadence | AWR Software

Xilinx HighXilinx HighXilinx HighXilinx High----Speed Serial BackplaneSpeed Serial BackplaneSpeed Serial BackplaneSpeed Serial Backplane White PaperWhite PaperWhite PaperWhite Paper

Ver 1.0

Written by: Bill Dempsey

Red Wire Enterprises

Date: April 2, 2009

Copyright 2006-2008, Red Wire Enterprises

ii

Release VersionRelease VersionRelease VersionRelease Version AuthorAuthorAuthorAuthor DateDateDateDate Description of RDescription of RDescription of RDescription of Releaseeleaseeleaseelease

1.0 WFD 03/17/08 Formal Release

iii

Table of ContentsTable of ContentsTable of ContentsTable of Contents

Abstract........................................................................................................................................... 7

Overview......................................................................................................................................... 8

Before you start .......................................................................................................................... 8

Designing the Backplane............................................................................................................... 9

Cost factors ................................................................................................................................. 9

Connectors................................................................................................................................. 10

Tools .............................................................................................................................................. 11

Tools selected ............................................................................................................................ 14

Layout Tools.............................................................................................................................. 14

Tradeoffs ....................................................................................................................................... 15

Connector type.......................................................................................................................... 15

Connector pinout ...................................................................................................................... 16

Material..................................................................................................................................... 20

Materials chosen....................................................................................................................... 22

Laminate Skew ......................................................................................................................... 25

Back-drilling ............................................................................................................................. 25

Hybrid Constructions ............................................................................................................... 27

Edge plating and ground via stitching.................................................................................... 27

Routing Skew............................................................................................................................ 28

Things to think about .................................................................................................................. 33

Contacting your PCB fabricator .............................................................................................. 33

Simulations and Measurements ................................................................................................. 34

Looking ahead to Measurements............................................................................................. 34

Simulation Models.................................................................................................................... 35

Simulating the channel ............................................................................................................ 35

A look at simulations................................................................................................................ 36

Stripline Simulations ............................................................................................................... 38

Reference Channel Simulation ................................................................................................ 39

Channel Simulation ................................................................................................................. 43

HSPICE Simulations................................................................................................................ 48

Conclusions................................................................................................................................... 51

iv

List of FiguresList of FiguresList of FiguresList of Figures

Figure 1 -- Connector pinout examined ...................................................................................... 17

Figure 2 -- Stripline shown with no anti-pads ........................................................................... 18

Figure 3 -- Stripline with anti-pads shown ................................................................................ 19

Figure 4 – Dielectric loss effect on stripline insertion loss........................................................ 23

Figure 5 -- Back-drilling example ............................................................................................... 26

Figure 6-- Example Hybrid construction .................................................................................... 27

Figure 7 -- Point-to-point routing with inherent skew .............................................................. 29

Figure 8 -- Point-to-point routing with inherent matching....................................................... 30

Figure 9 -- eHSD connector simulation ...................................................................................... 37

Figure 10 -- eHSD connector Sdd transmission ......................................................................... 37

Figure 11 -- eHSD connector crosstalk ....................................................................................... 38

Figure 12 -- Comparing Equation based Stripline to AWR Model............................................ 40

Figure 13 -- Cascaded reference channel model......................................................................... 40

Figure 14 -- Reference channel simulation vs. measured ......................................................... 41

Figure 15 -- Eye diagram of reference channel .......................................................................... 42

Figure 16 -- Measured eye on reference channel ....................................................................... 42

Figure 17 -- Backplane interconnect circuit model .................................................................... 43

Figure 18 -- Complete Backplane channel model with eHSD................................................... 44

Figure 19 -- Harmonic Balance simulation of AWR model at 3.125Gbps ................................ 45

Figure 20 -- Harmonic Balance of measured channel performance.......................................... 45

Figure 21 -- Harmonic Balance simulation of AWR model at 5 Gbps ...................................... 46

Figure 22 -- Harmonic Balance of measured channel performance at 5Gbps.......................... 46

Figure 23-- Harmonic Balance simulation of AWR model at 6.5 Gbps .................................... 47

Figure 24 -- Harmonic Balance of measured channel performance.......................................... 47

Figure 25 -- HSPICE Circuit model of V4 MGT......................................................................... 48

Figure 26 -- HSPICE node measurements ................................................................................. 49

Figure 27 -- PRBS pattern checking circuit ............................................................................... 50

Figure 28 -- PRBS eye diagram from HSPICE .......................................................................... 50

v

List of TablesList of TablesList of TablesList of Tables

Table 1 -- Tool Summary ............................................................................................................. 12

Table 2-- Typical connector parameters ..................................................................................... 15

Table 3 -- Relative cost of Materials ........................................................................................... 21

Table 4 -- Example Stripline Calculations ................................................................................. 24

Table 5-- Route lengths and skew ............................................................................................... 29

Table 6 -- Route lengths and skew matched............................................................................... 31

vi

Reference DocumentsReference DocumentsReference DocumentsReference Documents Xilinx High-Speed Serial Backplane Routing Tradeoffs Guide

GlossaryGlossaryGlossaryGlossary

Terms used throughout this document

Channel A differential pair and its complementary direction pair (Tx and Rx).

Lane Alternate naming for a channel. Sometimes referred to as x1, x2, x4,

x8 lane to indicate multiple lanes (channels) aggregated to carry data.

Pair Two signals each driven complementary (180 degrees out of phase).

Star A routing concept where all nodes attach to a single point (hub).

Hub The center of a star network.

Node One of many end points in a star network.

7

AbstractAbstractAbstractAbstract

This white paper covers the design process implemented at Xilinx for developing a high-

speed serial backplane to explore interconnects using a variety of connectors and PCB

materials.

It is intended for persons needing to design a high-speed backplane but are either new to

backplane design or who have only worked at sub-1Gbps speeds. Tools, methods, tradeoffs

used during the development of the backplane are discussed.

8

OverviewOverviewOverviewOverview

The backplane is the backbone in a variety of systems deployed world-wide. Backplanes are

used in telecom equipment, industrial controllers, flight-control systems, computing systems,

and more. Backplanes are not a customer upgrade option for many reasons which forces the

backplane to consider today and tomorrow’s technologies or land in a scrap-pile as an

obsolete piece of junk.

The challenge today is how to make a working backplane without pouring lots of unnecessary

resources and costs into the design. This document introduces the reader to the most

important aspects of backplane design and offers suggestions on what to focus on when

making decisions.

Before you startBefore you startBefore you startBefore you start

Before starting the design of a backplane the following items, at a minimum, will need to

have been decided:

• Topology to use

• Minimum slot-pitch that can be tolerated

• Number of signals that need to be routed between slots

• Number voltages that need to be supplied to line cards

• Maximum thickness of line card

• Minimum and maximum thickness of backplane

• Link budget

• Specifications that need to be followed.

9

Designing the BackplaneDesigning the BackplaneDesigning the BackplaneDesigning the Backplane

During the design of the High Speed Serial Backplane, the following considerations were

taken under consideration:

• Size

• Cost

• Number of layers

• Number of slots

• Materials

• Connectors

• Performance

• Interconnect topology

Although this particular backplane did not have to conform to a particular standard, most

backplanes are standards based. The standard dictates the type of connector, pinout, and

thickness whereas with a custom backplane the designer makes these choices.

Cost factorsCost factorsCost factorsCost factors

Some of the more important factors that affect the overall cost of a backplane are:

• Connector type and quantity

• Number of layers

• Material types and thicknesses

• Panel size and utilization

• Number of drill holes and tolerance

• Back-drilling

• Edge plating

10

ConnectorsConnectorsConnectorsConnectors

There is no one connector that performs equally well for all backplanes. As stated

previously, if the backplane is standards based then the connector and mechanical data is

defined. However, when choosing a connector for a backplane it is important to consider the

following:

• Signal density

• Signal crosstalk

• Slot pitch

• Cost

Sometimes a design can take advantage of a mix of connectors to achieve the needs of the

system. The High Speed Serial Backplane for example uses the following connectors:

• Amphenol-TCS eHSD

• Tyco/Erni HM-Zd (ATCA Zone 2)

• Hard Metric 2mm (Type B with shield)

11

ToolsToolsToolsTools

With today’s interconnect speeds it is imperative to do channel simulations to determine

whether or not the channel is going to work before the design enters the lab. Table 1 lists a

number of tools that are considered to be capable of analyzing channel structures. This list

is by no means complete and is provided as a general summary.

Engineers have always been faced with having to make tradeoffs between accurate

simulation results and getting the product released. The challenge today is to make the

product work today for tomorrow and keep the simulations simple but accurate.

In practice, a mixture of several tools is needed to accomplish proper channel modeling.

Time domain analysis is needed since we are concerned about transient effects on the source

signal and its arrival at the receiver. Frequency domain analysis is also needed for a

landscape view of how the interconnect channel responds over a wide band of frequencies.

Element Domain Tool/Model type Comments

Package Freq 3D Very good for analyzing multi-port structures in package. Must consider DC

point interpolation issues

Time HSPICE/

IBIS

Package RLGC must be provided by vendor either by transform of freq.

domain model

Trace Time RLGC Fairly accurate for most simulations

Freq 2D Well known closed-form equations exist. Surface roughness not usually

considered.

Connector Time RLGC Simple model that may provide some crosstalk info but not effective at links

>2.5Gbps.

Freq 3D Analyzes all pin-pin effects for accurate crosstalk and delay models. Suffers

from DC interpolation issues.

Via Time RLGC Very highly model dependent since return current path is not typically

expressed.

Freq 3D Can provide very accurate results but proper modeling and port assignment

needed.

12

Table Table Table Table 1111 -------- Tool SummaryTool SummaryTool SummaryTool Summary

ToolToolToolTool TypeTypeTypeType DescriptionDescriptionDescriptionDescription Ease of UseEase of UseEase of UseEase of Use AccuracyAccuracyAccuracyAccuracy CostCostCostCost

Ansoft Mixed 2.5D,

3D

Ansoft tool

suite:

Designer SI

Nexxsim

SI Wave

HFSS

HFSS –

very

complex

Considered

very

accurate

when 3D is

used

$180,000

CST 3D CST

Microwave

Studio

High >99% TBD

Mentor IBIS with

2D &

frequency

solver

GigaHertz

HyperLynx

allows a mix

of IBIS,

HSPICE,

and S-

parameters

to be used

High Probably

>90%

$60,000

AWR 2.5D and 3D

planar RF

simulator

with

HSPICE

Microwave

Office: Uses

a mix of

closed-form

models and

2.5D EM

simulation

to solve

transmission

line

problems

High Probably

>95%

TBD

13

ToolToolToolTool TypeTypeTypeType DescriptionDescriptionDescriptionDescription Ease of UseEase of UseEase of UseEase of Use AccuracyAccuracyAccuracyAccuracy CostCostCostCost

Cadence IBIS with

2D &

frequency

solver

Similar to

Mentor’s

tool. Fully

integrated

into PCB

layout tool

Mid-High Probably

>90%

$60,000 for

1 year

license.

HSPICE Time

domain

simulation

with W-

element

transmission

line models

Needed for

any time

domain

analysis

with

encrypted

HSPICE

Easy-Mid Model

dependent

but can

approach

100%

TBD

Agilent

ADS

2.5D, 3D

planar

Uses a mix

of closed-

form models

and 2.5D

EM

simulation

to solve

transmission

line probles

Mid-High Probably

>95%

TBD

14

Tools selectedTools selectedTools selectedTools selected

For the Xilinx High-Speed serial backplane project, AWR’s Microwave Office software with

HSPICE option was ultimately chosen. This tool allowed Xilinx to quickly build frequency

domain models of the channel interconnects and use 3rd party supplied s-parameter models

when needed for the via and connector elements.

Using the HSPICE feature of AWR, a working interconnect model using Xilinx factory

supplied HSPICE encrypted models of the Virtex-4 MGT drivers was created. HSPICE

contains an embedded s-parameter transform function in it. Since the channel models were

created as a frequency domain model along with the connector models, the transform feature

was needed to examine channel performance in the time domain.

Layout ToolsLayout ToolsLayout ToolsLayout Tools

Since the layout portion of channel design is as critical as the modeling, it is necessary to

choose a layout tool and process that works well with backplane design and allows easy-to-

use constraint features.

For the Xilinx High-Speed Serial backplane project Cadence’s PCB Design CIS Studio was

used. This includes both the OrCAD CIS schematic editor and Allegro PCB layout tool. The

tool suite supports both forward and back annotation which allows designers the ability to

apply design rules from either tool and annotate the changes to the other tool. Another nice

feature supported by this tool suite is cross-probing which is very helpful for finding possible

netlist issues.

With an upgraded license users can seamlessly integrate the Cadence PCB SI Explorer tool

to do full channel analysis. This was not done during the High-Speed Backplane project.

15

TradeoffsTradeoffsTradeoffsTradeoffs

The following sections introduce the most significant items which need to be considered when

designing a backplane.

This section examines how the following items affect both cost and performance:

• Connector type

• Connector pinout

• Material

• Routing geometry

Connector typeConnector typeConnector typeConnector type

Once the topology is known, a signal list between nodes and hubs can be established. The

following tradeoffs work equally well on high-speed signals and low-speed signals.

Choosing a connector will define:

• Minimum slot pitch (horizontal)

• Number of pairs per inch (vertical)

• Inherent Crosstalk

• Cost/pair

• Estimated maximum signaling speed

Table 2 lists some industry accepted connectors for backplane design.

Table Table Table Table 2222-------- Typical connector parameters Typical connector parameters Typical connector parameters Typical connector parameters

Connector Number of pairs

pairs/sq in

Min Slot Pitch

Total vias Adv performance

Cost per mated pair Xtalk (FEXT), freq Notes

Amphenol xCede 24 27.5-82 25.4mm 96 20Gbps N/A -50dB, 5 GHz

Shown for reference only, not used

Amphenol eHSD 30 N/A 22mm 120 10 Gbps $1.76 -25dB, 5GHz

Average price based Xilinx BOM

Tyco HMZd 40

20, 30, 40 25.4mm 120 6.5 Gbps $0.32 N/A

Standard ATCA Zone 2 connector pair, 40 pair inch shown

2mm** 12 N/A 17mm 133 <1 Gbps $1.28 N/A

**Assumes Tyco-Amp high-isolation pinout per guidelines

N/A = not advertised

16

Connector pinoutConnector pinoutConnector pinoutConnector pinout

There are several key points to consider when assigning pinouts to connectors:

• Row-Row crosstalk

• Signal phase

• Routing channels

• Pin-pair skew

• Pair-pair skew

Row-Row crosstalk will always occur so it is best to consider what the signal direction is: Tx

or Rx. Tx-Tx pairing results in the far-end crosstalk at the receiver being diminished. Tx-Rx

pairing causes near-end crosstalk at the receiver which increases the noise at the receiver

diminishing SNR.

Pin-pair phase is important and is based mostly on routing strategy. It is highly

recommended that a route study be performed before assigning final pinouts. It is very easy

to induce a natural phase-error by reversing a pos-neg pin pair assignment.

Depending on how signals are distributed from slot to slot, the total number of routing

channels has to be considered. Again, a route study is really needed so that a pin

assignment can be made which minimizes total layers and avoids an unnecessarily high-cost

backplane.

To avoid unintentional skew, keep like-signals on the same connector column pair. This is

not a strict rule but a guideline.

Figure 1 below depicts each of these important points.

17

Figure Figure Figure Figure 1111 -------- Connector pinout Connector pinout Connector pinout Connector pinout examinedexaminedexaminedexamined

It can be seen in Figure 1 that J122 (a hub in a dual-star network) has its Tx channels

arranged in a row-row configuration to prevent its own transmit signals from talking into its

own receiver. This becomes unavoidable at the junction (in J122) where the blue signals

occur next to the red (Rx) signals. At the top of J123, AB and CD are circled showing the

most desirable arrangement of Tx and Rx pins. This also forces a separate layer (stripline) to

be used for Tx and Rx again increasing isolation. Above J124 the two Tx inputs are

separated by five rows (AB10 and AB5). This was done to optimize routing channels (hub

with five (5) nodes). This allows all of the other node signals to pass through this connector

on their way to their node. Other combinations of Tx hub-node signals can be made to work

as well but this shows one viable strategy.

AntiAntiAntiAnti----padspadspadspads

Anti-pads are an unavoidable consideration when designing a backplane. Most connector

vendors selling connectors to operate at 3Gbps and above have already considered what anti-

pads should work best with their connector. What needs to be considered is the overall

thickness of the backplane and the stripline geometry.

The following diagrams look at stripline routing without anti-pad consideration and then

with anti-pad consideration.

18

Figure Figure Figure Figure 2222 -------- Stripline shown with no anti Stripline shown with no anti Stripline shown with no anti Stripline shown with no anti----padspadspadspads

19

Figure Figure Figure Figure 3333 -------- Stripline with anti Stripline with anti Stripline with anti Stripline with anti----pads shownpads shownpads shownpads shown

Choosing the stripline geometry without considering the anti-pad design is bad design

practice and will impact the design’s performance. Be sure to examine the anti-pad sizes

before deciding the stripline geometry. And do not forget that manufacturing tolerances

allow mis-registration of layers up to 5 mils. This can impact the stripline impedance as one

leg routes over the anti-pad opening unintentionally.

Note: If you are considering your own anti-pad design you probably have access to 3D planar

electromagnetic simulation tools and can accurately predict the influence of the anti-pad.

Without 3D tools, don’t risk guessing your anti-pad design – work with your connector

vendor and have them help you optimize their anti-pad for your application.

20

MaterialMaterialMaterialMaterial

When choosing a backplane material for your design, you should consider the following

aspects:

• Cost

• Dielectric constant

• Dissipation factor

• Weave type

• Resin content

Before serial channel speeds started going above 2.5Gbps or so, most designers were not too

concerned with material choice. In fact, there is a lot of press out there from the silicon

vendors and connector vendors showing they have channels working FR4 at 36”! All of the

aspects of your material must be considered before the final material choice is made.

Material choice will have a very dramatic impact to your design as it impacts:

• Producibility

• Processing cost

• Thickness

• Reliability

Table 3 lists a variety of backplane materials commonly used for backplane design. This is a

partial sampling of data provided on the websites of these material vendors. The table shows

how fabricators factor the cost of the finished product based on the laminate and how the

laminate supplier cost factors affect the fabricator’s cost. There are many more variables in

the fabrication that affect the cost so be sure to study these factors with your fabricator.

21

TableTableTableTable 3333 -------- Relative cost of Materials Relative cost of Materials Relative cost of Materials Relative cost of Materials

MaterialMaterialMaterialMaterial DkDkDkDk DfDfDfDf WeaveWeaveWeaveWeave Resin Resin Resin Resin

contentcontentcontentcontent

Relative Relative Relative Relative

Cost Cost Cost Cost

FactorFactorFactorFactor

(Fab)(Fab)(Fab)(Fab)

Relative Relative Relative Relative

Cost FactorCost FactorCost FactorCost Factor

(Laminate)(Laminate)(Laminate)(Laminate)

Nelco

4000-13SI

3.14-

3.29

.008 106, 1080, 2116 53-75% 1.4 1.5

Nelco

4000-13

3.31-

4.24

.009 106, 1080, 2113,

2116, 7628

38-58% 1.2 1.0

Nelco

4000-13EP

3.31-

4.20

.009 106, 1080, 2113,

2116, 7628

38-68% 1.2 1.1

Nelco

4000-6

3.64-

4.26

.022 106, 1080, 2113,

2116, 7628

39-69% 1.0 0.7

Isola

FR408

3.65 .012 106, 1080, 2113,

1652, 7628

N/A 1.2 NA

Isola

FR406

3.80 .020 106, 1080, 2113,

1652, 7628

N/A 1.0 NA

Isola 620 3.61 .008 106,1080,2113,3070,

2116,3313,1652

N/A 1.4 NA

In Table 3, one can see that by calling out a material by name is not sufficient. The material

comes in a variety of glass weave types and resin contents which affect the overall dielectric

constant. There is some variability in the dissipation factor but this data is not typically

published by the vendors.

Picking the material is a multi-variable problem. The loss factors (Dk, Df) need to be studied

to determine what amount of the link budget is assigned to backplane loss. Since overall cost

is a determining factor it is not as easy as just picking the ‘best’ material available.

22

Materials chosenMaterials chosenMaterials chosenMaterials chosen

For the High Speed Serial backplane project, a variety of different material types and

conductor geometries were studied to examine the effects of copper width and dielectric loss.

The following materials were chosen for the backplane to contrast their performance:

• Nelco 4000-13SI

• Nelco 4000-13

• Isola FR408

This is somewhat atypical for most backplanes but a hybrid combination of low-cost

materials for low frequency signals and power and a high-performance (high-cost) material

for selected signals is not uncommon.

GeometrGeometrGeometrGeometryyyy

The stripline geometry chosen was based on many parameters but one dominant parameter

was the anti-pad spacing between connector columns. In Figure 3 above, the anti-pads on

the eHSD connector are shown and how far they encroach into the routing zone. The Xilinx

backplane did not use any stripline geometries that would have protruded into the anti-pad

region. By examining the physical attributes of the connector and anti-pads the maximum

conductor edge-to-edge distance can be derived. The following table examines the eHSD

physical dimensions:

MeasurementMeasurementMeasurementMeasurement milsmilsmilsmils

Pin-Pin column spacing 78.74

Pin Anti-pad size 54

Remaining plane copper 24.74

Mis-registration guard band 5

Final edge-edge maximum 19.74

It can be seen that only 19.74 mils +/- some tolerance remains for the stripline conductors.

“Some tolerance” is noted because a 5 mil guard-band has already been applied to the

numbers and if additional routing width is needed it can be borrowed from this guard band.

At this point the maximum spacing of the outside edges of the conductors is known but not

how thick or wide they need to be. This is where simulation can really assist with the

design.

23

Dielectric LossDielectric LossDielectric LossDielectric Loss

It is important to consider the Df (tan d) of the material when doing high-speed serial links.

Figure 4 shows an arbitrary “100 ohm” differential pair (6 inch) insertion loss variation when

the dielectric loss of the material is swept from 0.008 to 0.016. The figure shows that at

5GHz, the difference between Df=0.008 and Df=0.016 is approximately 1dB. This may not be

significant enough to affect the particular link but needs to be a tradeoff against cost vs.

performance.

0 2000 4000 6000 8000 10000

Frequency (MHz)

Transmission

-6

-5

-4

-3

-2

-1

0

p5

p4

p3

p2

p1

DB(|S(3,1)|)Fixed_Er_Variable_Df

p1: Tan_d = 0.008

p2: Tan_d = 0.01

p3: Tan_d = 0.012

p4: Tan_d = 0.014

p5: Tan_d = 0.016

Data from AWR Microwave Office

Figure Figure Figure Figure 4444 –––– Dielectric loss effect on stripline insertion lossDielectric loss effect on stripline insertion lossDielectric loss effect on stripline insertion lossDielectric loss effect on stripline insertion loss

Once material choice has been made, the stripline geometry can be chosen. Differential pairs

are defined as ‘loosely coupled’ or ‘tightly coupled’. It is unlikely that sufficient routing

resources exist to consider loosely coupled striplines (where Zodd ≈ Zeven). In the current

example, it is practically impossible to build differential pairs that are loosely coupled.

24

ThicknessThicknessThicknessThickness

At this point, a maximum distance of the outside to outside of our conductors had been

determined but not the width and spacing of the conductors. Here practical limits guide us.

For example, it does not make sense to call out 3 mil lines and 13 mil spacing even though

that fits within our design limits.

Fabricator etching requirements play a large part of selecting a conductor width that works

best. If spacing rules are set to 5 mils minimum then the largest trace width possible can be

calculated along with its effects on overall plane spacing. In this the stripline edge-to-edge is

19.74mils -5mils=14.74 mils. Dividing by 2 gives approximately 7 mils per conductor. If 5

mils is considered to be the minimum etch width, the variation of line widths and spacing

that achieve 100 ohms and the resultant plane spacing (height) can be calculated.

Table Table Table Table 4444 -------- Example Stripline Calculations Example Stripline Calculations Example Stripline Calculations Example Stripline Calculations

(value in mils)

(Er=3.38, Df=0.008), 1oz Cu

Width Spacing Height between planes

5 5 25

6 5 38

7 5 100*

7 6 30

5 6 18

5 7 15.6

5 8 14.6

5 9 14

*limit in simulation reached

If each of the geometries in Table 4 results in 100 ohm differential pairs, then how does one

choose? There is not one answer to this. However when the overall backplane thickness

limits is considered, there will only be one or two of the practical combinations. If the overall

backplane thickness can still not be achieved then the following choices need to be

reconsidered:

• Changing conductor thickness

• Changing dielectric material

• Changing backplane thickness limits

25

• Choosing a connector with different geometries to allow more spacing for routes

The material chosen will decide one of the variables in the next decision point: thickness.

The overall thickness will be affected by the kinds of glass weaves chosen. It is wise to

include a ‘fill’ layer in the stackup to adjust the overall thickness of the backplane so that the

stripline geometry is not inadvertently affected.

Laminate SkewLaminate SkewLaminate SkewLaminate Skew

An effect known as ‘laminate weave skew’ or some sinister sounding skew effect is showing

up in literature. Xilinx did examine this effect and in fact the problem does exist and there is

no certain fix to the problem right now. Check the current literature to see if this problem is

being resolved. First, what is the effect? Read on if you are not familiar; otherwise skip to

the next section.

The laminate skew effect is an effect that can be measured where one leg of a differential

pair has a different propagation velocity than the other pair. This results in signal eye-

closure ultimately when hit by the effect. Measurements are widely ranging but it is not

atypical to see 1.5-2.5ps per inch of skew. Over 20 inches, this can easily add up to 50ps of

skew. For a given link, this amount of laminate skew can impact link performance.

To help minimize the effect, the glass weave chosen vs. the copper conductor width and

spacing seems to have the greatest effect. In simple terms, what is happening is that one leg

is falling into a ‘valley’ where the fiberglass strands are separated. This area tends to be

resin-rich and has an effective Dk lower than the glass-rich areas.

There are several patented approaches to fixing the problem. The reader is encouraged to

investigate the patents applied to the mitigation of laminate skew. Several fabricators are

releasing new fabric weaves to help mitigate this issue as well.

BackBackBackBack----drillingdrillingdrillingdrilling

By now most engineers have heard of back-drilling. It is a post-fabrication step where the

rear of backplane vias are drilled to a controlled depth to minimize the remaining stub.

Figure 5 shows a pictorial view of back-drilling that was used on the Xilinx High-Speed serial

backplane project.

26

5.5mil

9.0mil

9.2mil

12.0mil

11.4mil

31.0mil

9.7mil

11.4mil

12.0mil

12.0mil

5.5mil

9.0mil

9.2mil

12.0mil

9.7mil

N4000-13

N4000-13

N4000-13

N4000-13

N4000-13

N4000-13

N4000-13

FR408

FR408

FR408

FR408

N4000-13si

N4000-13si

N4000-13si

N4000-13si

Sig1

Sig2

Sig3

Sig4

Sig5

Sig6

Stub

10mil

Stub

35mil

Stub

60mil

Stub

10mil

Stub

10mil

Stub

10mil

5.5mil

9.0mil

9.2mil

12.0mil

11.4mil

31.0mil

9.7mil

11.4mil

12.0mil

12.0mil

5.5mil

9.0mil

9.2mil

12.0mil

9.7mil

N4000-13

N4000-13

N4000-13

N4000-13

N4000-13

N4000-13

N4000-13

FR408

FR408

FR408

FR408

N4000-13si

N4000-13si

N4000-13si

N4000-13si

Sig1

Sig2

Sig3

Sig4

Sig5

Sig6

Stub

10mil

Stub

35mil

Stub

60mil

Stub

10mil

Stub

10mil

Stub

10mil

Figure Figure Figure Figure 5555 -------- Back Back Back Back----drilling exampledrilling exampledrilling exampledrilling example

Upon examination of Figure 5 it can be seen that Sig1 and Sig2 have longer stubs than the

other layers. This is because the pins used in backplanes are called “compliant” pins and

need a minimum z-axis depth for proper functionality. Check with your backplane connector

vendor to see how far the vias can be backdrilled and still function with the connector.

The need for back-drilling really depends on the application – it is not as simple as stating a

particular frequency needs backdrilling. In the above figure, it is obvious that Sig6 would

have a shorter stub naturally than Sig3 without back-drilling. 60 mil stubs can have

resonant effects above 5GHz which is the first harmonic of 10Gbps links or the second

harmonic of 5Gbps links. Back-drilling is not an absolute requirement even for these link

speeds but with other effects being consider most companies are quick to jump on back-

drilling before a full analysis has been performed to determine the system benefit. It is

highly recommended that simulations using quality microwave tools be used to make

decisions before checking the “back-drill” check-box on the fab drawing.

27

Hybrid ConstructionsHybrid ConstructionsHybrid ConstructionsHybrid Constructions

Another consideration for backplane design is to reserve only a few layers for high-speed low-

loss routing. There is no need to specify higher-cost materials such as Rogers 4350, Isola 620

or Nelco 4000-13SI when FR406 would work.

An example of a hybrid backplane stackup is shown in Figure 6 below. Here the low-loss

signal layers (Signal Layer 3, Signal Layer 4) using Nelco 4000-13SI have been placed in the

middle of the backplane. Other lower cost materials can be utilized on remaining layers to

reduce cost.

.0055

.012

.0114

.012

.0092

.009

.0092

.0097

.012

.031

.0114

.0097

.012

.009

.0055

0.1875

+/- 10%

106 / 1080

2116 (2 PLY)

2116 (2 PLY)

1080 (2 PLY) / 7628

2113 / 1080 / 2113

2116 (3 PLY)

106 / 2116 (2 PLY)

2113 / 7628 (4 PLY)

2116 (2 PLY) / 106

2116 (3 PLY)

2113 / 1080 / 2113

1080 (2 PLY) / 7628

2116 (2 PLY)

2116 (2 PLY)

106 / 1080

N4000-13 FILL

N4000-13 CORE

N4000-13 FILL

FR408 CORE

FR408 FILL

N4000-13si CORE

N4000-13si FILL

N4000-13 CORE

N4000-13si FILL

N4000-13si CORE

FR408 CORE

FR408 FILL

N4000-13 FILL

N4000-13 CORE

N4000-13 FILL

Signal Layer 1

Signal Layer 2

Signal Layer 3

Signal Layer 4

Signal Layer 5

Signal Layer 6

Surface Pads only

Surface Pads only

Figure Figure Figure Figure 6666-------- E E E Example Hybrid constructionxample Hybrid constructionxample Hybrid constructionxample Hybrid construction

Edge plating and Edge plating and Edge plating and Edge plating and ground via stitchingground via stitchingground via stitchingground via stitching

There are several techniques to mitigate EMI caused by energy generated by power plane

resonances and signals routed close to the edge of the backplane.

Edge plating is not necessarily expensive. Be sure to check with your fabricator on the cost

implementing edge plating. If your fabricator has little experience in edge plating you will

find this a costly venture and perhaps ground stitching is a better alternative.

Ground stitching as defined here implies the use vias placed around the perimeter of the

backplane which connect all of the internal ground planes together. The spacing between the

vias helps define the attenuation frequency. A field-solver is typically required for final

28

determination but in practice randomly placing vias between 50 and 100 mils apart along the

edge works for backplane designs.

Some things to consider before applying either one of these techniques is whether or not you

have ground planes extending to the edge of the backplane and will the edge plating or vias

contact the metal structure of the backplane unintentionally.

Routing Routing Routing Routing SkewSkewSkewSkew

Here routing skew is defined as intra-pair skew and inter-pair skew. Intra-pair skew is

defined as the route difference between the copper trace for the positive leg and the negative

leg. Inter-pair skew is defined as the route difference between one pair and another.

It is tempting to over-constrain a design and request that the skew between P & N legs be

zero or skew between pairs be zero. This is both unnecessary and costly.

What is important is to make an interconnect budget and determine the maximum allowable

skew for overall interconnect. Be sure to think about the laminate skew effects as well if

your design is operating above 5Gbps.

Smart ThinkingSmart ThinkingSmart ThinkingSmart Thinking

There is significant literature presenting routing methods to equalize skew. Smart thinking

is your best friend when thinking about minimizing skew. Next two interconnect routes are

examined and the result of good up-front planning prevents additional wasteful routing

methods to equalize skew.

In the following figure there are two node slots that have four (4) pair interconnecting the

two slots. The goal was route the four pair as 6” matched pair.

29

Figure Figure Figure Figure 7777 -------- Point Point Point Point----totototo----point routing with inherent skewpoint routing with inherent skewpoint routing with inherent skewpoint routing with inherent skew

Table Table Table Table 5555-------- Route lengths and skew Route lengths and skew Route lengths and skew Route lengths and skew

RouteRouteRouteRoute PosPosPosPos (mils) (mils) (mils) (mils) NegNegNegNeg (mils) (mils) (mils) (mils) DiffDiffDiffDiff (mils) (mils) (mils) (mils)

J117 AB7 5437 5347 90

J117 AB6 5912 5822 90

J117 AB5 6375 6285 90

J117 AB4 6707 6797 90

Although at first glance the routes appear to be following the same path there are some

inherent problems with these routes. This is where advice in existing literature recommends

serpentining and corner-jogging to correct the problem. Table 5 shows the resulting path

lengths of each of the four routes above.

30

Next the same routes with simply a direction change and right-turn/left-turn balancing are

examined.

Figure Figure Figure Figure 8888 -------- Point Point Point Point----totototo----point routing with inherent matpoint routing with inherent matpoint routing with inherent matpoint routing with inherent matchingchingchingching

31

Table Table Table Table 6666 -------- Route lengths and skew Route lengths and skew Route lengths and skew Route lengths and skew matched matched matched matched

RouteRouteRouteRoute PosPosPosPos (mils) (mils) (mils) (mils) NegNegNegNeg (mils) (mils) (mils) (mils) DiffDiffDiffDiff (mils) (mils) (mils) (mils)

J117 AB7 5998 5998 0

J117 AB6 6000 6002 2

J117 AB5 6000 6002 2

J117 AB4 6000 6000 0

Now the goal of minimizing intra-pair skew and inter-pair skew has been accomplished by a

simple change in routing approach. If you examine Figure 8 it can be seen that for every left

turn there is a right turn and the pairs that are naturally pinned top to bottom are routed

top to bottom.

Think about how to smartly route before wasting a lot of time with a bad plan.

Potential trapsPotential trapsPotential trapsPotential traps

• Line card material is different from backplane

• Backplane Signal layers use different material

• Z-axis skew

• Connector skew

• Laminate Weave effect

When doing a link budget don’t forget that different materials and even different material

thicknesses can cause velocity differences that result in skew. Be sure to check with your

fabricator to find out if they have measured the exact combination of laminates prescribed

and cross-check their data with the laminate supplier. Xilinx has found that the techniques

used to measure Er vary from vendor to vendor and particular expectations may not be met

upon delivery.

Another oversight is the z-axis distance the signal must travel down the via when entering

and exiting a connector. An upper layer can be 15ps away from a lower layer which

introduces 30ps inter-pair skew without much thought. And within the connector there will

be intra-pair skew and additionally if one pair is routed on AB and another on pair CD, for

example, there will be inter-pair skew because of the physical pin lengths inside the

connector.

It must be repeated that you caution needs to be exercised if the link budget does not include

32

both intra-pair and inter-pair skew because of laminate weave related issues. Do not worry

about how well the layout team matches pairs to 5 mils (800 femtoseconds) and then ignore

laminate skew -- the design is destined to fail.

33

Things to think aboutThings to think aboutThings to think aboutThings to think about

• Voltages

• Creepage/clearance

• UL requirements

• Return currents

• Soldermasks

• Silkscreens

• Mixing connector families

• Guide pins

• Mechanical holes

• Grounding

• Test and Measurement

The bulleted list above is a partial list of items that must be considered when designing a

backplane. This document can not begin to touch on the importance of these items.

Everything in the design interacts with everything else! Plan accordingly. Read the

specifications. If the budget allows, build some test vehicles to experiment with laminates,

vias, anti-pads, back-drilling, etc…

Lastly, be sure to plan for some test methodology for your backplane. Is a specialized test

card needed to validate the design? What about snooping backplane signals in a working

system? Be sure to budget for this and the time it will take to thoroughly test the backplane

so your system will be a success.

Contacting your PCB fabricatorContacting your PCB fabricatorContacting your PCB fabricatorContacting your PCB fabricator

It can not be over-stated that you must develop a relationship with a trusted PCB fabricator

before starting routing. Your fabricator needs to review your proposed stackup and confirm

that they can build your backplane with the chosen materials and geometries. Too often this

author has seen where hundreds of differential pairs had to be re-routed at the last minute

when the gerbers arrived at the fabricator and they could not build to the specified

impedances.

34

Simulations and MeasurementsSimulations and MeasurementsSimulations and MeasurementsSimulations and Measurements

With any simulation the quality of the results depends on the quality of the models and the

realism of the circuit being simulated. It is not for example atypical to ignore parasitics in a

simple circuit model to make a simulation go faster. Inserting a simplified model of a

component for simulation because a real model is not available or might take too long to

simulate is not uncommon.

In a backplane channel simulation you need to determine what level of accuracy is needed to

have confidence that your channel will be usable at the data rates and with the data patterns

being sent. And after simulation comes measurement. It is imperative to have a

measurement and validation of the final backplane.

Looking ahead to MeasurementsLooking ahead to MeasurementsLooking ahead to MeasurementsLooking ahead to Measurements

Measurement and validation of backplane performance is a final proof of the design. Some

measurement techniques to consider are:

VNA 4-port Limited cross-talk measurements. Needs rigidly fixed SMA attachment.

VNA 12-

port

Improved channel cross-talk measurements. Needs rigidly fixed SMA

attachment.

TDR

TDR

One

diff

head

Can be used with hand-held differential probe but typically needs rigid

SMA attachment.

TDR

TDR

Two

diff

Head

Offers single-ended, differential, and reciprocal measurements. Used with

post-processing software this data can be transformed to s-parameters.

Oscope Limited bandwidth. Very useful for ‘looking’ at eye patterns generated

across channel. Can monitor live system

Depending on available test equipment a method for measurement of the backplane channel

needs to be considered. This may include a passive test card which can be plugged into the

backplane and provide SMA connections to the test equipment.

35

Simulation ModelsSimulation ModelsSimulation ModelsSimulation Models

As stated earlier Xilinx chose to use AWR’s Microwave Office software with HSPICE option.

Good s-parameter models of the backplane connectors and mounting vias were needed to

accurately simulate the various channels. Accurate stripline models of the interconnects

were done using Microwave Office. It was quickly found that the accuracy of the connector

models quickly dominated the results of the channel interconnect.

For this product development, connector vendors were asked to supply accurate models of

their connectors. The importance of this can not be understated if you do not have the ability

to simulate your connectors with 3D EM simulation. Developing a good working relationship

with your connector vendor is vital to the success of your project. Make sure they are

committed to helping you get good simulation results.

Simulating the channelSimulating the channelSimulating the channelSimulating the channel

The approach taken for simulating the channel was to generate each of the building blocks

that made up our system interconnect model, simulate and verify each model independently,

cascade the building blocks together and then simulate the complete interconnect. Whenever

a vendor supplied model was used it was cross-checked with the simulation results from the

vendor to make sure the models were in agreement with the results before proceeding.

After cascading the blocks together, AWR was used to perform frequency domain analysis of

the channel insertion loss (Sdd21) and crosstalk (Sdd13, Sdd23). Since the channels were

symmetrical, the channel was naturally reciprocal (Sdd21=Sdd12) and likewise for the NEXT

and FEXT signals.

When the entire channel model has been constructed, the channel performance can be

verified against any specification requirements if the specification includes limits for

crosstalk and insertion-loss across frequency. The IEEE 802.3ap specification is one such

specification that provides frequency based channel requirements.

AWR can generate a PRBS pulse-train and simulate it natively using a harmonic balance

approach. The results can be displayed in an eye-diagram format which tends to be the

metric that most people use for determining overall channel performance.

Lastly, the full system interconnect from MGT transmitter to MGT receiver was simulated in

HSPICE. Xilinx provides HSPICE design kits for customers which can be used in AWR.

36

With the HSPICE models the amount of pre-emphasis and receiver equalization can be

varied and channel response “seen” in near real-time.

A look at simulationsA look at simulationsA look at simulationsA look at simulations

As stated earlier, each piece of the backplane channel was simulated and analyzed before

cascading that piece with other pieces of the backplane. This way any setup or model data

problems could be identified before attempting to churn out an entire channel.

Here in Figure 9 the eHSD connector verification circuit model is shown. Using AWR’s

element library the stimulus was converted to differential mode stimulus since the connector

was being stimulated with differentially driven outputs. In the center of the figure is a

black-box which contains the s-parameter data supplied by Amphenol-TCS for their eHSD

connector.

Next the frequency is swept from approximately 0Hz to 20GHz to view the Sdd differential

transmission of each of the signal pairs in the connector. The resultant sweep is shown in

Figure 10. By examining this graph it can be seen that the pairs are well matched out to

15GHz which should be well beyond the backplane channel needs. Above 15GHz one can

begin to see some irregularities and resonances which may be measurement induced or real.

Most of this will disappear once the backplane vias are connected to the channel.

37

Figure Figure Figure Figure 9999 -------- eHSD connector simulation eHSD connector simulation eHSD connector simulation eHSD connector simulation

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM1

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM2

LOADID=Z1Z=25 Ohm

LOADID=Z2Z=25 Ohm

LOADID=Z3Z=25 Ohm

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM3

LOADID=Z4Z=25 Ohm

LOADID=Z5Z=25 Ohm

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM4

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM5

LOADID=Z6Z=25 Ohm

LOADID=Z7Z=25 Ohm

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM6

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM7

LOADID=Z8Z=25 Ohm

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM8

LOADID=Z9Z=25 Ohm

LOADID=Z10Z=25 Ohm

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM9

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM10

LOADID=Z11Z=25 Ohm

LOADID=Z12Z=25 Ohm

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM11

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM12

F5

E5

D5

C5

B5

A5

F6

E6

D6

C6

B6

A6

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

SUBCKTID=S1NET="EHSD8_Connector_model"PORT

P=1Z=100 Ohm

PORTP=2Z=100 Ohm

PORTP=3Z=100 Ohm

PORTP=4Z=100 Ohm

PORTP=5Z=100 Ohm

PORTP=6Z=100 Ohm

PORTP=7Z=100 Ohm

PORTP=8Z=100 Ohm

PORTP=9Z=100 Ohm

PORTP=10Z=100 Ohm

PORTP=11Z=100 Ohm

PORTP=12Z=100 Ohm

Schematic from AWR Microwave Office

Figure Figure Figure Figure 10101010 -------- eHSD connector Sdd transmission eHSD connector Sdd transmission eHSD connector Sdd transmission eHSD connector Sdd transmission

0 5 10 15 20

Frequency (GHz)

eHSD Transmission

-8

-6

-4

-2

0

DB(|S(7,1)|)Connector Ports






38

Figure Figure Figure Figure 11111111 -------- eHSD connector crosstalk eHSD connector crosstalk eHSD connector crosstalk eHSD connector crosstalk

0.1 5.1 10.1 15.1 20

Frequency (GHz)

eHSD NEXT and FEXT

-80

-60

-40

-20

0



Exploring further near-end crosstalk (NEXT) and far-end crosstalk (FEXT) generated by the

connector are examined. The example shown in Figure 11 shows that the arrangement of

pins as Tx and Rx later on will matter as signals that transit the connector in a column-to-

column arrangement will crosstalk through the connector. This coupled with backplane via

coupling may degrade performance.

Stripline SimulationsStripline SimulationsStripline SimulationsStripline Simulations

Next this paper examines a simple equation-based stripline formula versus a closed-form

model of a differential pair that is an element in the AWR library. Recall that stripline

impedance is a function of frequency and its characteristic impedance can be estimated by

the following formula:

where R is the ac+dc resistance of the etch, G represents the dielectric loss (tan_d or

R + jωL

G + jωC

39

dissipation factor), and L and C are the unit length inductance and capacitance of the line for

a 50 ohm line surrounded by a homegenous dielectric (Er). Once the loss per unit length was

computed, the linear loss factor was computed by multiplying the expected trace length by

the unit loss. This was done at each of the frequency harmonics (1x, 3x, 5x, 7x).

Using AWR’s data import feature, results from an Excel spreadsheet calculation of the

stripline performance were plotted on the graph shown in Figure 12 along with a frequency

sweep of the AWR closed-form model. The equation based model results and closed-form

model results agree with some expected error since they are not identical models. This

simulation gives confidence to the AWR model for going ahead with a cascaded system

model.

Reference Channel SimulationReference Channel SimulationReference Channel SimulationReference Channel Simulation

The first cascaded system model represents a 20” differential stripline and SMA connectors.

This line was constructed and measured on the High Speed Serial Backplane project so the

stripline performance could be verified over a range of materials. Once the backplane was

actually measured it became obvious that the model for the SMA connector was too

simplistic. Using the tuning feature in AWR, the values of inductors and capacitors were

tuned to get close matching of the SMA performance in the time domain. Next the

interconnect was swept in the frequency domain plotted against the measured s-parameter

data from the VNA. The results are shown in Figure 14.

40

Figure Figure Figure Figure 12121212 -------- Comparing Equation based Stripline to AWR Model Comparing Equation based Stripline to AWR Model Comparing Equation based Stripline to AWR Model Comparing Equation based Stripline to AWR Model

0.01 2.01 4.01 6.01 8.01 10

Frequency (GHz)

Calc vs AWR Diff

-20

-15

-10

-5

0

DB(|S(3,1)|)Composite 20 in Stripline

PlotCol(1,2)n4000_13si

Figure Figure Figure Figure 13131313 -------- Cascaded Cascaded Cascaded Cascaded reference channel reference channel reference channel reference channel modelmodelmodelmodel

CAPID=C1C=ViaCap pF

CAPID=C3C=ViaCap pF

INDID=L1L=ViaInd nH

INDID=L2L=ViaInd nH

INDID=L4L=ViaInd nH

INDID=L3L=ViaInd nH

SLINID=SL2W=15 milL=10 mil



SSUBEr=3.54B=98 milT=12 milRho=1Tand=0.009Name=SSUB1


CAPID=C2C=ViaCap pF

CAPID=C4C=ViaCap pF

INDID=L5L=ViaInd nH

INDID=L6L=ViaInd nH

S1LINID=TL5W=12 milL=LaunchLen milAcc=1

S1LINID=TL6W=12 milL=LaunchLen milAcc=1

RESID=R1R=0.2 Ohm

RESID=R2R=0.2 Ohm

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM1

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM2

SLINID=SL5W=15 milL=AptLen mil




W1

W2

1

2

3

4

SUBCKTID=S1NET="Composite 20 in Stripline"

PORTP=1Z=Zdiff Ohm

PORTP=4Z=Zcom Ohm

PORTP=2Z=Zcom Ohm

PORTP=3Z=Zdiff Ohm

ViaInd=0.254ViaCap=0.273LaunchLen=275AptLen=99

41

Figure Figure Figure Figure 14141414 -------- Reference channel simulation vs. measured Reference channel simulation vs. measured Reference channel simulation vs. measured Reference channel simulation vs. measured

0.01 5 10 15 20

Frequency (GHz)

Sig4 Reference Meas vs Actual

-80

-60

-40

-20

0

DB(|S(3,1)|)Sig4 Simulated

DB(|S(1,3)|)sig4 trimmed

DB(|S(3,1)|)Composite 20 in Stripline

In the above graph, the differential stripline without connectors is shown in pink. This

shows the best-case channel performance. The remaining two graphs compare the measured

data against the predicted channel performance. Above 16 GHz the reference model does not

match since the model is too simple. In this case it was decided the modeled performance

was acceptable since contribution above 15GHz are not significant.

Next the harmonic balance feature of AWR was used to generate PRBS signaling across the

channel (with SMAs). The results of the channel eye using this simple (but fast) approach to

channel modeling can be seen. The channel was measured using a Xilinx ML-421 MGT test

board to generate the source signal while driving through the channel and into an Agilent

oscilloscope. The measured eye is shown in Figure 16.

42

Figure Figure Figure Figure 15151515 -------- Eye diagram of reference channelEye diagram of reference channelEye diagram of reference channelEye diagram of reference channel

0 0.1 0.2 0.3 0.4

Time (ns)

Eye at 5Gbps

0

0.1

0.2

0.3

0.4

(V)

Figure Figure Figure Figure 16161616 -------- Measured eye on reference channelMeasured eye on reference channelMeasured eye on reference channelMeasured eye on reference channel

43

Channel SimChannel SimChannel SimChannel Simulationulationulationulation

Finally a complete system interconnect model was built that included SMA connectors, 8” of

daughtercard trace, backplane connectors and vias, and backplane trace. That complete

model is shown below in Figure 17. The connector and via models were imported and a

wrapper was placed around the s-parameter file. At this point, frequency, harmonic balance,

export to HSPICE, or transform to time domain could be done.

A frequency sweep of the channel simulation vs. measured is shown in Figure 18. Next the

harmonic balance simulation is compared against the measured channel eye. Data rates of

3.125Gbps, 5 Gbps, and 6.5Gbps are shown in the following figures.

Figure Figure Figure Figure 17171717 -------- Backp Backp Backp Backplane interconnect circuit modellane interconnect circuit modellane interconnect circuit modellane interconnect circuit model

Diff

Comm

+

-

1

2

3

4

MMCONVMM1

LOADZ1Zcom OhmLOAD

Z2Zcom Ohm

Diff

Comm

+

-

1

2

3

4

MMCONVMM2

LOADZ3Zcom Ohm

Diff

Comm

+

-

1

2

3

4

MMCONVMM3

LOADZ4Zcom Ohm

Diff

Comm

+

-

1

2

3

4

MMCONVMM4

CAPC1CSMA pF

CAPC2CSMA pF

CAPC3CSMA pF

CAPC4CSMA pF

CAPC5CSMA pF

CAPC6CSMA pF

CAPC7CSMA pF

CAPC8CSMA pF

SSUB3.6200 mil40 mil.70661e-12SSUB1

COAX2CX190 Deg5 GHz50

COAX2CX290 Deg5 GHz50

F5

E5

D5

C5

B5

A5

F6

E6

D6

C6

B6

A6

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

SUBCKTS1"EHSD8_Connector_model"

F5

E5

D5

C5

B5

A5

F6

E6

D6

C6

B6

A6

1 2

3 4

5 6

7 8

9 10

11 12

13 14

15 16

17 18

19 20

21 22

23 24

SUBCKTS2"EHSD8_Connector_model"

1 2

3 4

5 6

7 8

SUBCKTS8"eHSD_Xilinx_RW_BP"

12

34

56

78


1 2

3 4

5 6

7 8


12

34

56

78


W1

W2

1

2

3

4

SUBCKTS7"Composite Stripline"

W1

W2

1

2

3

4

SUBCKTS12"Composite Stripline"

W1

W2

1

2

3

4

SUBCKTS13"DC Composite Stripline"

W1

W2

1

2

3

4


W1

W2

1

2

3

4


W1

W2

1

2

3

4


PORT3Zdif Ohm

PORT4Zdif Ohm

PORT2Zdif Ohm

PORT1Zdif Ohm

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT

PORT_PRBS1100 Ohmrate GHz256810.8 V0 V80 ps80 psNRZDEFAULT-1

PORT_PRBS3100 Ohmrate GHz256810.8 V0 V80 ps80 psNRZDEFAULT-1

PORT

PORT

PORT

PORT

Zdif = 100Zcom = 25

This is the uncoupled version

44

Figure Figure Figure Figure 18181818 -------- Complete Backplane channel model with eHSD Complete Backplane channel model with eHSD Complete Backplane channel model with eHSD Complete Backplane channel model with eHSD

0 5 10 15

Frequency (GHz)

S21 PR105 vs Simulated 20_in

-80

-60

-40

-20

0DB(|S(1,3)|)Measured_pr105

DB(|S(4,2)|)pr101_pr105.*20in

45

Figure Figure Figure Figure 19191919 -------- Harmonic Balance simulation of AWR model at 3.125Gbps Harmonic Balance simulation of AWR model at 3.125Gbps Harmonic Balance simulation of AWR model at 3.125Gbps Harmonic Balance simulation of AWR model at 3.125Gbps

0 200 400 600 640

Time (ps)

Eye Diagram 3125 Mbps

0

0.1

0.2

0.3

0.4

(V)

Figure Figure Figure Figure 20202020 -------- Harmon Harmon Harmon Harmonic Balance of measured channel performanceic Balance of measured channel performanceic Balance of measured channel performanceic Balance of measured channel performance

0 200 400 600 640

Time (ps)

Eye Diagram 3125 Mbps using measured channel

-0.1

0

0.1

0.2

0.3

0.4

(V)

46

Figure Figure Figure Figure 21212121 -------- Harmonic Balance simulation of AWR model at 5 Gbps Harmonic Balance simulation of AWR model at 5 Gbps Harmonic Balance simulation of AWR model at 5 Gbps Harmonic Balance simulation of AWR model at 5 Gbps

0 100 200 300 400

Time (ps)


0

0.1

0.2

0.3

0.4

(V)

Figure Figure Figure Figure 22222222 -------- Harmonic Balance of measured channel performanceHarmonic Balance of measured channel performanceHarmonic Balance of measured channel performanceHarmonic Balance of measured channel performance at 5Gbps at 5Gbps at 5Gbps at 5Gbps

0 100 200 300 400

Time (ps)


0

0.1

0.2

0.3

0.4

(V)

47

Figure Figure Figure Figure 23232323-------- Harmonic Balance simulation of AWR model at 6.5 Gbps Harmonic Balance simulation of AWR model at 6.5 Gbps Harmonic Balance simulation of AWR model at 6.5 Gbps Harmonic Balance simulation of AWR model at 6.5 Gbps

0 100 200 300307.7

Time (ps)


0

0.1

0.2

0.3

0.4

(V)

Figure Figure Figure Figure 24242424 -------- Harmonic Balance of measured channel performance Harmonic Balance of measured channel performance Harmonic Balance of measured channel performance Harmonic Balance of measured channel performance

0 100 200 300307.7

Time (ps)


-0.1

0

0.1

0.2

0.3

0.4

(V)

48

HSPICE SimulationsHSPICE SimulationsHSPICE SimulationsHSPICE Simulations

The last phase of simulation was to incorporate HSPICE MGT models of the V4 transmitter

and receiver into the backplane simulation. Here the entire channel shown in Figure 17 is

inserted between the transmitter and receiver. The circuit model of MGT simulation is

shown in Figure 25.

Analyzing the circuit in the time domain gives the ability to monitor all of the nodes in the

MGT Tx-Rx path that are not normally visible in a running system. This allows the designer

to fine tune the pre-emphasis and receiver equalization before getting into the lab. The

accuracy of the backplane channel model will affect the HSPICE simulation but a very tight

correlation between our simulated channel and measured channel has been shown.

Figure Figure Figure Figure 25252525 -------- HSPICE Circuit HSPICE Circuit HSPICE Circuit HSPICE Circuit model model model model of V4 MGTof V4 MGTof V4 MGTof V4 MGT

DCVSID=GNDV=0 V

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM1 M_PROBE

ID=OUT

M_PROBEID=TX_P

M_PROBEID=TX_N

M_PROBEID=PWL

M_PROBEID=PRE_P

M_PROBEID=PRE_N

M_PROBEID=DAT_P

M_PROBEID=POST_P

M_PROBEID=DAT_N

M_PROBEID=POST_N

DCVSID=V1V=1.2 V

M_PROBEID=RX_EQN

M_PROBEID=RX_EQP

M_PROBEID=RX_INP

M_PROBEID=RX_INN

M_PROBEID=RX_LON

M_PROBEID=RX_LOP

DCVSID=V2V=2.5 V

DCVSID=V3V=0.5 V

DCVSID=VTXD1A1V=1.5 V

IN

REF

OUT_0_P

OUT_0_N

OUT_1_P

OUT_1_N

OUT_2_P

OUT_2_N

FIR_3

1

2

3

4

5

6

7

8

SUBCKTID=S1NET="FIR_3"

DAT_N

DAT_P

D33 (TXPRE_PRDRV_DAC_2)



D30 (TXPRE_TAP_PD)

D29 (TX_PRETAP_DAC_4)





D23 (TXSLEWRATE)

D22 (TXTRIMTERM3)

D21 (TXTRIMTERM2)

D20 (TXTRIMTERM1)

D19 (TXTRIMTERM0)

D18 (TX_POST_PRDRV_DAC_2)


D16 (TX_POST_PRDRV_DAC_0) (TXDAT_PRDRV_DAC_2) D15

(TXDAT_PRDRV_DAC_1) D14


D12 (TXHIGHSIGNALEN)

(TXPOST_TAP_DAC_4) D11





(TXDAT_TAP_DAC_4) D6





(TXPOST_TAP_PD) D1

(PMACOREPWRENABLE) D0

TX_N

TX_P

PAIRPD

POST_P

POST_N

PRE_P

PRE_N

VTXD1A5

VTXS1A5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19 20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

SUBCKTID=S3NET="Tx"

REQADJ_2

REQADJ_1

REQADJ_0

REQI_1

REQI_0

RXDCCOUPLE

RXFEPD

RX_EQN

RX_EQP

RX_INN

RX_INP

RX_LON

RX_LOP

VD1A2

VD2A5

RX SUBCKTGND

VTRX

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

SUBCKTID=S2NET="Rx"SUBCKT

ID=S4NET="V_PWL"

W1

W2

1

2

3

4

SUBCKTID=S5NET="pr105_20"

GND

VDD

VDD

VDD

GND

VTRX

VD2A5

VTXD1A5

GND

VDD

Xilinx data file as source for waveforms

FIR_3 Tx RxChannel

49

Figure Figure Figure Figure 26262626 -------- HSPICE node measurement HSPICE node measurement HSPICE node measurement HSPICE node measurementssss

0 5 10 15 20 25

Time (ns)

Waveforms

-1

0

1-0.4

0

0.4-1-0.8-0.6-0.4-0.200.20.40.60.810

0.5

1-0.6-0.4-0.200.20.40.6

9.394 ns0.9373 ns

3.174 ns-0.45 V

6.087 ns

-0.3621 V

Tx (V)

Tx

Channel (V)

Channel

Rx (V)

Rx

Input (V)

Input

DAT In (V)

DAT In

PRE In (V)

PRE In

POST In (V)

POST In

VtimeD(M_PROBE.RX_LOP,M_PROBE.RX_LON,1) (V)

Tx_Ch_Rx.HS.$F_SPEC

In the above simulation the source is a pulse train defined by Xilinx for the channel. This

source is replaced with a PRBS generator next to examine the channel eye. Figure 28 shows

the resultant eye diagram. Here eye closure can be seen which indicates a change to pre-

emphasis might be needed. This eye is measured *before* the receiver. Additional receiver

equalization can and is applied which results in a working channel.

50

Figure Figure Figure Figure 27272727 -------- PRBS pattern checking circuit PRBS pattern checking circuit PRBS pattern checking circuit PRBS pattern checking circuit

M_PROBEID=POST_N1

M_PROBEID=DAT_N1

M_PROBEID=POST_P1

M_PROBEID=DAT_P1

M_PROBEID=PRE_N1

M_PROBEID=PRE_P1M_PROBE

ID=PWL1

M_PROBEID=TX_N1

M_PROBEID=TX_P1

M_PROBEID=OUT1

Diff

Comm

+

-

1

2

3

4

MMCONVID=MM1

DCVSID=VTXD1A1V=1.5 V

DCVSID=GND1V=0 V

M_PROBEID=RX_LOP1

M_PROBEID=RX_LON1

M_PROBEID=RX_INN1

M_PROBEID=RX_INP1

M_PROBEID=RX_EQP1

M_PROBEID=RX_EQN1

DCVSID=V1V=2.5 V

DCVSID=V2V=0.5 V

DCVSID=V3V=1.2 V

REQADJ_2

REQADJ_1

REQADJ_0

REQI_1

REQI_0

RXDCCOUPLE

RXFEPD

RX_EQN

RX_EQP

RX_INN

RX_INP

RX_LON

RX_LOP

VD1A2

VD2A5

RX SUBCKTGND

VTRX

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

SUBCKTID=S1NET="Rx"

DAT_N

DAT_P




D30 (TXPRE_TAP_PD)






D23 (TXSLEWRATE)

D22 (TXTRIMTERM3)

D21 (TXTRIMTERM2)

D20 (TXTRIMTERM1)

D19 (TXTRIMTERM0)



D16 (TX_POST_PRDRV_DAC_0) (TXDAT_PRDRV_DAC_2) D15



D12 (TXHIGHSIGNALEN)











(TXPOST_TAP_PD) D1

(PMACOREPWRENABLE) D0

TX_N

TX_P

PAIRPD

POST_P

POST_N

PRE_P

PRE_N

VTXD1A5

VTXS1A5

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19 20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

SUBCKTID=S2NET="Tx"

IN

REF

OUT_0_P

OUT_0_N

OUT_1_P

OUT_1_N

OUT_2_P

OUT_2_N

FIR_3

1

2

3

4

5

6

7

8

SUBCKTID=S3NET="FIR_3"

W1

W2

1

2

3

4

SUBCKTID=S4NET="pr105_20"

PORT_PRBSP=1Z=50 OhmRATE=5 GHzNSYMB=64SAMP=8BITW=1HI=1 VLO=0 VTR=0.1 nsTF=0.1 nsTYPE=NRZWINDOW=DEFAULTSEED=-1

GND

VDD

GND

VTRX

VD2A5

VDD

VTXD1A5

VDD

GND

VDD

AWR PRBS as source for eyes

FIR_3 Tx RxChannel

Figure Figure Figure Figure 28282828 -------- PRBS eye diagram from HSPICE PRBS eye diagram from HSPICE PRBS eye diagram from HSPICE PRBS eye diagram from HSPICE

0 0.1 0.2 0.3 0.4

Time (ns)

Eye vs Channel Modeling

-1

-0.6

-0.2

0.2

0.6

1

Rx

Ideal Channel

Rx

Realistic Channel

VeyeD(M_PROBE.RX_LOP1,M_PROBE.RX_LON1,2,0,0,0,1000)[*] (V)

Eye_Tx_Ch_Rx.HS.$F_SPEC

51

ConclusionsConclusionsConclusionsConclusions

Backplanes are the central piece of any industrial system or telecommunications platform.

Their design can predict the lifetime of the equipment and the success of the equipment. For

this reason the design of the backplane has to be right the first time and guessing your way

to success will ensure failure.

There are number of design decisions that must be made prior to routing a backplane.

Choosing the materials, the connectors, and your fabricator are all key. Developing strong

relationships up front with these suppliers is a necessary requirement.

Simulation has taken a key role in the development of backplane design. There are number

of tools available to comprehensively simulate the backplane channel. Xilinx chose AWR and

found the simulation results matched very closely with the measured results.

Developing a strategy for simulation and verification is necessary early on. It is very

important to be able to study and measure the channel both actively and passively. And

sharing your verification strategy with your connector and backplane fabricators is very

important as well if there are any issues discovered. Having this agreed methodology in

place before constructing the backplane will save much grief in the long run.

Xilinx offers complete HSPICE models which will allows designers to fully investigate the

MGT performance across a channel before the product is built.

Contact your local Xilinx FAE for support of these models and to review your channel design

with Xilinx MGT IO Specialists.