Will FinFET era last only for 10 years? FinFET scaling challenges for next CMOS technology nodesDr. Arkadiusz Malinowski

Thank you for the invitation

• It is my pleasure to give presentation during this Mini-Colloquium so I would like to thank Prof. Krzysztof Gorecki (Gdynia Maritime Academy) ED Poland Chair for the invitation and this opportunity.

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Contents

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Background

FinFET integration challenges

Summary

1

2

3

Contents

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FinFET integration challenges

Summary

2

3

Background1

Moore’s prediction and Dennard’s scaling rules in practice

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Year of production

1971

Clock speed

760kHz

Number of transistors

2300

Technology

10m

Intel 4004

Year of production

2009

Clock speed

3.33GHz

Number of transistors

1.17billion

Technology

32nm

Intel Core i7 980X

• 4 decades of scaling CMOS planar technology 1971 – 2009

The Story of the Intel® 4004 https://www.intel.com/content/www/us/en/history/museum-story-of-intel-4004.html

Intel 32nm technology http://download.intel.com/pressroom/kits/32nm/westmere/Mark_Bohr_32nm.pdf

In May 2011 Intel starts FinFET era

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• On May 2nd, 2011 Intel announces a major breakthrough and historic innovation in microchips: the world’s first 3-D transistors in mass production (Ivy Bridge).

• The others TSMC, Samsung and GLOBALFOUNDRIES had followed.

https://newsroom.intel.com/press-kits/intel-22nm-3-d-tri-gate-transistor-technology/http://www.tsmc.com/english/dedicatedFoundry/technology/16nm.htmhttps://www.globalfoundries.com/news-events/press-releases/globalfoundries-achieves-14nm-finfet-technology-success-for-next-generation-amd-products

FinFET origin: key publications 1984 and 1998

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• Idea of double gate transistor has been presented by T. Sekigawa and Y. Hayashi in 1984.

• FinFET structure as we know it right now for the first time has been proposed by D. Hisamoto in 1998.

T. Sekigawa and Y. Hayashi, “Calculated threshold voltage characteristics of an XMOS transistor having an additional bottom gate,” Solid-State Electron., vol. 27, no. 8–9, pp. 827–828, 1984.

D. Hisamoto et al., "A folded-channel MOSFET for deep-sub-tenth micron era," IEDM 1998. Technical Digest (Cat. No.98CH36217), San Francisco, CA, USA, 1998, pp. 1032-1034.

“No Exponential is Forever: But 'Forever' Can Be Delayed!”

20192003 - 2009 2011 2014 - 2017

High-k

Metal Gate

45nm technology

FinFET

22nm technology

Low-k

14nm technology

EUV

7nm technology

> 2021

EUV DP

5nm technology

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https://www.eetimes.com/document.asp?doc_id=1333318# / https://semiengineering.com/single-vs-multi-patterning-euv/

Gordon E. Moore, “No Exponential is Forever: But 'Forever' Can Be Delayed!”, Digest of Technical Papers. ISSCC. 2003 IEEE International, 2003, pgs. 20 - 23 vol.1

NSFET

3nm technology

ArF 193i

45nm technology

Strained Silicon

90nm technology

Cobalt Contact

10nm technology

• Several times in the past it was predicted that technological barriers would stop CMOS technology scaling.

• Processes, materials, tools as well as architecture game changers kept Moore’s Law and scaling alive!

10 years of FinFET era

Contents

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Background

Summary

1

3

FinFET integration challenges2

So what is the problem?

• CMOS technology reached tremendous scaling level: 100 mln transistors / mm2 (size of amaranth grain).

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Level Pitch [nm]

Fin 30

Gate 56

M0 40

M1 56

M2 40

M3 40

𝐹𝑖𝑛𝐹𝐸𝑇𝐴𝑟𝑒𝑎 = 𝐹𝑖𝑛𝑃𝑖𝑡𝑐ℎ × 𝐺𝑎𝑡𝑒𝑃𝑖𝑡𝑐ℎ = 30 𝑛𝑚 × 56 𝑛𝑚 = 1680 𝑛𝑚2

1 𝑚𝑚2

1680 𝑛𝑚2=1 × 10−6 𝑚

2 × 10−15𝑚= 0.5 × 109 →> 𝟏𝟎𝟎𝒎𝒍𝒏

𝑻𝒓𝒂𝒏𝒔𝒊𝒔𝒕𝒐𝒓𝒔

𝒎𝒎𝟐

S. Narasimha et al., “A 7nm CMOS technology platform for mobile and high performance compute application”, 2017 IEEE International Electron Devices Meeting

(IEDM), DOI: 10.1109/IEDM.2017.8268476

Amaranth

Key GF 7nm technology pitches

Advanced FinFET technology challenges

• Such advanced FinFET technologies (10nm / 7nm) are facing many difficult challenges which can be grouped into 5 main categories.

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Challenges

Metro

Inspection

Litho

OVL

Integration

VariabilityCycle Time

Quantum effects

Metro – single nm matters!

• FinFET 10/7nm device electrical parameters are very sensitive to single nm structure changes metrology needs to able to capture such changes!

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FinFET

3D

structure

Very

Small

Dense packed

Tall Narrow

New Materials

Metro – increasing data volumes!

• Process complexity means exponentially increasing data volumes and causing analysis challenges.

• Critical importance of OCD (Scatterometry) only HVM solution to profile parameters for 3D metrology.

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ht/tps://semiengineering.com/finfet-metrology-challenges-grow

B. Bunday SUNY Poly SEMATECH Proc. SPIE 9778 97780E-1 (2016)

Dimensions

• CD-SEM, CD-AFM, OCD

Composition

• XPS, EDX

Dopants

• SIMS

Strain

• XRD, XRF

Electrical

• I-V, C-VScatterometric method measure property changes of the light

caused by the interaction with the sample, use information to

reconstruct the structures under test model dependent!

i r

Raw Spectral DataModel / Library

software

Inspection – finding killer defects in chips

• Optical inspection is being stretched to the limit and is struggling to detect defects at 20nm and below.

• E-beam inspection can find the smallest defects, as the technology has sensitivities down to 1nm very slow.

• The e-beam inspection technique is increasingly utilized for the traditional voltage contrast mode (MOL).

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https://semiengineering.com/e-beam-inspection-makes-inroads/

https://semiengineering.com/fab-challenges-at-7nm-and-5nm/

Optical

E-beam

Voltage Contrast

BVCDVC

Electrical defects:

shortsopens

OVL – challenge on the rise

• ICs are built up layer by layer and 7nm technology IC can easily have more than 60 layers. Overlay is a measure of a system’s ability to print these layers accurately on top of each other. Successive layers must be accurately aligned to the previous layer huge impact on yield / performance.

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OVL systematic error correction…(worst case re-work)

Step & scanReticle stage accelerates at 150 m/sec2

Car: 0 100 km/h in 0.11 seconds

Translation X, Y RotationMagnification

Lens trapezoid

Lens distortion

Overlay errors

…after correction overlay residuals:

nonsystematic errors cannot be correctedSingle-machine (dedicated chuck):

≤ 1.4 nm full wafer coverage

OVL correction – Processed Wafer Geometry.

• Addressing non-litho overlay is paramount to reducing wafer level variability.

• Nonuniform stress across the wafer is very problematic resulting in noncorrectable overlay errors.

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J. Micro/Nanolith. MEMS MOEMS 12(4), 043002 (Oct–Dec 2013)

Nonuniform wafer stress

Design pattern

RTAThin Film

Deposition

Deposition of thin film

Wafer before process

L + L

OVL budget approached to

3-nm regime (|mean|+3σ)

OVL control – the need for single nm control

• Total measurement uncertainty (TMU) reduction is critical (IBO DBO).

• The need for In-Device Metrology (IDM) that enables accurate and dense overlay metrology on device level features.

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DBO based on an angle-resolved high-NA scatterometry detection of first or higher order diffraction of gratings subsequently exposed in two different layers

https://www.semanticscholar.org/paper/Diffraction-based-and-image-based-overlay-for-node-Xu-Qin/dc878b8703e844a7e2915224811f8a37a742940f

https://semiengineering.com/overlay-challenges-on-the-rise/ / https://www.kla-tencor.com/products/chip-manufacturing/metrology

https://www.3d-metrology-workshop.eu/images/presentations_2018/6_Paul_Hinnen.pdf

Image Base Overlay marks large structures Metrology based on optical microscopy systems

Box In Box (BIB)Advanced Imaging Metrology (AIM) more robust and compatible with

CMP processes

inner (current layer) and

outer (previous layer)

-OV OV = 0 +OV

I0I+1

I-1

I0I+1

I-1

I0I+1

I-1

1st layer(etch patterned)

2nd layer(resist)

OVL Tree – implications of complicated align tree for yield

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Mx / VxDesign

Metal masks (LELE)

OVL error in Vx masksVx opens

Vx-Mx shortsVx-Vx shorts

VIA masks(layout colors)

Cut masks

OVL error in Mx Mx shorts

(not a problem in SADP / SAQP)

• Massive shorts / opens in BEOL due to OVL error in Mx / Cut + VIA masks.

• EUV excellent solution for VIA + Cut masks.

OVL error in Cut masksMx opensMx shorts

EUV excellent solution forVIAs + Cuts

OVL – growth of self-aligned techniques

VIAFSAV

BEOLSADPSAQP

GateSADP

FinSAQP

Contact SAC

Self Aligned

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• OLV challenges led to explosion of self aligned techniques in all areas FEOL, MOL as well as BEOL with double as well as quadruple pitch division.

Bower, RW and Dill, RG (1966). "Insulated gate field effect transistors fabricated using the gate as source-drain mask". IEEE International Electron Devices Meeting, 1966

OVL – Making Fins Self Aligned Double Patterning (SADP)

• Self-aligned spacer avoid mask misalignment.

• Doubled SADP (double mandrel formation) SAQP.

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https://semiengineering.com/single-vs-multi-patterning-euv/

SOH HM

SiN

Silicon Substrate

Layer deposition Mandrel Formation Spacer deposition Spacer etch Mandrel pull Nitride and silicon etch

Defines Fin Pitch Defines Fin Width

Lithography – need for EUV

• Resolution ArF 193i 38 nm which leads to significant increase number of masking layers (quadruple and double patterning) increasing product cost and cycle time. EUV is needed resolution 13nm.

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𝑅 = 𝑘1𝜆

𝑁𝐴

= 13.5nmNA = 0.33k1 = 0.31

SOH HM

SiN

Silicon Substrate

Layer deposition Nitride and silicon etch𝑅 = 13 𝑛𝑚

EUV

Complex pattern in one shot

• Fewer masks

• Shorter cycle time

• Simpler stack

EUV – it has its own challenges

• However EUV lithography is creating a new set of challenges, and for some of them, like on the photomask side for which there currently are no simple solutions.

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EUV issues

CoO

Up time

Source power

Tool particles

Mask inspection

Pellicle

EUV – tool up time / source power

• EUV tool up-time is primary concern for reaching availability level required for high volume manufacturing.

• Major contributor to tool down time is exposure source.

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LPP – laser produced plasma

EUV

Tin dropletsPre-pulse laser

Main pulse laser

Direct incidence multi-layercollector mirror

Debris

10.6 micron wavelength

pulsed CO2 laser

Despite the collector is protected from the

plasma by a debris mitigation technology based

on a hydrogen buffer gas after a certain number

of gigapulses tool requires collector swap.

Must ensure satisfactory dose control at high

power 250W needed for HVM

EUV – defectivity / pellicle

• EUV tool defectivity and particles fall on the mask is another critical concern.

• Scanner particle adder rate is still too high for HVM without pellicle.

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Reticle

Pellicle Frame

Pellicle Mask

Focal plane

particle

Out of Focus

Wafer

Objective Lens

Pellicle

E-beam mask inspection too slow

Actinic Patterned Mask Inspection

(APMI) needed

Pellicle membrane continued

improvement necessary for increasing

transmission, withstanding increased

source power, and extending lifetime

(OpEx)

Lithography – pushing ArF 193nm to the limits

• Because of so many EUV issues, DUV lithography is still preferred choice and it is being pushed to the limits.

• In order to further improve resolution (for given wavelength) numerical aperture (NA) of the optical system must be increased increased NA degrades DOF new Hard Mask scheme is needed!

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𝑅 = 𝑘1𝜆

𝑁𝐴

𝐷𝑂𝐹 = 𝑘2𝜆

(𝑁𝐴)2

Hg• 365 nm (i)

KrF • 248 nm

ArF• 193 nm

ArF i• 193 nm + NA

Numerical aperture (NA) of 1.35 – the

highest in the industry.

Wafer

Water

LensResist stack

PR

BARC

SiON

SOH

Wafer

Hard Mask needs:

Excellent Litho performance

Excellent Etch Performance

Easy re-work

Low CoO

High Throughput

Product Integration – Process complexity

• Currently FinFET technology 7nm manufacture only 3 companies in the World: TSMC, Intel, Samsung. For example 130nm technology was manufactured by ~25 companies.

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Product Process

New materials

Co, Ru

Small Volumes

EPI, RMG

High Aspect Ratios

Tighter pitches

Fin, Gate

Quantum Effects

Product Integration – FEOL Fin

• Challenges of further scaling Fin Height and Pitch.

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EPI

FinFin Pitch

Fin Height

Fin TCD

EPI size

Scaling trends:

Fin height taller

Fin pitch shorter

Fin aspect ratio higher

Fin TCD narrower

EPI size smaller

Product Integration – FEOL Fin

• Challenges of further scaling Fin Height and Pitch.

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Fin Pitch

Fin Height

Fin TCD

EPI size Small EPI volume

• High contact resistance

• Requires high doping (e21)

• In-situ doping levels (B / P) reaching solubility levels in Si

• Requires complex anneals (LSA / DSA)

• High level dopant de-activation @ 600C

• Smaller stress from eSiGe

Dynamic Surface Anneal (DSA) The systems' laser heats the

top few layers of atoms of the wafer surface layers to over 1000°C

in less than a millisecond, a heating rate of 1 million degrees

Celsius per second.

Scaling Fin

• Contact area becomes smaller as scaling fin pitch

• Fill material pinch-off as spacer and gatestack formation

• Fin height and pitch scaling increase Ceff

• Taller Fin more challenging fin reveal and fin profile (TCD / BCD ratio).

• Fin TCD scaling limited by Quantum confinement effect

• Smaller S/D epi size as scaling fin pitch

Quantum confinement is change of electronic and optical properties

when the material sampled is of sufficiently small size (<10nm).

Product Integration – FEOL RMG / mWF

• Diminishing space at 7nm (Lg) poses serious challenge on process control and device variability.

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Drain

Source

Oxide

Siliconsubstrate

Gate

Cross section

FinFET 3D viewtypical illustration

Siliconsubstrate

Source Drain

Gate

Fin

Fin

Metal workfunctionsetting by metal thicknesses

Lg

Product Integration – FEOL RMG / mWF

• Gatestack engineering very critical for Tinv – mobility – reliability – performance.

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Scaling

Siliconsubstrate

Source Drain

Gate

Fin

Lg

Siliconsubstrate

Source DrainGate

Fin

Lg < 17nm

Small gate volume makes mVT and SAC

contacts integration very challenging.

Multiple Dep/Etch required for different Vt (volume-based)

RMG gate-recess extremely difficult when the Lg < 17nm

Fill / recess of sacrificial material very hard (process variation)

Product Integration – MOL CA

• Low contact resistance (Rc) is key to boost device performance for sub-10nm nodes.

• To achieve Rc < 10-9 cm2 requires active dopant carrier concentration >51020 cm-3

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Scaling

CA

M0

TS

EPI

Fin

Resistance benefit cobalt insertion from W to Co/Co

W

CA CD

CAM0

TS

Co TS to PC shorts

rising challenge for

scaling FinFET

Product Integration – BEOL Lines / VIAs

• Scaling the Cu interconnect metallization Liner/barrier THK has the biggest impact on Cu volume and therefore RES more than aspect ratio and symmetry

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scaling

Scaling R C RC delay

Cu

Interconnect metal

Cu

ULK

Barrier

Liner

Product Integration – BEOL Lines / VIAs

• Big game changer copper metallization which replaced aluminum soon might be replaced as well with barrier-less ruthenium metallization.

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Thinner Barrier/Liners

EM & TDDB concerns limit how

thin liner and cap can be for Cu

Ru barriersless can take over Cu

Lower Capacitance but TDDB and

mechanical integrity concernsLower- dielectric

Airgap

Lowest RVia for Ru / TiN with metal

barrier THK 0 nm

FSAV allows for topography CD and

OVL relaxation

Variability – the need for super fine plasma etch

• The other problem directly related to process integration and resulting from scaling pitch is process variability.

• Minor technology processes dispersion causes significant impact on FinFET electrical parameters fluctuations.

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Variability sources:

• Lithography: IBO DBO / EUV

• Deposition: CVD ALD

• CMP: process recipe optimization

• RTA: Zonal RTA

• Etch need for Atomic Precision

Drain

Source

Oxide

Siliconsubstrate

Gate

Nsub

Nwell

DummyGate

EG Oxide

Fin

Fin / Gate defined by plasma etch

Channel length

Cavity etch for EPI

Plasma etch defines channel length

Variability – etch precision modeling: sticking coefficient is a key!

• Next generations of FinFETs or NSFETs with aggressively scaled pitches won’t be possible without super fine plasma etch super fine plasma etch process modeling is required.

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A. Malinowski, PhD thesis, Nagoya University, 2012.

Etch precision which is inverse of number of damaged layerscan be expressed using measurable etch parameters:

ERi – ion enhanced etch rate (ignoring spontaneous chemical etching), SC – sticking coefficient, JR – radical

flux, Ji – ion flux, i – ion energy (i < sputter; sputter – sputter threshold energy), th – threshold energy.

Key element for PE modeling is SC estimation which is not a trivial task!

A. Malinowski et al.J. Phys. D: Appl. Phys. 46 265201, doi: 10.1088/0022-3727/46/26/265201

Variability – Line Width Roughness

• What can ultimately stop technology scaling can be Line Width Roughness / Line Edge Roughness.

• It doesn’t scale with the feature size LWR/LER becomes bigger portion of CD.

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A. Malinowski, PhD thesis Warsaw University of Technology, The Institute of Microelectronics and Optoelectronics, 2016

Drain

Source

Oxide

Siliconsubstrate

Gate

Cycle Time – Time to market = $$$

• Cycle time defines how fast we get lot through the line how fast we can learn and how fast we can improve (CIP) ultimately how fast we can deliver lot to customer and generate revenue.

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Depends of processcomplexity.

Mask Count 7nm >> 28nm

Tool up time SDT / UDT / SOAK (R&D) Adding tools not easy Factory Physics!

Automated Handling Systemthat carries a lot is also adding to CT

Number of masks

Tools

AMHS

DPML

Cycle time CT = DPML * # masks

Average number of days needed for processing of 1

Masking Layer

How to double chips in IC every 2 years with such long learning

cycle needed for R&D?

EUV critical reducing #masks

Costs – three main components

• Costs driven by product design and technology development followed by manufacturing Fab (including tooling).

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Product design

Technology development

Manufacturing Fab

Cost – Design costs increasing problem

• IC design costs have jumped from $51.3 million for a 28nm planar device to $297.8 million for a 7nm chip.

• At 3nm complex GPU design (Nvidia) may be as high as $1.5 billion.

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https://semiengineering.com/big-trouble-at-3nm/

Product Design

Design Complexity

Many new design rules

Layout Effects

OPC cycles

Parasitic extraction

$300M

$540M

$500M - 1.5B

7nm

5nm

3nm

Cost – Manufacturing Fab

• Typically cost of brand new fab hovers around $10 billion.

• Currently under constriction, in total, the Fab 18 will cost TSMC $17.08 billion, making it one of the most expensive chip manufacturing facilities in the world.

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https://www.anandtech.com/show/12377/tsmc-starts-to-build-fab-18-5nm-in-early-2020

GF, Fab1, Dresden, Germany GF, Fab8, Malta, USA

Contents

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Background

FinFET integration challenges

1

2

Summary3

Summary

• We are observing live the end of Moore’s Law!

• Moore’s Law / Dennard scaling From 4000 trans in 1971 to 1B in 2011 in 4 decades

• The end of tech scaling predicted many times but massive research kept it alive

• Many game changers process introduced: strained Si, High-k MG, FinFET

• Variations are at every process layer exceeding capabilities of process / inspection tools.

• Cost of design, development, manufacturing, tooling (=wafer cost) above reasonable levels.

• EUV is a must in 7nm and/or following nodes but brings another set of challenges.

• FinFET architecture will be replaced with GAAFET probably with NSFET (nano-sheets).

• CMOS technology scaling will continue thanks to another game changers such as EUV DP and the end of classical CMOS technology scaling 3nm?

• Beyond CMOS era will start with NC, TFT?

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Thank you for your kind attention!arek.malinowski@globalfoundries.com