Winning in 3D NAND

ETCH & DSM

Prabu Gopalraja, Ph.D. Mukund Srinivasan, Ph.D.

VP, General Manager – ETCH VP, General Manager – DSM

Silicon Systems Group Silicon Systems Group

External Use

Safe Harbor Statement

2

This presentation contains forward-looking statements, including those regarding our

industry outlooks, growth opportunities, market positions, products and strategies.

These statements are subject to known and unknown risks and uncertainties that

could cause actual results to differ materially from those expressed or implied in our

current views, including: uncertain global economic and industry conditions; demand

for mobility products; customers’ new technology and capacity requirements; the

concentrated nature of our customer base; Applied’s ability to (i) develop, deliver and

support a broad range of products and expand its markets, (ii) achieve the objectives

of operational initiatives, (iii) obtain and protect IP, and (iv) attract, motivate and retain

key employees; and other risks described in our most recent SEC Form 10-Q. All

forward-looking statements are based on management’s estimates, projections and

assumptions as of July 8, 2013, and Applied undertakes no obligation to update any

forward-looking statements.

3D - The Future of NAND

“3D NAND will carry us beyond the 10-nm limit”

Keyvan Esfarjani, co-CEO, IM Flash Technologies,

IMEC Technology Forum 2013

“…all major semiconductor companies are investing more in the

development of 3D flash memory chips’’

Dr. Park Sung-wook, Chief Technology Officer,

SK Hynix, Jan’13, Korean Times

“to meet the market trend, 3D nonvolatile memories are expected

to replace the planar one, especially for 10nm nodes and beyond”

Dr. Jungdal Choi, VP, Samsung Semiconductor R&D

VLSI Technology Digest 2011

External Use 3

COST PER BIT REDUCTION

3D NAND

0.1

1

10

100

1000

150nm 100nm 60nm 50nm 40nm 20nm 1Ynm

Technology Node

$/GB

SLOWING

COST-BENEFIT

PHYSICAL LIMITS

Challenges in 2D NAND Extendibility

2D NAND approaching cost and physical scaling limits

DATA RETENTION

FEWER ELECTRONS/CELL

(1000@50nm vs 8@10nm)

Control Gate

Floating

Gate

e-

e-

e-

e-

e-

External Use 4

3D NAND

2) Stretch It Out In The Middle

3) Fold It Over

1) Typical Planar NAND Cell String

4) Stand It Vertically

3D NAND Uses Less Wafer Area Than

2D For Same Bit Density

Future 3D NAND:

increasing

number of pairs

32 64 pairs

External Use 5

3D NAND

5) Replicate

6) Make contact to staircase vias

“Advantage of 3D NAND is that it doesn’t require leading-edge

lithography…the burden will shift from lithography to deposition and etch.”

Ritu Shrivastava, VP Technology, SanDisk, May 2013 (SemiMD)

NAND Cell

NAND

Cell STAIRCASE

PATTERNING

External Use 6

3D NAND

5) Replicate

6) Make contact to staircase vias

“Advantage of 3D NAND is that it doesn’t require leading-edge

lithography…the burden will shift from lithography to deposition and etch.”

Ritu Shrivastava, VP Technology, SanDisk, May 2013 (SemiMD)

NAND Cell

NAND

Cell STAIRCASE

PATTERNING

the burden will shift from lithography to deposition and etch

External Use 7

3D NAND: Game Changer for Etch and Deposition

1

2

3

CD DEFINITION AND SCALING (<15nm) Lithography

ETCH Lower aspect ratios

Multi-patterning (SATP, SAQP)

CD DEFINITION AND SCALING (~50nm) Etch and Deposition Grows

Lithography drops

ETCH (+30 to +40%) High aspect ratios

Staircase patterning (trim and etch)

DEPOSITION Single layer

Thinner films

DEPOSITION (+50 to +60%) Multi-layer stacks

Thick films (active and hardmask)

PLANAR 3D NAND

External Use 8

Winning in 3D NAND

ETCH

STAIRCASE PATTERNING

3D NAND: New Etch Applications

Sources: VLSI and IEDM

STAIRCASE

PATTERNING

HIGH ASPECT RATIO SLITS/TRENCHES

HIGH ASPECT RATIO CHANNEL FORMATION HIGH ASPECT RATIO

STAIRCASE CONTACT

HIGH ASPECT

RATIO HARD MASK OPEN

4 TO 5 PASSES

32, 48, 64 pairs

STAIRCASE PATTERNING MULTIPLE PASSES

New Etch Capabilities Required

DEVICE PERFORMANCE AND YIELD DRIVERS

Litho Etch Etch Litho

Etch a Step

Trim Resist

Strip Resist

Step Width Control Multiple Trim Steps

Step Profile Lateral-Vertical Control

HIGH ASPECT RATIO

3D

NA

ND

PL

AN

AR

DEVICE PERFORMANCE AND YIELD DRIVERS

Multi-Layer Etch Hardmask Selectivity Profile Control

New Etch Regime Novel Etch Technology

CD <15nm

AR ~8:1

CD <50nm

AR >60:1

External Use 10

$350M NEW MARKET OPPORTUNITY

PER 100K WSPM 32 pair

$550M for 64 pair

PHASE YEAR

R&D 2013-14

PILOT 2013-15

RAMP 2014-16 PLANAR

3D NAND

HIGH ASPECT RATIO ETCH

$200M TAM

STAIRCASE PATTERNING

$150M TAM

CRITICAL SILICON

$600M, 32 pair

OTHER PATTERNING

$450M TAM/100K WSPM

NEW

STEPS

3D NAND: High Growth Etch Opportunity

INTERCONNECT

/ OTHER

CRITICAL

SILICON

OTHER

PATTERNING

INTERCONNECT/OTHER

External Use 11

32 pair

Applied Product Portfolio for 3D NAND Etch

AVATAR™ (2012)

HAR Profile Control + High Productivity

CENTRIS™ MESA™ (2010)

Staircase Precision + High productivity

12 External Use

Winning High Aspect Ratio Etch

13

Industry Unique VHF RF

Source Technology

+

PulSync™ Synchronized

Source and Bias Pulsing

Ion Energy Distribution

Ion Angle Control

Surface Charge Management

Passivation Control

Distortion-free Profiles of Channel and Contact Holes

AVATAR HIGH VALUE PROBLEMS

BOWING BENDING

+

+

STRAIGHT VERTICAL CIRCULAR

NON-CIRCULAR

+ +

- -

- - -

+ +

+ +

- -

APPLIED SOLUTIONS

WIDE

NARROW

CHARGING

NO CHARGING

External Use

Winning Staircase Patterning

14

Proprietary ICP Technology

with Source and Bias

Synch-Pulsing

+

Differentiated IP for Precise

Step-Width Control

+

High Productivity Centris

Platform

Precise Step-width Control with High Productivity

CENTRIS MESA HIGH VALUE PROBLEMS

APPLIED SOLUTIONS

TAPERED PROFILE UNEVEN STEPS

STRAIGHT PROFILE EQUAL STEPS

UN-LANDED CONTACTS

LANDED CONTACTS

External Use

Applied Etch is Positioned to Win in 3D NAND

15

HIGH ASPECT RATIO ETCH

$200M TAM

STAIRCASE PATTERNING

$150M TAM

3D NAND Cust 1 Cust 2 Cust 3 Cust 4

Development Tool of Record (DTOR)

Customer

A Customer

B Customer

C Customer

D

INTERCONNECT/OTHER

CRITICAL SILICON

OTHER PATTERNING

Evaluation On-going $350M NEW MARKET OPPORTUNITY

PER 100K WSPM 32 pair

$550M for 64 pair

External Use

Winning in 3D NAND

DIELECTRIC SYSTEMS & MODULES

APPLIED 3D NAND – CVD Opportunity*

New TAM in PECVD and greenfield

investments in HDP & SACVD (high share

segment for Applied) are a significant

opportunity for CVD

PECVD = Plasma-Enhanced Chemical Vapor Deposition

ALD = Atomic Layer Deposition

High Density Plasma and Atmospheric Pressure/Sub Atmospheric Chemical Vapor Deposition

* Per 100K WSPM, 32 pairs

2D NAND 3D NAND

VNAND Stack

Hardmask

Oxide, Nitride

$350M

$580M, 32 pair

HDP, SACVD

PECVD

ALD

17

$230M NEW MARKET OPPORTUNITY

PER 100K WSPM 32 pair

$310M for 64 pair

NEW

STEPS

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3D NAND-High Value Problems for CVD

18

Sources: VLSI and IEDM

Must edit to match TAM chart’s

labels

Add animation to build layers

Can mention aspect ratios against

the HAR steps Critical Hardmask

HDP & SACVD

Gate Stack

32, 48, 64 pair

Critical CVD Requirements Create Multiple Opportunities for Applied

Oxide/Nitride or Silicon

Channel, Word Line, Metal Contact High Aspect Ratios up to 60:1

Isolation and Interlayer Dielectrics

External Use

3D NAND Gate Stack Deposition

Challenges:

Film Thickness determines Gate Length;

Uniformity is Critical

Manufacturing costs will pace adoption due to lower

throughputs

Applied Solution:

Innovative PrecisionTM CVD Chamber Design

► Uniform deposition to <1% with layer-to-layer precision

► Superior repeatability with independent station control

► Higher Chamber throughput efficiency with lower operating cost

~$80M New Gate Stack Market Opportunity per 100KWSPM, 32 pair

19 External Use

In Production New Hardmask

Integrated Patterning Solutions with Next Gen Hard Mask and Etch

Challenge:

High etch-selectivity required for

patterning high aspect ratio 3D NAND

structures

Solution:

Synthesis of novel chemistry for new

hardmask films

Collaboration with Etch to ensure film

extendibility to meet 3D NAND roadmap

~$150M New Patterning Market Opportunity per 100KWSPM, 32 pair

Etch Selectivity

2X

20 External Use

Positioned to Grow in 3D NAND

2D NAND 3D NAND

HDP, SACVD

PECVD

ALD

VNAND

Stack

Hardmask

Oxide, Nitride

$350M

$580M, 32pair Customer

A

Customer

B

Customer

C

Customer

D

Development Tool of Record (DTOR)

Evaluation On-going

$230M NEW MARKET OPPORTUNITY

PER 100K WSPM 32 pair

$310M for 64 pair

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22

Opportunities

for Applied in

3D NAND

3D NAND grows TAM with new and existing

steps for Etch and CVD ~ $580M per

100kwspm

Positioned to win with all NAND

customers in their R&D efforts

Differentiated products will lead to

profitable growth by solving high

value problems

External Use