WRTLT'16 ProgramThe Seventeenth Workshop on RTL and High Level TestingNovember 24-25, 2016, Aki Grand Hotel, Hiroshima, JAPAN

12:00 Bus Service from (ATS'16 Venue) to (WRTLT'16 Venue)

13:00-14:20 Welcome Lunch (1F Itsukushima)

14:20-14:40 Opening

14:40-15:40 Keynote Speech:

"Automatic generation of test programs from high-level processor descriptions: an academic dream?"

Prof. Matteo Sonza Reorda (Politecnico di Torino, Italy)

15:40-16:10 Invited Talk :

“Why Open Defects Should be Explicitly Targeted During Test”

Prof. Adit D. Singh (Auburn University, USA)

* presenter

Chair: Prof. Toshinori Hosokawa (Nihon University)

16:30-16:50 Synchronization, Calibration and Triggering of IEEE 1687 Embedded Instruments

* Artur Jutman, Sergei Devadze (Testonica Lab) and Konstantin Shibin (Tallinn University of Technology)

16:50-17:10 Capacitive Open Defect Detection by Electrical Interconnect Test of 3D ICs without Boundary Scan Flip Flops

* Fara Ashikin Binti Ali (Universiti Teknikal Malaysia Melaka; Tokushima University), Yuki Ikiri, Masaki Hashizume, HiroyukiYotsuyanagi (Tokushima University) and Shyue-Kung Lu (National Taiwan University of Science and Technology)

17:10-17:25 On Control Circuit and Observation Conditions for Testing Multiple TSVs Using Boundary Scan Circuit with EmbeddedTDC

* Takumi Kawaguchi, Hiroyuki Yotsuyanagi and Masaki Hashizume (Tokushima University)

Chair: Prof. Huawei Li (Institute of Computing Technology, CAS)

17:30-17:50 Use Machine Learning to Predict Circuit Test Timing Based on Physical Information

Yu-Cheng Liu and * James C.-M. Li (National Taiwan University)

17:50-18:10 R-fill : Timing Aware Capture Power Reduction using ZOLP

Rohini Gulve and * Virendra Singh(Indian Institute of Technology Bombay)

19:00-21:00 Banquet (4F Seto-no-Ma)

Day 1: Thursday, Nov. 24, 2016

Plenary Session (4F Sango)

Session 1: System Test and 3D-IC Test (4F Sango)

Session 2: Power-Aware Testing (4F Sango)

6:00-8:00 Tour to the Miyajima Island (A World Heritage Site)

* presenter

Chair: Prof. Yasuo Sato (Kyushu Institute of Technology)9:00-9:20 Exploration of Four-Phase Dual-Rail Asynchronous RTL Design for Delay-Robustness

Tsuyoshi Iwagaki, * Kohta Itani, Hideyuki Ichihara and Tomoo Inoue (Hiroshima City University)9:20-9:40 Fault Diagnosis of Physical Unclonable Function

Jing Ye, * Qingli Guo, Yu Hu and Xiaowei Li (Chinese Academy of Sciences)9:40-9:55 Impact of State Assignment on Error Resilient Stochastic Computing with Linear Finite State Machines

Hideyuki Ichihara, * Motoi Fukuda, Tsuyoshi Iwagaki and Tomoo Inoue (Hiroshima City University)9:55-10:10 A Binding Method to Generate Easily Testable Functional Time Expansion Models

* Mamoru Sato, Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa (Nihon University) and Hideo Fujiwara (Osaka GakuinUniversity)

10:10-10:25 A Design for Testability Method at RTL for Concurrent Operational Unit Testing

* Shun Takeda, Toshinori Hosokawa, Hiroshi Yamazaki (Nihon University) and Masayoshi Yoshimura (Kyoto Sangyo University)

Chair: Prof. Jiun-Lang Huang (National Taiwan University)10:35-10:55 Measurement of On-Chip Temperature and Voltage Variation Using Digital Sensors

* Yousuke Miyake, Yasuo Sato and Seiji Kajihara (Kyushu Institute of Technology)10:55-11:15 Pattern Partitioning for Field Testing Considering the Aging Speed

* Hanan Al Awadhi, Senling Wang, Yoshinobu Higami and Hiroshi Takahashi (Ehime University)11:15-11:35 Path-based Approach to Identify Timing Critical Paths under Aging

Ankush Srivastava (NXP Semiconductor India), * Virendra Singh (Indian Institute of Technology Bombay), Adit D. Singh(Auburn University) and Kewal Saluja (University of Wisconsin)

11:45-12:10 Invited Talk:

“Multi-Level High-Throughput Simulation for Design & Test Validation”

Prof. Hans-Joachim Wunderlich (University of Stuttgart, Germany�

12:10-13:40 ���������������� ��

Chair: Prof. Ilia Polian (University of Passau)13:40-14:00 A Methodology For Post-Silicon Debug Utilizing Progressive Random Access Scan Architecture

Binod Kumar, Ankit Jindal (Indian Institute of Technology Bombay) , Jaynarayan Tudu (Indian Institute of Science) and* Virendra Singh (Indian Institute of Technology Bombay)

14:00-14:15 Strongly Secure Scan Design Using Extended Shift Registers

* Hiroshi Yamazaki, Toshinori Hosokawa (Nihon University) and Hideo Fujiwara (Osaka Gakuin University)

14:30-16:00 Panel: "Quo vadis high-level test?"Organizer: Prof. Jaan Raik (Tallinn UT, Estonia)Panelists: Bernd Becker (Freiburg University, Germany) Virendra Singh (Indian Institute of Technology Bombay, India) Toshinori Hosokawa (Nihon University, Japan) Artur Jutman (Testonica Lab, Estonia)

16:00-16:10 Closing and Group Photo16:10-17:00 Tea Ceremony

Session 4: Field Test and Aging Analysis (4F Sango)

Session5: Advanced Scan Architecture (4F Sango)

Panel Session (4F Sango)

Day 2: Friday, Nov. 25, 2016

Session 3: RTL Design and Test (4F Sango)

Keynote speech

(Nov. 24, 14:40-15:40)

Automatic generation of test programs from high-level processor

descriptions: an academic dream?

Prof. Matteo Sonza Reorda (Politecnico di Torino, Italy) Abstract: The usage of functional programs to test processors is popular in several scenarios. However, these test programs often come from the re-use of application code or from random generation. In some cases, they are manually generated to achieve a given coverage value with respect to some target metric. Clearly, automating the generation process would be highly desirable, especially if we could start from a high-level description of the target processor. The talk will highlight the state of the art, identify the main obstacles and challenges, and emphasize the research opportunities in this area. Presenter: Matteo Sonza Reorda received his MS degree in Electronics (1986) and PhD degree in Computer Engineering (1990), both from Politecnico di Torino. He is a Full Professor at the Dept. of Control and Computer Engineering of the same University and leads the research group on test and fault tolerance there. He is involved in several research projects funded by public bodies and industries. He is a Fellow of IEEE. His research interests include test of SoCs and fault tolerant electronic system design.

Invited talk

(Nov. 24, 15:40-16:10)

Why Open Defects Should Be Explicitly Targeted

During Test

Prof. Adit D. Singh (Auburn University, USA) Abstract: New cell-aware test methods have recently received much publicity because of their success in screening significant defectivity missed by traditional stuck-at and transition delay fault (TDF) testing. For example, at ITC 2012, Hapke et al. reported 885 DPPM test escapes in a 32 nm notebook processor part despite industrial strength stuck-at and 5-detect TDF testing. Importantly, most of these test escapes were observed to cause failure in actual system application, pointing to a potentially serious field reliability issue. Careful analysis indicates that the large majority of the additional fallout from cell aware tests are open defects. In this presentation we make the case that intra gate open defects should be directly targeted during ATPG aimed at generating the most cost effective test sets. Since two-pattern tests for open defects also cover corresponding TDFs, the increase in test set size over current stuck-at and TDF is modest, while such tests can significantly improve actual defect coverage in production. Additionally, if very low defect levels are required, hazard activated opens that appear redundant in steady state signal analysis, must also be targeted. Efficient testing for these defects is more challenging and remains an open research problem. Presenter: Adit D. Singh is currently James B. Davis Professor of Electrical and Computer Engineering at Auburn University, USA. Before joining Auburn in 1991, he served on the faculty at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He has published over two hundred research papers, served as a consultant to many semiconductor companies, and holds international patents that have been licensed to industry. He has had leadership roles as General Chair/Co-Chair/Program Chair for dozens of international VLSI design and test conferences and has also served on the editorial boards of several journals, including IEEE Design and Test and JETTA. He served two elected terms (2007-11) as Chair of the IEEE Test Technology Technical Council (TTTC), and on the Board of Governors (2011-15) of the IEEE Council on Design Automation (CEDA). Singh is a Fellow of IEEE and a Golden Core member of the IEEE Computer Society.

Invited talk

(Nov. 25, 11:45-12:10)

Multi-Level High-Throughput Simulation for Design & Test Validation

Prof. Hans-Joachim Wunderlich (University of Stuttgart, Germany� Abstract: Design and test validation is one of the most important and complex tasks within modern semi-conductor product development cycles. Both tasks analyze a design with respect to certain validation targets to ensure the compliance with given specifications or requirements, for instance timing, power, or test and product quality. The type of specification can range from abstract high-level functional behavior of the circuit down to constraints of parameters at lower levels, such as peak power consumption or transistor stress. With process scaling, not only variations but also more complex defect mechanisms have to be considered in simulation, requiring models and algorithms for analysis of effects at switch or even electrical level. Yet, state-of-the-art algorithms for the required model accuracy rely on compute-intensive simulations that do not scale to the dimensions of current and future designs. Over the past years, data-parallel architectures, such as Graphics Processing Units (GPUs), have evolved and introduced the many-core paradigm. Scalable simulation algorithms optimized for such architectures provide very high throughput allowing for the first time exhaustive timing-accurate fault simulation or switch-level simulation for large circuits, for instance. This is enabled by careful abstraction in the modeling and by tailoring the algorithmic kernels to the many-core features. Current research aims at further increasing the modeling accuracy and at hybrid approaches that employ models at different abstraction levels. Presenter: Hans-Joachim Wunderlich is a full professor and the director of the Institute of Computer Architecture and Computer Engineering at the University of Stuttgart. He studied Mathematics and Philosophy at the Universities of Konstanz and Freiburg, Germany, and received his PhD degree (Dr. rer. nat.) from the University of Karlsruhe in 1986. Since then, he has worked as a professor at the universities of Karlsruhe, Duisburg, Siegen and Stuttgart. For more than 32 years, Prof. Wunderlich contributed to the areas of VLSI testing, Design for Test, Dependability, Fault Tolerance and Design Automation. He published more than 250 books and articles in these fields, and led numerous projects funded by industry, European Commission, German government or national funding organizations like DFG. Prof. Wunderlich was recipient of the award for excellent academic teaching of the state of Baden-Württemberg, was promoted Golden Core Member of the IEEE Computer Society, and was elevated Fellow of the IEEE.

Panel session

(Nov. 25, 14:30-16:00)

"Quo vadis high-level test?" Organizer: Prof. Jaan Raik (Tallinn UT, Estonia) Panelist: Prof. Bernd Becker (Freiburg University, Germany) Prof. Virendra Singh (Indian Institute of Technology Bombay, India) Prof. Toshinori Hosokawa (Nihon University, Japan) Dr. Artur Jutman (Testonica Lab, Estonia) Abstract: The panel will focus on future trends and use cases of high-level test. The topic of higher abstraction levels to improve the scalability of test generation was a promise in 1990s and early 2000s. However, industry adoption of applying high-level test in design automation has been slow. Are there any trends that could renew the boom of high-level testing? Will there be emerging new standards to support test automation at higher abstraction levels? If so then what will be the future applications of high-level test techniques? A group of distinguished experts from the academy and industry will share there knowledge on these as well as other related questions at the WRTLT’16 panel discussion.