Www.eit.Lth.se Fileadmin Eit Courses Eti180 Slides2011 Lec-PipePar

8/13/2019 Www.eit.Lth.se Fileadmin Eit Courses Eti180 Slides2011 Lec-PipePar

1/23

DSP Design

andParallel Processing

Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden-www.eit.lth.se

DSP Desig n

Pipelining Splits the logic path by introducing pipiline registers

leads to a reduction of the critical path but introduce latency

power consumption at same speed in a DSP system

Parallel Processing Multiple outputs are computed in parallel in a clock period Can also be used to reduce the power consumption


DSP Design

pe n nga b

x(n) ax(n) abx(n)

a bx n abx(n-1)

Z-1

Critical path cut in half Introduced

double clock speedor

1cc


lower power consumption due to reduced V DD

DSP Desig n

a b

x(0), x(1), x(2)...

a bk=0,1,2,3...

x ax(2k) a x x(0), x(2), x(4)...

x(2k+1) ax(2k+1) abx(2k+1)x(1), x(3), x(5)...

Two samples are processed in parallel double throughput


or lower power consumption due to reduced V DD


2/23

DSP Design

Direct Form 4-tap FIR

D D Dx(n)

h0 h3h2h1

y(n)

Clock speed limited by Critical Path!Critical M - A

N = Nr. of Ta s


DSP Desig n

DefinitionsCutset: A set of edges that if removed, or cut,results in two disjoint graphs.

Feedforward Cutset: if data is moved in forwarddirection on all cutsets. D D Dx(n)

h0 h3h2h1

y(n)

. A B

Viktor wall, Dept. of Electrical and Information Technology, Lund University, Sweden-www.eit.lth.seD

DSP Design

PipeliningPipelining: Placing delays at feedforward cutsets.

D D Dx(n)

h0 h3h2h1

y(n)

Feedforward


DSP Desig n

PipeliningPipelining: Placing delays at feedforward cutsets.

D D Dx(n) D

h0 h3h2h1

y(n-1)D

Pipeline stagePi elinin will not affect functionalit


but introduce latency!


3/23


4/23


5/23


6/23

DSP Design

ECombinatorial

Logic E

Logic depth t min t max

e ayNew input data is

previous computation

is done.

Tclk < Tcritical path


timen 0 Tclk

DSP Desig n

Wave pipelining: Pros and cons?

+ shorter Tclk

- extensive simulation-- hard to verify-


DSP Design

Double Pumped Bus?


DSP Desig n

Parallel processing and pipelining techniques are duals each other: if a

, .exploit concurrency available in the computation in different ways.

How to design a Parallel FIR system? - -

y(n)=ax(n)+bx(n-1)+cx(n-2)

Convert the SISO system into an MIMO (multiple-input multiple-output)system in order to obtain a parallel processing structure

y(3k)=ax(3k)+bx(3k-1)+cx(3k-2)-

y(3k+2)=ax(3k+2)+bx(3k+1)+cx(3k)


,inputs processed in a clock cycle is referred to as the block size


7/23


8/23


9/23

DSP Design

ara e - ap

)1()0()1()1( 210

210

x b x b x b y

x x x y

D x(2k-1)x(2k)x(2k+1)

2 In utsD

x(2k-2)

0

y(2k)

1 2

b0 b1 b2


DSP Desig n

ara e - ap

)1()0()1()1( 210

210

x b x b x b y

x x y

D x(2k-1)x(2k)x(2k+1)

2 In utsD

x(2k-2)

0

y(2k)

1 2

b0 b1 b2


DSP Design

ara e - ap

)1()0()1()1( 210

210

x b x b x b y

x x x y

D x(2k-1)x(2k)x(2k+1)

2 In utsD

x(2k-2)

0

y(2k)

1 2

+b0 b1 b2


DSP Desig n

system remains unchanged. But since L samples arerocessed in 1 clock c cle the iteration or sam le eriod is

given by the following equations:

T T T A M clock 2 for a 3-tap FIR filter

LT T clock sampleiteration

So, it is important to understand that in a parallel system

Tsample Tclock , whereas in a pipelined system Tsample = Tclock



10/23

DSP Design

ara e rocess ng con

Consider the following chip set: when the critical path is less than the I/Obound (output-pad delay plus input-pad delay and the wire delay between

e wo c ps , we say s sys em s commun ca on oun e

So, we know that pipelining can be used only to the extent such that thecritical path computation time is limited by the communication (or I/O)bound. Once this is reached, pipelining can no longer increase the speed

Chip 1 Chip 2

output pad

input pad

ioncommunicat


ncomputat o

DSP Desig n

So in such cases i elinin can be combined with arallel

processing to further increase the speed of the DSP system

(pipelining stage: M), the sample period can be reduced to:

T T T clock sampleiteration

consumption while using slow clocks


DSP Design

A serial-to-parallel converter

DDx(n)

DT/4 T/4 T/4

+

Sample Period T/4

TT T T

x(4k+3) x(4k+2) x(4k+1) x(4k)

A parallel-to-serial converter

y(4k+3) y(4k+2) y(4k+1) y(4k)

4k

DD DT/4 T/4 T/4


DSP Desig n

Parallel FIR withPolyphase Decomposition



11/23

DSP Design

1 N

n nY H X h n x n

0 0n n

h(n)x(n) y(n)

x(n)

3

y(n)

012

Idea: Split to an L-parallel


filter and reduce the strength

DSP Desig n

Split the input sequence1 2 3 4 5( ) (0) (1) (2) (3) (4) (5) X z x x z x z x z x z x z

0 2 4( ) (0) (2) (4) X z x z x z x z

1 2 4(1) (3) (5) z x x z x z

2 1 2( ) ( ) ( ) X z X z z X z )2()(

2

k xof transform Z are z X

x 2k 2k


nx n y n n y(2k+1)x(2k+1)

DSP Design

Split the filter accordingly1 2 3 4 5( ) (0) (1) (2) (3) (4) (5) H z h h z h z h z h z h z

2 1 20 1( ) ( ) ( ) H z H z z H z

and( ) ( ) ( )Y z H z X z

2 1 2 2 1 20 1 0 1( ) ( ) ( ) ( ) H z z H z X z z X z


DSP Desig n

2 1 2 2 1 20 1 0 1( ) ( ) ( ) ( ) H z z H z X z z X z

0 0 1 1( ) ( ) ( ) ( ) H z X z z H z X z

0 1 1 0( ) ( ) ( ) ( ) z H z X z H z X z

0 0 0 1 12 2 2 2 2

z z z z z z



12/23

DSP Design

Split h(n) inx(2k)

wofiltersH0: Even Coef.H1: Odd Coef.

y(2k+1)x(2k+1)

H0

H1 D

2 2 2 2 2 20 0 0 1 1

2 2 2 2 2

( ) ( ) ( ) ( ) ( )Y z X z H z z X z H z


DSP Desig n

Split h(n) inx(2k)

wofiltersH0: Even Coef.H1: Odd Coef.

y(2k+1)x(2k+1)

H0

H1 D

2 2 2 2 2 20 0 0 1 1

2 2 2 2 2

( ) ( ) ( ) ( ) ( )Y z X z H z z X z H z

Y z X z H z X z H z


DSP Design

Example h 2 h 0

y0 = x0 h0x(2n)

y(2n)

3 1

h h

y(2n+1)x(2n+1)

h 3 h 1


DSP Desig n

Example h 2 h 0

y0 = x0 h0x(2n)

y(2n)

y1 = x0 h1 + x1 h03 1

h hy2 = x0 h2 + x1 h1 +

y(2n+1)x(2n+1)

+ x2 h0

h 3 h 1



13/23

DSP Design

Criticalh 2 h 0

No Strengthpath

x(2n)y(2n)Reduction yet

2N Multi lications er 3 1

two samples

h hPower can be saved:

y(2n+1)

x(2n+1)

Slightly increasedcritical path but 2

h 3 h 1

samp e per o s


DSP Desig n

-


DSP Design

Polyphase Filters

Filter Mult Add SubfiltersFIR N N-1 1

- -3-Parallel 3 N 3(N-1) 9L-Parallel L N L(N-1) L

However, they give L samples each cycle


DSP Desig n

Fast FIR Filters

112

000 X H z X H Y

10011 X H X H Y 0 0 2 4, , ,... H h h h 1 1 3 5, , ,... H h h h

0 1 0 1 2 3 4 5, , , ... H H h h h h h h

11000 X H z X H Y


110010101


14/23

DSP Design

Fast FIR Filters

112

000 X H z X H Y

10011 X H X H Y H0 y(2k)x(2k)

y(2k+1)H0 +H 1

H1x(2k+1)

11000 X H z X H Y


110010101

DSP Desig n

e uce omp ex y

N/2 MultH

0 y(2k)x(2k)

eachy(2k+1)H0+H 1

N/2-1 Addeach

H1x(2k+1)

Total

= . u s compare o 3(N/2 - 1) + 4 = 1.5N + 1 Adds compared to 2(N - 1)


DSP Design

ast xamp ex(2n)

2n

h 2 h 0H0+H1 Precomputed

y(2n+1)

h 0+h 1h 2+h 3

x(2n+1)

h 3 h 1

and 3.5 Add per


DSP Desig n

112

000 X H z X H Y

10011 X H X H Y

H0

(2k+1)H -H

y(2k)x(2k)

H1x(2k+1)

11

2000 X H z X H Y

))(( 101011001 X X H H X H X H Y



15/23

DSP Design

LP n H0-H1 might be better for lowpass and

H0+H1 might be better for highpassers

Saves power

H y(2k)x(2k)

y(2k+1)H0-H1h HP (n)

H1x(2k+1)0


DSP Desig n

Transposition

edges andn erc ange

in- outputs


DSP Design

e uce omp ex y -para e


DSP Desig n

e uce omp ex y -para e

H0H +H

H1

Two Cascaded 2-parallel filters



16/23

DSP Design

-arallel

3-parallel filtersn a para estructure


DSP Desig n

as -para e

3 cascaded

2- arallel filters


DSP Design

Traditional Fast FIR

FIR N N-12-Parallel 2 N 2 N-1 1.5N 1.5N+13-Parallel 3 N 3(N-1) 2N 2N+44-Parallel 4 N 4(N-1) 9N/4 20+9(N/4-1)

(n m)-parallel filter with n=2, m=2


DSP Desig n

=

Filter Mults Adds Mults AddsFIR 8 72-Parallel 16 14 12 113-Parallel 24 21 16 204-Parallel 32 28 18 29

N=1000 Traditional Reduced ComplexityFilter Mults Adds Mults AddsFIR 1000 9992-Parallel 2000 1998 1500 1499

-4-Parallel 4000 3996 2250 2261


e uce omp ex y:


17/23

DSP Design

Pipeliningand

for Low Power


DSP Desig n

Power Dissipation

Two measures are important

Avera e ower Batter and coolin

peak DD DDmax

V TDDT 0

DDav


Or rather energy

DSP Design

Power consumption in CMOS

importance with

staticcircuit-shortdynamictotal

The one we will look at

and reduce withpipelining and


parallelism

DSP Desig n

CMOS Power Consumption

PPPP staticcircuit-shortdynamictot VIIVVCf DDleakagescDDDDL



18/23

DSP Design

Short Circuit - Current Spikes

Current peak when both N- and PMOS are open

V -V

VT

Ipeak


DSP Desig n

due to leakage current

Ileakage increasesVDD w ecreas ng T

stat leakage DDDrain Leakage

ea age

SubthresholdCurrent


DSP Design

T T OFF -

Performance vs I D

S ) Low VT

Leakage:

T l n

(

T OFF IOFFL

VGVTH

OFFH

VTL

As VT decreases, sub-threshold leakage increases


DSP Desig n

Assumed that V swing =VDD, otherwise V swing VDD

nergy c arge n a capac or EC = CV2 /2 = CLVDD2 /2

VDD

Energy E c is also discharged, i.e.Charge

Etot= CL VDD2

Power consumptionP = CL VDD2 fsc argeSince squared most


efficient to reduce P


19/23

DSP Design

Reduce...apac ances

Transistor/Gate C oa Interconnects, more and more important x erna

ActivityFrequency

ower supp y square so mos e c en


...w ou re uc ng per ormance .

DSP Desig n

Propagation Delay in CMOS

V C W 2)( T DD pd V V k

ox L,,,

T DD

T L pd proportional to


DD DD

DSP Design

Propagation Delay in CMOS

is a valid assumption?T DD V V 2

L

)( T DD DD

pd V V k V C

T


Shouri Chatterjee, Yannis Tsividis and Peter Kinget,Analog Circuit Design Techniques at 0.5V

DSP Desig n

pe n ng, power consumpt ona b

x(n) ax(n) abx(n)

x(n)a b

abx n-1

ax(n)

-

ax(n-1)Critical path cut in half

double double throu h ut DDV C f P

or


DD


20/23

DSP Design

e uc on o r ca a

Propagation delay of the original filter and the

seqT Sequential (critical path):

Pipelined: (critical path when M=3)0

pipeT 0V pipeT pipeT


DSP Desig n

The power consumption in original architecture

pe n ng, power consumption

2 seq

The supply voltage can be reduced to V DD , (0<


21/23


22/23

DSP Design

o a capac ance, , s ncrease y

To maintain the same sam le rate f is reduced by 1/L

f reduced V DD can be reduced


DSP Desig n

ara e rocess ng

a b= , , , ...

a b

, , ...

x(2k+1) ax(2k+1) abx(2k+1)x(1), x(3), x(5)...

2 2( ) p a r a L D D s e qP L C V P L


DSP Design

Sequential (critical path):

seq

Parallel: critical ath when L=3 0V

V

seqT 3 seqT 3

seqT 3

-

22 DD L DD L

seq par

V C L

V C T LT

T DDT DD


22 )()( T DDT DD V V V V L

DSP Desig n

2.15 due to mux

0.36P(0.58V) 2.15C 0.5f P 2 par a

Register Register Register

cb a


cb



23/23

DSP Design

ara e rocess ng an pe n ng

0.19P(0.4V) 2.35C 0.5f P 2 pipe par, a


cb a


cb

Register Register Register Register

stage


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Www.eit.Lth.se Fileadmin Eit Courses Eti180 Slides2011 Lec-PipePar