X-band Medium Power Amplifier€¦ · X-band Medium Power Amplifier AI1807 June 2018 Advanced Information Ref. : AI18078166 - 15 Jun 18 5/15 Subject to change without notice Bât

AI1807

Ref. : AI18078166 - 15 Jun 18 1/15 Subject to change without notice

United Monolithic Semiconductors S.A.S. Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France

Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 - www.ums-gaas.com

Advanced Information: AI1807

X-band Medium Power Amplifier

GaN Monolithic Microwave IC SMD Ceramic Hermetic package

UMS develops a two stage Medium Power Amplifier operating between 8 and 12.75GHz. It typically provides 5W of saturated output power and 34% of Power Added Efficiency.

It is designed for a wide range of applications, from space and military to commercial communication systems.

The circuit is manufactured with a GaN HEMT process, 0.25µm gate length, via holes through the substrate, air bridges and electron beam gate lithography. It is proposed in leadless surface mount hermetic metal ceramic 6x6mm² package, compliant with the regulation in particular with the directives RoHS N°2011/65 and REACh N°1907/2006.

■ Broadband performances: 8-12.75GHz

■ 22dB Linear Gain

■ 37dBm output power @ saturated power.

■ DC bias: Vd=25.0Volt@Idq=200mA

■ 6x6mm² hermetic metal ceramic package

In Out

V+

V-

STG1 STG2

AI1807 June 2018


Advanced Information Ref. : AI18078166 - 15 Jun 18 2/15 Subject to change without notice

Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France Tel.: +33 (0) 1 69 86 32 00 - Fax: +33 (0) 1 69 86 34 34 - www.ums-gaas.com

Electrical Characteristics (pulse mode)

Tamb.= +25°C, Vd = +25V, Idq = 200mA, Pulse width=25µs, Duty cycle =10%

Symbol Parameter Min Typ Max Unit

Freq Frequency range 8 12.75 GHz

Gain Linear Gain 22 dB

Pout Output Power (Pin=23dBm) 5 W

PAE Associated Power Added Efficiency (Pin=23dBm)

34 %

Id Associated current (Pin=23dBm) 0.55 A

Idq Quiescent Current 0.2 A

Vd Drain Voltage 25 V

Vg Gate Voltage -3.2 V

These values are representative of measurements done in test fixture.

Electrical Characteristics (CW mode) Tamb.= +25°C, Vd = +25V, Idq = 200mA

Symbol Parameter Min Typ Max Unit

Freq Frequency range 8 12.75 GHz

Gain Linear Gain 21.5 dB

Pout Output Power (Pin=23dBm) 4.5 W

PAE Associated Power Added Efficiency (Pin=24dBm)

33 %

Id Associated current (Pin=24dBm) 0.53 A

Idq Quiescent Current 0.2 A

Vd Drain Voltage 25 V

Vg Gate Voltage -3.2 V

These values are representative of measurements done in test fixture.


AI1807 June 2018


Bât. Charmille - Parc SILIC - 10, Avenue du Québec - 91140 VILLEBON-SUR-YVETTE - France


Absolute Maximum Ratings (1)

Tamb.= +25°C

Symbol Parameter Values Unit

Vd Drain bias voltage 55V V

Pin Maximum peak input power overdrive 30 dBm

Pdiss Maximum dissipated power 22 W

Tj Junction temperature 230 °C

Tstg Storage temperature range -55 to +150 °C (1) Operation of this device above anyone of these parameters may cause permanent damage.

Typical Bias Conditions

Tamb.= +25°C

Symbol Pad No Parameter Values Unit

Vd Vd1, Vd2 Drain voltage 25 V

Vg Vg1, Vg2 Gate voltage

HPA on (pulsed mode)

HPA on (CW mode)

HPA off

-3.2

-3.25

-8 to -5

V

V

V

Bias-up Procedure

1. Bias HPA gate voltage at Vg close to Vpinch-off (Typically: Vg -5V)

2. Apply Vds bias voltage (Typically: Vd = 25V)

3. Increase slowly Vgs up to quiescent bias drain current Idq (pulsed applied on the gate)

4. Apply RF signal

Bias-down Procedure

1. Turn off RF signal

2. Bias HPA gate voltage at Vg close to Vpinch-off (Typically: Vg -5V)

3. Turn Vds bias voltage to 0V

4. Turn Vgs bias voltage to 0V

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Device thermal performances

All the figures given in this section are obtained assuming that the SMD package device is only cooled down by conduction through the package thermal pad (no convection mode considered).

The temperature is monitored at the package back-side interface (Tcase).

The system maximum temperature must be adjusted in order to guarantee that Tjunction remains below the maximum value specified in the Absolute Maximum Ratings table.

So, the system PCB must be designed to comply with this requirement.

Parameter Biasing

conditions

Tjunction

(°C) RTH

( °C/W) T50

( hours)

RTH (1)

Thermal Resistance ( Junction to Case)

Vd= 25V

Id= 510mA Pdiss= 9.5W

156 7.5 4x107

(1) Assuming 85°C Tcase

Parameter Biasing

conditions

Tjunction

(°C) RTH

( °C/W) T50

( hours)

RTH (1)

Thermal Resistance ( Junction to Case)

Vd= 30V

Id= 550mA Pdiss= 11.5W

173 7.7 1x107


AI1807 June 2018




Typical Board Measurements (CW mode)

Tamb.= +25°C, Vd = +25V & +30V, Idq = 200mA

Linear gain versus Frequency (VD.=+25V & +30V, Temp=+25°C)

Output power versus Frequency (VD.=+25V & +30V, Temp=+25°C)

AI1807 June 2018





Tamb.= +25°C, Vd = +25V & +30V, Idq = 200mA

Power Added Efficiency versus Frequency (VD.=+25V & +30V, Temp=+25°C)

Drain Current versus Frequency (VD.=+25V & +30V, Temp=+25°C)


AI1807 June 2018





Tamb.= +25°C, Vd = +25V, Idq = 200mA

Gain versus Input Power (Temp=+25°C)

Output Power versus Input Power (Temp=+25°C)

AI1807 June 2018





Tamb.= +25°C, Vd = +25V, Idq = 200mA

Power Added Efficiency versus Input Power (Temp=+25°C)

Drain Current versus Input Power (Temp=+25°C)


AI1807 June 2018




Typical Board Measurements (Pulsed mode)

Tamb.= +25°C, Vd = +25V & +30V, Idq = 200mA, Pulse width=25µs, Duty cycle =10%

Linear gain versus Frequency (VD.=+25V & +30V, Temp=+25°C)

Output Power versus Frequency (VD.=+25V & +30V, Temp=+25°C)

AI1807 June 2018





Tamb.= +25°C, Vd = +25V & +30V, Idq = 200mA, Pulse width=25µs, Duty cycle =10%

Power Added Efficiency versus Frequency (VD.=+25V & +30V, Temp=+25°C)

Drain Current versus Frequency (VD.=+25V & +30V, Temp=+25°C)


AI1807 June 2018






Gain versus Input Power (VD=25V, Temp=+25°C)

Output Power versus Input Power (VD=25V, Temp=+25°C)

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Power Added Efficiency versus Input Power (Temp=+25°C)

Drain Current versus Input Power (Temp=+25°C)


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Package outline (1)

Units: mm 1- Gnd(2) 8- RF out 15- Gnd(2)

2- Gnd(2) 9- Gnd(2) 16- Nc

3- Vd1 10- Gnd(2) 17- Gnd(2)

4- Vd2 11- Gnd(2) 18- RF in

5- Gnd(2) 12- Vg2 19- Gnd(2)

6- Nc 13- Gnd(2) 20- Nc

7- Gnd(2) 14- Vg1 21- Gnd(2)

(1) The package outline drawing included to this data-sheet is given for indication. Refer to the application note AN0017 (http://www.ums-gaas.com) for exact package dimensions.

(2) It is strongly recommended to ground all pins marked “Gnd” through the PCB board. Ensure that the PCB board is designed to provide the best possible ground to the package.

http://www.ums-gaas.com/

AI1807 June 2018




Definition of the Sij reference planes

The reference planes used for Sij measurements given above are symmetrical from the symmetrical axis of the package (see drawing beside). The input and output reference planes are located at 3.39mm offset (input wise and output wise respectively) from this axis. Then, the given Sij parameters incorporate the land pattern of the evaluation motherboard recommended in paragraph "Evaluation mother board".

Package Information

Parameter Value

Package body material RoHS-compliant

Lead finish Gold

Hermetic sealing (fine leak compliant Mil-Std-883 Method 1014.10 Condition A4, tracer gas He at 1atm)

1x10-8 ccHe/s/atm


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Evaluation board description

■ Compatible with the proposed footprint.

■ Based on typically Ro4003 / 8mils or equivalent.

■ Using a micro-strip to coplanar transition to access the package.

■ Recommended for the implementation of this product on a module board.

■ Decoupling capacitors of 120pF + 10nF are recommended on each DC access (Vg1 / Vg2 / Vd1 / Vd2) in CW mode.

■ Decoupling capacitors of 10nF are recommended on each DC gate access (Vg1 & Vg2) in CW mode.

■ Decoupling capacitors of 120pF + 10nF are recommended on each DC drain access (Vd1 & Vd2) in CW mode.

Documents

X-band Medium Power Amplifier€¦ · X-band Medium Power Amplifier AI1807 June 2018 Advanced Information Ref. : AI18078166 - 15 Jun 18 5/15 Subject to change without notice Bât