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by Jeff GarrisonDirector of Marketing, FPGA ProductsSynplicity,
[email protected]
Advances in FPGA technology have
opened the door wide open for use in all
types of applications, including wirelesscommunications,
computer, industrial,
defense/aerospace, medical, automotive,
and even consumer. Xilinx Virtex-4
devices have the capacity, performance, and
cost structure to lead a migration from tra-
ditional cell-based ASICs to programmable
devices in all but the highest volume and
bleeding-edge applications. Along with this
capability, however, are new challenges
from a designers perspective. In this article,
Ill discuss a solution to one of these most
important challenges timing closure.One of the biggest reasons
to use
FPGAs in the first place is their ability to
deliver working silicon to an electronics
system quickly and reliably. As the com-
plexity of FPGAs and all integrated circuits
has increased, the time-to-market advan-
tage offered by FPGAs could be dimin-
ished if you do not make significant
changes to your core design technology.
The primary issue is timing closure the
ability to reach your designs timing goals
in a fast, predictable way. Gone are the
days when logic delay and wire-load mod-
els for interconnect delay are enough to
estimate timing and give predictable
results. In 90 nm FPGAs, you must incor-
porate actual routing delay into the syn-
thesis process to achieve rapid timing
closure for high-performance designs.
Timing Accuracy is EverythingThe underlying problem that
determines if
you will be able to close on timing is esti-
mation accuracy. Historically, synthesis and
placement tools have been based on the
assumption that the proximity of logic and
wire-load estimation determines the routing
delay. Although this used to work reason-
ably well for ASIC design, it does not work
at all for FPGAs. Unlike an ASIC, FPGA
routing is pre-determined. In an ASIC therouting is customized
for the placement of
the logic. In other words, once the place-
ment of an ASIC is done, it is relatively easy
to get a good estimation of routing delay by
measuring Manhattan distances from one
point to another (see Figure 1).
Because FPGAs have fixed routing
resources, the design tool needs to under-
stand the different types of routing and its
implication on timing. In an FPGA, the
fastest routing between two points may very
well not be the shortest. Think of your com-
mute to work sometimes its faster to go
slightly out of your way and get on a freeway
than to travel the shorter distance on side
streets. The same concept applies to FPGAs
some direct routing resources (freeways) are
faster than those that have to go through
switch matrices (side streets) (Figure 2).Figure 3 illustrates
how placement is dif-
ferent for proximity- and graph-based tools.
Graph-Based Physical SynthesisSynplicity invented graph-based
physical
synthesis to improve timing closure by
means of a single-pass physical synthesis
flow for 90 nm FPGAs. The essence of the
graph-based approach is that the pre-exist-
ing wires, switches, and placement sites used
for routing an FPGA can be represented as a
detailed routing resource graph. The notionof distance then
changes from proximity to
a measure of delay and wire availability.
Synplicitys graph-based physical syn-
thesis technology merges optimization,
placement, and routing to generate a fully
placed and physically optimized design,
providing rapid timing closure and a 5% to
20% timing improvement.
Graph-based physical synthesis does not
require you to create a floorplan or provide
other information to the physical synthesis
Achieve Faster Timing Closure
with Graph-Based Physical Synthesis
Achieve Faster Timing Closure
with Graph-Based Physical Synthesis
12 Xcell Journal Fourth Quarter 200
Graph-based physical synthesis was invented to improve
timingclosure by means of a single-pass physical synthesis
flow.Graph-based physical synthesis was invented to improve
timingclosure by means of a single-pass physical synthesis
flow.
D E S I G N P E R F O R M A N CE
Copyright 2005 Xilinx, Inc. All rights reserved. XILINX, the
Xilinx logo, and other designated brands included herein are
trademarks of Xilinx, Inc. All other trademarks are the property of
their respective owners.
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process (often only known by expert users)
in order to get good results. It is a fully
automated methodology that can be used
without special knowledge of the physical
FPGA device. In addition to this fully auto-
mated mode, you do have the option to
guide physical synthesis by providing design
planning information (such as a floorplan)
used during the physical synthesis process.
Synplify Premier
To directly address the challenge of keeping
timing closure under control for advanced
FPGA technologies, Synplicity has intro-
duced Synplify Premier, its first FPGA
design product based on graph-based physi-
FPGA directly in the RTL source code or in
waveform. An incremental place and route
capability saves time by allowing you to
quickly update instrumented nodes and
debug. The debugging technology within
Synplify Premier software is closely integrat-
ed with synthesis and Xilinx ISE software
for a seamless development environment.
A second technology important for ASIC
prototyping with FPGAs is the ability to
convert gated clocks to FPGA clock-enable
structures without modifying your RTL
source. Synplify Premier performs this task
automatically, along with handling generat-
ed clocks and instantiations of most com-
mon Synopsys DesignWare components.
ConclusionBecause of the increased design complexi-
ty enabled by new devices such as Virtex-
4 FPGAs, designers need EDA tools that
can handle the physical properties of
FPGA architecture to achieve acceptable
timing closure. Several physical design
tools based on ASIC technologies have
been used to address FPGA design, but
they have had little success. The ASIC
approach does not work for FPGAsbecause the silicon fabric is
completely
different and, unlike ASICs, proximity
does not imply better timing.
Synplicitys Synplify Premier product
with graph-based physical synthesis direct-
ly addresses the challenges of FPGA physi-
cal design and results in faster designs done
in less time. For more information on
graph-based physical synthesis, ASIC pro-
totyping, and Synplify Premier, visit
www.synplicity.com/products/index.html.
cal synthesis technology. Synplify Premier
includes all of the features in Synplify Pro
and adds graph-based physical synthesis for
the Virtex-4, Virtex-II Pro, and Spartan-3
families. In addition to the new graph-based
physical synthesis, Synplify Premier also
offers a new capability for debugging and
prototyping ASICs using FPGAs. One such
technology is RTL instrumentation and
debugging of live, running FPGAs.
This technology is based on Synplicitys
Identify product, which allows you to navi-
gate your design graphically and mark sig-
nals directly in your RTL code as probes or
sample triggers. After synthesis, you can
view the signal values of a live, running
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Driver and loadsconnected withdirect, orthogonalrouting is
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Short, but slowconnection
Longer, but fastdirect connection
Optimal Graph-BasedPlacement forBest Performance
Traditional Proximity-BasedPlacement
CLB with 4 LUTs, 4 Flops, and
No Intra-CLB Direct Connect
Figure 1 Proximity-based placement isbest when you use flexible
routing.
Figure 2 A graph-based approach is best whenrouting is fixed and
of differing performance levels.
Figure 3 Graph-based placement for LUT driving four flops
Fourth Quarter 2005 Xcell Journal 1
D E S I G N P E R F O R M A N CE
