xst

RXST User Guide

9.1i

XST User Guide www.xilinx.com 9.1i

Xilinx is disclosing this Document and Intellectual Property (hereinafter the Design) to you for use in the development of designs to operate on, or interface with Xilinx FPGA devices. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes.Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design.THE DESIGN IS PROVIDED AS IS WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS.IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY.The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring fail-safe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air traffic control, life support, or weapons systems (High-Risk Applications). Xilinx specifically disclaims any express or implied warranties of fitness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk.Copyright 1995-2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners.

R

RPreface

About This Guide

This manual describes Xilinx Synthesis Technology (XST) support for HDL languages, Xilinx devices, and constraints for the ISE software. The manual also discusses FPGA and CPLD optimization techniques and explains how to run XST from the Project Navigator Process window and command line.

Guide ContentsThis manual contains the following chapters and appendixes.

Chapter 1, Introduction, provides a basic description of XST, and describes the changes to XST in this release.

Chapter 2, HDL Coding Techniques, describes a variety of VHDL and Verilog coding techniques that can be used for various digital logic circuits, such as registers, latches, tristates, RAMs, counters, accumulators, multiplexers, decoders, and arithmetic operations. The chapter also provides coding techniques for state machines and black boxes.

Chapter 3, FPGA Optimization, explains how constraints can be used to optimize FPGA devices and explains macro generation. The chapter also describes the Virtex primitives that are supported.

Chapter 4, CPLD Optimization, discusses CPLD synthesis options and the implementation details for macro generation.

Chapter 5, Design Constraints, describes constraints supported for use with XST. The chapter explains which attributes and properties can be used with FPGA devices, CPLD devices, VHDL, and Verilog.

Chapter 6, VHDL Language Support, explains how VHDL is supported for XST. The chapter provides details on the VHDL language, supported constructs, and synthesis options in relationship to XST.

Chapter 7, Verilog Language Support, describes XST support for Verilog constructs and meta comments.

Chapter 8, Mixed Language Support, describes how to run an XST project that mixes Verilog and VHDL designs.

Chapter 9, Log File Analysis, describes the XST log file, and explains what it contains.

Chapter 10, Command Line Mode, describes how to run XST using the command line, including the XST run and set commands and their options.

Chapter 11, XST Naming Conventions, discusses net naming and instance naming conventions.XST User Guide www.xilinx.com 39.1i

Preface: About This Guide RAdditional ResourcesTo find additional documentation, see the Xilinx website at:

http://www.xilinx.com/literature

To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at:

http://www.xilinx.com/support

ConventionsThis document uses the following conventions. An example illustrates each convention.

TypographicalThe following typographical conventions are used in this document:

Convention Meaning or Use Example

Courier fontMessages, prompts, and program files that the system displays

speed grade: - 100

Courier bold Literal commands that you enter in a syntactical statement ngdbuild design_name

Helvetica boldCommands that you select from a menu File > Open

Keyboard shortcuts Ctrl+C

Italic font

Variables in a syntax statement for which you must supply values

ngdbuild design_name

References to other manualsSee the Development System Reference Guide for more information.

Emphasis in textIf a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected.

Square brackets [ ]

An optional entry or parameter. However, in bus specifications, such as bus[7:0], they are required.

ngdbuild [option_name] design_name

Braces { } A list of items from which you must choose one or more lowpwr ={on|off}

Vertical bar | Separates items in a list of choices lowpwr ={on|off}4 www.xilinx.com XST User Guide9.1i

ConventionsROnline DocumentThe following conventions are used in this document:

Vertical ellipsis...

Repetitive material that has been omitted

IOB #1: Name = QOUT IOB #2: Name = CLKIN.

.

.

Horizontal ellipsis . . . Repetitive material that has been omittedallow block block_name loc1 loc2... locn;



Blue text

Cross-reference link to a location in the current file or in another file in the current document

See the section Additional Resources for details.

Refer to Title Formats in Chapter 1 for details.

Red text Cross-reference link to a location in another document See Figure 2-5 in the Virtex-II Platform FPGA User Guide.

Blue, underlined text Hyperlink to a website (URL) Go to http://www.xilinx.com for the latest speed files.XST User Guide www.xilinx.com 59.1i

Preface: About This Guide R6 www.xilinx.com XST User Guide9.1i

Preface: About This GuideGuide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Additional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Chapter 1: IntroductionAbout XST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Whats New in Release 9.1i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Macro Inference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Design Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Setting XST Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19XST LOG Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Sample Log File One . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20Sample Log File Two . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Signed/Unsigned Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Chapter 2: HDL Coding TechniquesRegisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

About Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Registers Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Registers Related Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Registers Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Latches. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32About Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Latches Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Latches Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Latches Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Tristates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37About Tristates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Tristates Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Tristates Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37Tristates Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40About Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40Counters Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table of ContentsXST User Guide www.xilinx.com 79.1i

Counters Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41Counters Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54About Accumulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

RAccumulators Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Accumulators Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Accumulators Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57About Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Shift Registers Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Shift Registers Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Shift Registers Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Dynamic Shift Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73About Dynamic Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Dynamic Shift Registers Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Dynamic Shift Registers Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Dynamic Shift Registers Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77About Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Multiplexers Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Multiplexers Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Multiplexers Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85About Decoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Decoders Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Decoders Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Decoders Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Priority Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90About Priority Encoders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Priority Encoders Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Priority Encoders Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Priority Encoders Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Logical Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92About Logical Shifters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Logical Shifters Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Logical Shifters Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Logical Shifters Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

Arithmetic Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97About Arithmetic Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Arithmetic Operators Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Arithmetic Operators Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Arithmetic Operators Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

Adders, Subtractors, and Adders/Subtractors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99About Adders, Subtractors, and Adders/Subtractors . . . . . . . . . . . . . . . . . . . . . . . . . . 99Adders, Subtractors, and Adders/Subtractors Log File . . . . . . . . . . . . . . . . . . . . . . . . 99Adders, Subtractors, and Adders/Subtractors Related Constraints . . . . . . . . . . . . . 100Adders, Subtractors, and Adders/Subtractors Coding Examples . . . . . . . . . . . . . . . 100

Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110About Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Comparators Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Comparators Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111Comparators Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Multipliers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112About Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Multipliers Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1148 www.xilinx.com XST User Guide9.1i

RMultipliers Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114Multipliers Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Sequential Complex Multipliers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116About Sequential Complex Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Sequential Complex Multipliers Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Sequential Complex Multipliers Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . 116Sequential Complex Multipliers Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

Pipelined Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120About Pipelined Multipliers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Pipelined Multipliers Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120Pipelined Multipliers Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Pipelined Multipliers Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

Multiply Adder/Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126About Multiply Adder/Subtractor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126Multiply Adder/Subtractor Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127Multiply Adder/Subtractor Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128Multiply Adder/Subtractor Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Multiply Accumulate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132About Multiply Accumulate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132Multiply Accumulate Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Multiply Accumulate Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133Multiply Accumulate Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138About Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Dividers Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Dividers Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Dividers Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

Resource Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139About Resource Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139Resource Sharing Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140Resource Sharing Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140Resource Sharing Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

RAMs and ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142About RAMs and ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142RAMs and ROMs Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144RAMs and ROMs Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145RAMs and ROMs Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145ROMs Using Block RAM Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205Pipelined Distributed RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Finite State Machines (FSMs). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217Finite State Machines Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221Finite State Machines Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222Finite State Machines Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222

Black Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229About Black Boxes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229Black Box Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229Black Box Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229Black Box Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230

Chapter 3: FPGA OptimizationIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233XST User Guide www.xilinx.com 99.1i

RVirtex Specific Synthesis Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234Macro Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

Arithmetic Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235Loadable Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236Priority Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237ROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238

Using DSP48 Block Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239Mapping Logic Onto Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

About Mapping Logic Onto Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240Mapping Logic Onto Block RAM LOG Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240Mapping Logic Onto Block RAM Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . 241

Flip-Flop Retiming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244Partitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244Incremental Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

INCREMENTAL_SYNTHESIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245RESYNTHESIZE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

Speed Optimization Under Area Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249About Speed Optimization Under Area Constraint . . . . . . . . . . . . . . . . . . . . . . . . . . . 249Speed Optimization Under Area Constraint Examples . . . . . . . . . . . . . . . . . . . . . . . . 249

Log File Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250Design Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251Resource Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251Timing Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Implementation Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255Virtex Primitive Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

About Virtex Primitive Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255Virtex Primitives Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257Virtex Primitives Related Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257Virtex Primitives Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Cores Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259Specifying INITs and RLOCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Specifying INITs and RLOCs Coding Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260PCI Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

Chapter 4: CPLD OptimizationCPLD Synthesis Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

About CPLD Synthesis Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267Global CPLD Synthesis Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Implementation Details for Macro Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268Log File Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270Improving Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Obtaining Better Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271Fitting Large Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27210 www.xilinx.com XST User Guide9.1i

RChapter 5: Design ConstraintsAlphabetized List of Xilinx Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273About Constraints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276Setting Global Constraints and Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276

Synthesis Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276HDL Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277Xilinx Specific Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278Other XST Command Line Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279Custom Compile File List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

VHDL Attribute Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280Verilog Attribute Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280

Verilog-2001 Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280Verilog Meta Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

XST Constraint File (XCF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282XCF Syntax and Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

General Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283Add I/O Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283Box Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285Bus Delimiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287Case . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287Case Implementation Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288Verilog Macros (DEFINE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289Duplication Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290Full Case (Verilog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291Generate RTL Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292Generics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293Hierarchy Separator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294IOSTANDARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295Keep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295Keep Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295Library Search Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298LOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299Optimization Effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299Optimization Goal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300Parallel Case (Verilog) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302RLOC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303Synthesis Constraint File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303Translate Off/Translate On (Verilog/VHDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304Use Synthesis Constraints File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305Verilog Include Directories (Verilog Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305Verilog 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306HDL Library Mapping File (.INI File) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307Work Directory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308

HDL Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310Automatic FSM Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310Enumerated Encoding (VHDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312Equivalent Register Removal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314FSM Encoding Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316Mux Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318Register Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320Resource Sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322XST User Guide www.xilinx.com 119.1i

RSafe Recovery State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323Safe Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325Signal Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326

FPGA Constraints (Non-Timing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328Asynchronous to Synchronous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328Automatic BRAM Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330BRAM Utilization Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333BUFGCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335Cores Search Directories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336Decoder Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337DSP Utilization Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339FSM Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340Power Reduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342Read Cores . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344Resynthesize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346Incremental Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347Logical Shifter Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348Map Logic on BRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350Max Fanout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352Move First Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354Move Last Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357Multiplier Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359Mux Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361Number of Global Clock Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363Number of Regional Clock Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364Optimize Instantiated Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365Pack I/O Registers Into IOBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367Priority Encoder Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367RAM Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369RAM Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371Register Balancing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372Register Duplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376ROM Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378ROM Style . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380Shift Register Extraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381Slice Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383USELOWSKEWLINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384XOR Collapsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385Slice Utilization Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386Slice Utilization Ratio Delta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389Map Entity on a Single LUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391Use Carry Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392Convert Tristates to Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394Use Clock Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396Use Synchronous Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398Use Synchronous Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400Use DSP48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402

CPLD Constraints (Non-Timing) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404Clock Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404Data Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406Macro Preserve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406No Reduce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40712 www.xilinx.com XST User Guide9.1i

RWYSIWYG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407XOR Preserve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410Cross Clock Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411Write Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413Global Timing Constraints Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415XCF Timing Constraint Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416

Constraints Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418XST-Specific Non-Timing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418XST Timing Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425

Implementation Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426Handling by XST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426

Third Party Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429Constraints Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433

Chapter 6: VHDL Language SupportIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435VHDL IEEE Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

VHDL IEEE Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436Non-LRM Compliant Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

File Type Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437Debugging Using Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438

Data Types in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440Overloaded Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441Multi-Dimensional Array Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442

Record Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443Initial Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443

Local Reset/Global Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444Default Initial Values on Memory Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445Default Initial Values on Unconnected Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

Objects in VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446Entity and Architecture Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447

Entity Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447Architecture Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447Component Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448Recursive Component Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449Component Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450Generic Parameter Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450Generic/Attribute Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451

Combinatorial Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452Concurrent Signal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452Simple Signal Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452Selected Signal Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452Conditional Signal Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453Generate Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453Combinatorial Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454If...Else Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456XST User Guide www.xilinx.com 139.1i

RCase Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457For...Loop Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457

Sequential Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458Sequential Process with a Sensitivity List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458Sequential Process Without a Sensitivity List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459Examples of Register and Counter Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459Multiple Wait Statements Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461

Functions and Procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462Assert Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466

STANDARD Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466IEEE Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466Synopsys Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467

VHDL Constructs Supported in XST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468Design Entities and Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471Supported VHDL Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472

VHDL Reserved Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474

Chapter 7: Verilog Language SupportIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475Behavioral Verilog Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476

Variable Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478Legal Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482Module Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482Verilog Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482Continuous Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482Procedural Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483Constants, Macros, Include Files and Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492Generate Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494

Variable Part Selects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495Structural Verilog Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498Parameter/Attribute Conflicts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499Verilog Limitations in XST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499

Case Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499Blocking and Nonblocking Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500Integer Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501

Verilog Attributes and Meta Comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502Verilog Language Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503System Tasks and Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507Verilog Reserved Keywords . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508Verilog-2001 Support in XST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50914 www.xilinx.com XST User Guide9.1i

RChapter 8: Mixed Language SupportIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511Mixed Language Project File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512VHDL And Verilog Boundary Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512

Instantiating a Verilog Module in a VHDL Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 512Instantiating a VHDL Design Unit in a Verilog Design . . . . . . . . . . . . . . . . . . . . . . . . 513

Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514Generics Support in Mixed Language Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514Library Search Order File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

Project Navigator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515Search Order Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515

Chapter 9: Log File AnalysisIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519Reducing the Size of the LOG File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520

Quiet Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520Silent Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521Hiding Specific Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

Timing Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522FPGA Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522CPLD Log File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530

Chapter 10: Command Line ModeIntroduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537

File Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537Names with Spaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538Launching XST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538

Setting Up an XST Script . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539Run Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539Set Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542Elaborate Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542

Synthesizing Designs Using Command Line Mode . . . . . . . . . . . . . . . . . . . . . . . . . 543Synthesizing VHDL Designs Using Command Line Mode . . . . . . . . . . . . . . . . . . . . 543Synthesizing Verilog Designs Using Command Line Mode . . . . . . . . . . . . . . . . . . . . 545Synthesizing Mixed VHDL and Verilog Designs Using Command Line Mode . . . 548

Chapter 11: XST Naming ConventionsNet Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551Instance Naming Conventions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551Name Generation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552XST User Guide www.xilinx.com 159.1i

R16 www.xilinx.com XST User Guide9.1i

RChapter 1

Introduction

This chapter provides a basic description of XST, and describes the changes to XST in this release. This chapter contains the following sections.

About XST

Whats New in Release 9.1i

Setting XST Options

XST LOG Files

Signed/Unsigned Support

About XSTXilinx Synthesis Technology (XST) is a Xilinx application that synthesizes HDL designs to create Xilinx specific netlist files called NGC files. The NGC file is a netlist that contains both logical design data and constraints. The NGC file takes the place of both EDIF and NCF files. This Guide:

Describes XST support for Xilinx devices, HDL languages, and design constraints.

Explains how to use various design optimization and coding techniques when creating designs for use with XST.

Whats New in Release 9.1iFollowing are the major changes to XST for Release 9.1i.

Macro InferenceImprovements in Macro Inference in Release 9.1i include:

Improved DSP Specific Design and General Arithmetic Support

Improved Memory Inference Support

Improved DSP Specific Design and General Arithmetic SupportImprovements in DSP specific design and general arithmetic support in Release 9.1i include:

Support inference of the MDSP block. All DSP based macros supported on Virtex-4 and Virtex-5 architectures are now supported on MDSP as well. This includes:

All enhancements for the Virtex-4 and Virtex-5 families

Automatic MDSP resource managementXST User Guide www.xilinx.com 179.1i

Chapter 1: Introduction R Improved synthesis engine for filters

Sequential Complex Multipliers support. For more information, see Multipliers in Chapter 2.

XST can now cascade DSP blocks on input A.

Improved accumulator implementation with constant.

Improved accumulator implementation on DSP blocks when synchronous set is used, or data input is registered.

Improved absorption of control registers such as Opmode by DSP block

Improved Adders processing on DSP blocks (when adder is not a part of a filter).

Adders are taken into account by automatic DSP resource management mechanism. For more information, see Adders, Subtractors, and Adders/Subtractors in Chapter 2.

When placing an adder on a DSP block, XST uses fast connections to connect it to other DSP blocks. For more information, see Adders, Subtractors, and Adders/Subtractors in Chapter 2.

Note: You must still use the use_dsp48=yes constraint to place an adder on a DSP block. Improved pipelining of multipliers and distributed RAMs

XST infers subtractors with borrow in. For more information, see Adders, Subtractors, and Adders/Subtractors in Chapter 2.

Improved Memory Inference SupportImprovements in Memory inference support in Release 9.1i include:

Improved overall RAM inference flow. The decision on implementation resources (BRAM or distributed resources) is done entirely at the Advanced HDL Synthesis step. For more information, see RAMs and ROMs in Chapter 2.

Automatic BRAM resource management

Automatic packing of two single-port BRAMs in a single BRAM primitive. For more information, see Automatic BRAM Packing in Chapter 5.

Inference of BRAMs with byte write enable

Inference of simple dual-port BRAM mode for Virtex-5

Inference of dual-port BROMs

Adjusted RAM size limits for automatic choice between BRAM and Distributed implementation.

Design ConstraintsThe following new design constraints were introduced in Release 9.1i:

The Power Reduction constraint (POWER) reduces power consumption in the synthesized design. For more information, see Power Reduction in Chapter 5.

The Asynchronous to Synchronous (ASYNC_TO_SYNC) constraint automatically replaces Asynchronous Set/Reset signals with Synchronous signals throughout the entire design. This allows absorption of registers by DSP48 and BRAMs, thereby improving quality of results. For more information, see Asynchronous to Synchronous in Chapter 5.

Caution! Replacing Asynchronous Set/Reset signals by Synchronous signals makes the generated NGC netlist NOT equivalent to the initial RTL description. You must ensure that the 18 www.xilinx.com XST User Guide9.1i

Setting XST OptionsRsynthesized design satisfies the initial specification. For more information, see Asynchronous to Synchronous in Chapter 5.

The BRAM Utilization Ratio constraint (BRAM_UTILIZATION_RATIO) specifies the number of available BRAM blocks for synthesis. This constraint is supported only via the command line switch or the XST synthesis properties. For more information, see BRAM Utilization Ratio in Chapter 5.

Automatic BRAM Packing constraint (AUTO_BRAM_PACKING) packs two small BRAMs in a single BRAM primitive as dual-port BRAM. For more information, see Automatic BRAM Packing in Chapter 5.

The GENERICS constraint redefinse generics (VHDL) or parameters (Verilog) values defined in the top-level design block. This allows you to easily modify the design configuration without any HDL source modifications. For more information, see Generics in Chapter 5.

The Verilog Macros (DEFINE) constraint defines (or redefines) Verilog macros. This allows you to easily modify the design configuration without any HDL source modifications. For more information, see Verilog Macros (DEFINE) in Chapter 5.

The following existing design constraints were modified in Release 9.1i:

The Read_Cores synthesis option is supported as a constraint through HDL attributes or XCF file and can be applied on block be block basis. For more information, see Read Cores in Chapter 5.

The schematics for the SLICE_UTILIZATION_RATIO and SLICE_UTILIZATION_RATIO_MAXMARGIN constraints have been modified for the Virtex-5 family. These two constraints are interpreted as LUT-FF utilization ratio and LUT-FF utilization ratio delta. For more information, see Slice Utilization Ratio in Chapter 5.

Slice/LUT-FF pairs resource management can be disabled by specifying a value of -1 for the SLICE_UTILIZATION_RATIO constraint. For more information, see Slice Utilization Ratio in Chapter 5.

Log FileThe Log File now includes an Area report on a partition by partition basis for incremental flow with partitions.

Naming ConventionsThe way XST composes names for internal signals has been modified to improve signal name predictability. This change relates to combinatorial signals only, and not to names of sequential elements. For more information, see Chapter 11, XST Naming Conventions.

Setting XST OptionsBefore synthesizing your design, you can set a variety of options for XST. For further information on setting XST options, see:

ISE Help

Chapter 5, Design Constraints

Chapter 10, Command Line ModeXST User Guide www.xilinx.com 199.1i

Chapter 1: Introduction RDesigns are usually made up of combinatorial logic and macros (for example, flip-flops, adders, subtractors, counters, FSMs, and RAMs). The macros greatly improve performance of the synthesized designs. Therefore, it is important to use some coding techniques to model the macros so that they are optimally processed by XST.

During its run, XST first tries to recognize (infer) as many macros as possible. Then all of these macros are passed to the Low Level Optimization step, either preserved as separate blocks or merged with surrounded logic in order to get better optimization results. This filtering depends on the type and size of a macro (for example, by default, 2-to-1 multiplexers are not preserved by the optimization engine). You have full control of the processing of inferred macros through synthesis constraints.

For more information, see Chapter 5, Design Constraints.

XST LOG FilesXST LOG files contain the following detailed information about the macro processing:

The set of macros and associated signals inferred by XST from the VHDL or Verilog source on a block by block basis.

Macro inference is done in two steps:

HDL Synthesis

XST recognizes as many simple macro blocks as possible, such as adders, subtractors, and registers.

Advanced HDL Synthesis

XST does additional macro processing by improving the macros (for example, pipelining of multipliers) recognized at the HDL synthesis step, or by creating the new, more complex ones, such as dynamic shift registers. The Macro Recognition report at the Advanced HDL Synthesis step is formatted the same as the corresponding report at the HDL Synthesis step.

XST gives overall statistics of recognized macros twice:

After the HDL Synthesis step

After the Advanced HDL Synthesis step

XST no longer lists statistics of preserved macros in the final report.

Sample Log File OneThe following log sample displays the set of recognized macros on a block by block basis, as well as the overall macro statistics after this step.

===================================================

* HDL Synthesis *===================================================

...

Synthesizing Unit .Related source file is "decode.vhd".Found 16x10-bit ROM for signal .Summary:

inferred 1 ROM(s).Unit synthesized.20 www.xilinx.com XST User Guide9.1i

XST LOG FilesRSynthesizing Unit .Related source file is "statmach.vhd".Found finite state machine for signal .------------------------------------------------------

| States | 6 || Transitions | 11 || Inputs | 1 || Outputs | 2 || Clock | CLK (rising_edge) || Reset | RESET (positive) || Reset type | asynchronous || Reset State | clear || Power Up State | clear || Encoding | automatic || Implementation | LUT |------------------------------------------------------

Summary:inferred 1 Finite State Machine(s).

Unit synthesized....

==============================================================

HDL Synthesis Report

Macro Statistics# ROMs : 316x10-bit ROM : 116x7-bit ROM : 2# Counters : 24-bit up counter : 2

==============================================================

...

Sample Log File TwoThe following log sample displays the additional macro processing done during the Advanced HDL Synthesis step and the overall macro statistics after this step.

===================================================

* Advanced HDL Synthesis *===================================================

Analyzing FSM for best encoding.Optimizing FSM on signal with gray encoding.----------------------

State | Encoding----------------------

clear | 000zero | 001start | 011counting | 010stop | 110stopped | 111----------------------

============================================================XST User Guide www.xilinx.com 219.1i

Chapter 1: Introduction RAdvanced HDL Synthesis Report

Macro Statistics# FSMs : 1# ROMs : 316x10-bit ROM : 116x7-bit ROM : 2# Counters : 24-bit up counter : 2# Registers : 3Flip-Flops/Latches : 3

============================================================

...

Signed/Unsigned SupportWhen using Verilog or VHDL in XST, some macros, such as adders or counters, can be implemented for signed and unsigned values.

To enable support for signed and unsigned values in Verilog, enable Verilog-2001 as follows:

In Project Navigator, select Verilog 2001 as instructed in the Synthesis Options topic of ISE Help, or

Set the verilog2001 command line option to yes.

For VHDL, depending on the operation and type of the operands, you must include additional packages in your code. For example, in order to create an unsigned adder, you can use the following arithmetic packages and types that operate on unsigned values.

To create a signed adder you can use arithmetic packages and types that operate on signed values.

For more information, see the IEEE VHDL Manual for details on available types.

Table 1-1: Unsigned AdderPACKAGE TYPE

numeric_std unsigned

std_logic_arith unsigned

std_logic_unsigned std_logic_vector

Table 1-2: Signed AdderPACKAGE TYPE

numeric_std signed

std_logic_arith signed

std_logic_signed std_logic_vector22 www.xilinx.com XST User Guide9.1i

RChapter 2

HDL Coding Techniques

This chapter gives VHDL and Verilog coding examples for various digital logic circuits, such as Registers, Latches, Tristates, RAMs, Counters, Accumulators, Multiplexers, Decoders, and Arithmetic Operators. It also provides coding techniques for State Machines and Black Boxes.

This chapter contains the following sections:

Registers

Latches

Tristates

Counters

Accumulators

Shift Registers

Dynamic Shift Registers

Multiplexers

Decoders

Priority Encoders

Logical Shifters

Arithmetic Operators

RAMs and ROMs

Finite State Machines (FSMs)

Black Boxes

For each macro, both VHDL and Verilog examples are given. There is also a list of constraints you can use to control the macro processing in XST.

For more information, see Chapter 3, FPGA Optimization, and Chapter 4, CPLD Optimization.

For information on accessing the synthesis templates from Project Navigator, see the ISE Help.XST User Guide www.xilinx.com 239.1i

Chapter 2: HDL Coding Techniques RRegistersThis section discusses Registers.

About RegistersXST recognizes flip-flops with the following control signals:

Asynchronous Set/Reset

Synchronous Set/Reset

Clock Enable

For more information, see Specifying INITs and RLOCs in Chapter 3.

Registers Log FileThe XST log file reports the type and size of recognized flip-flops during the Macro Recognition step.

...

===============================================================

* HDL Synthesis *===============================================================

Synthesizing Unit .Related source file is "registers_5.vhd".Found 4-bit register for signal .Summary:

inferred 4 D-type flip-flop(s).Unit synthesized.

===============================================================


Macro Statistics# Registers : 14-bit register : 1

===============================================================

===============================================================

* Advanced HDL Synthesis *===============================================================

===============================================================

Advance HDL Synthesis Report

Macro Statistics# Registers : 4Flip-Flops/Latches : 4

===============================================================

...

With the introduction of new families such as Virtex-4, XST may optimize different slices of the same register in different ways. For example, XST may push a part of a register into a DSP48 block and another part may be implemented on slices or even become a part of a shift register. XST now reports the total number of FF bits in the design in the HDL Synthesis Report after the Advanced HDL Synthesis step. 24 www.xilinx.com XST User Guide9.1i

RegistersRRegisters Related Constraints IOB

REGISTER_DUPLICATION

EQUIVALENT_REGISTER_REMOVAL

REGISTER_BALANCING

Registers Coding ExamplesThese coding examples are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip.

Flip-Flop With Positive-Edge ClockThis section discusses Flip-Flop With Positive-Edge Clock.

VHDL Coding Example for Flip-Flop With Positive-Edge Clock--

-- Flip-Flop with Positive-Edge Clock--

library ieee;use ieee.std_logic_1164.all;

entity registers_1 is port(C, D : in std_logic; Q : out std_logic);end registers_1;

architecture archi of registers_1 isbegin

process (C) begin if (C'event and C='1') then

Figure 2-1: Flip-Flop With Positive-Edge Clock

Table 2-1: Pin Descriptions for Flip-Flop With Positive-Edge Clock IO Pins Description

D Data Input

C Positive-Edge Clock

Q Data Output

Q

X3715

D FD

CXST User Guide www.xilinx.com 259.1i

Chapter 2: HDL Coding Techniques R Q

RegistersRVHDL Coding Example for Flip-Flop With Negative-Edge Clock And Asynchronous Reset

--

-- Flip-Flop with Negative-Edge Clock and Asynchronous Reset--


entity registers_2 is port(C, D, CLR : in std_logic; Q : out std_logic);end registers_2;


process (C, CLR) begin if (CLR = '1')then Q

Chapter 2: HDL Coding Techniques RFlip-Flop With Positive-Edge Clock And Synchronous SetThis section discusses Flip-Flop With Positive-Edge Clock And Synchronous Set.

VHDL Coding Example for Flip-Flop With Positive-Edge Clock And Synchronous Set

--

-- Flip-Flop with Positive-Edge Clock and Synchronous Set--


entity registers_3 is port(C, D, S : in std_logic; Q : out std_logic);end registers_3;


process (C) begin if (C'event and C='1') then if (S='1') then Q

RegistersRVerilog Coding Example for Flip-Flop With Positive-Edge Clock And Synchronous Set

//// Flip-Flop with Positive-Edge Clock and Synchronous Set//

module v_registers_3 (C, D, S, Q); input C, D, S; output Q; reg Q;

always @(posedge C) begin if (S) Q

Chapter 2: HDL Coding Techniques Rentity registers_4 is port(C, D, CE : in std_logic; Q : out std_logic);end registers_4;


process (C) begin if (C'event and C='1') then if (CE='1') then Q

RegistersRVHDL Coding Example for 4-Bit Register With Positive-Edge Clock, Asynchronous Set, And Clock Enable

--

-- 4-bit Register with Positive-Edge Clock, Asynchronous Set and Clock Enable--


entity registers_5 is port(C, CE, PRE : in std_logic; D : in std_logic_vector (3 downto 0); Q : out std_logic_vector (3 downto 0));end registers_5;


process (C, PRE) begin if (PRE='1') then Q

Chapter 2: HDL Coding Techniques R output [3:0] Q; reg [3:0] Q;

always @(posedge C or posedge PRE) begin if (PRE) Q

LatchesRLatches Coding ExamplesThese coding examples are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip.

Latch With Positive GateThis section discusses Latch With Positive Gate.

VHDL Coding Example for Latch With Positive Gate--

-- Latch with Positive Gate--


entity latches_1 is port(G, D : in std_logic; Q : out std_logic);end latches_1;

architecture archi of latches_1 isbegin process (G, D) begin if (G='1') then Q

Chapter 2: HDL Coding Techniques RVerilog Coding Example for Latch With Positive Gate//// Latch with Positive Gate//

module v_latches_1 (G, D, Q); input G, D; output Q; reg Q;

always @(G or D) begin if (G) Q = D; endendmodule

Latch With Positive Gate And Asynchronous ResetThis section discusses Latch With Positive Gate And Asynchronous Reset.

VHDL Coding Example for Latch With Positive Gate And Asynchronous Reset--

-- Latch with Positive Gate and Asynchronous Reset--


entity latches_2 is port(G, D, CLR : in std_logic; Q : out std_logic);end latches_2;

Figure 2-7: Latch With Positive Gate And Asynchronous Reset

Table 2-7: Pin Descriptions for Latch With Positive Gate And Asynchronous ResetIO Pins Description

D Data Input

G Positive Gate

CLR Asynchronous Reset (Active High)

Q Data Output

Q

X4070

D LDC

G

CLR34 www.xilinx.com XST User Guide9.1i

LatchesRarchitecture archi of latches_2 isbegin process (CLR, D, G) begin if (CLR='1') then Q

Chapter 2: HDL Coding Techniques RVHDL Coding Example for 4-Bit Latch With Inverted Gate And Asynchronous Set--

-- 4-bit Latch with Inverted Gate and Asynchronous Set--


entity latches_3 is port(D : in std_logic_vector(3 downto 0); G, PRE : in std_logic; Q : out std_logic_vector(3 downto 0));end latches_3;

architecture archi of latches_3 isbegin process (PRE, G, D) begin if (PRE='1') then Q

TristatesRTristatesThis section discusses Tristates.

About TristatesTristate elements can be described using the following:

Combinatorial process (VHDL) and always block (Verilog)

Concurrent assignment

In the following examples, comparing to 0 instead of 1 infers a BUFT primitive instead of a BUFE macro. The BUFE macro has an inverter on the E pin.

Tristates Log FileThe XST log reports the type and size of recognized tristates during the Macro Recognition step.

...

Synthesizing Unit . Related source file is tristates_1.vhd.Found 1-bit tristate buffer for signal .Summary:

inferred 1 Tristate(s).Unit synthesized.

=============================


Macro Statistics# Tristates : 1

1-bit tristate buffer : 1=============================

...

Tristates Related Constraints TRISTATE2LOGIC

Tristates Coding ExamplesThese coding examples are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip. XST User Guide www.xilinx.com 379.1i

Chapter 2: HDL Coding Techniques RTristate Description Using Combinatorial Process and Always BlockThis section discusses Tristate Description Using Combinatorial Process and Always Block.

VHDL Coding Example for Tristate Description Using Combinatorial Process--

-- Tristate Description Using Combinatorial Process--


entity three_st_1 is port(T : in std_logic; I : in std_logic; O : out std_logic);end three_st_1;

architecture archi of three_st_1 isbegin

process (I, T) begin if (T='0') then O

TristatesRVerilog Coding Example for Tristate Description Using Combinatorial Always Block//// Tristate Description Using Combinatorial Always Block//

module v_three_st_1 (T, I, O); input T, I; output O; reg O;

always @(T or I) begin if (~T) O = I; else O = 1'bZ; end

endmodule

Tristate Description Using Concurrent AssignmentThis section discusses Tristate Description Using Concurrent Assignment.

VHDL Coding Example for Tristate Description Using Concurrent Assignment--

-- Tristate Description Using Concurrent Assignment--


entity three_st_2 is port(T : in std_logic; I : in std_logic;

Figure 2-10: Tristate Description Using Concurrent Assignment

Table 2-10: Pin Descriptions for Tristate Description Using Concurrent AssignmentIO Pins Description

I Data Input

T Output Enable (active Low)

O Data Output

X10525

T

I OXST User Guide www.xilinx.com 399.1i

Chapter 2: HDL Coding Techniques R O : out std_logic);end three_st_2;

architecture archi of three_st_2 isbegin O

CountersRCounters Log FileThe XST log file reports the type and size of recognized counters during the Macro Recognition step.

...

Synthesizing Unit . Related source file is counters_1.vhd. Found 4-bit up counter for signal . Summary:

inferred 1 Counter(s). Unit synthesized.

==============================


Macro Statistics # Counters : 1

4-bit up counter : 1==============================

...

During synthesis, XST decomposes Counters on Adders and Registers if they do not contain synchronous load signals. This is done to create additional opportunities for timing optimization. Because of this, counters reported during the Macro Recognition step and in the overall statistics of recognized macros may not appear in the final report. Adders/registers are reported instead.

Counters Related Constraints Use DSP48

DSP Utilization Ratio

Keep

Counters Coding ExamplesThese coding examples are accurate as of the date of publication. Download updates from ftp://ftp.xilinx.com/pub/documentation/misc/examples_v9.zip.

4-Bit Unsigned Up Counter With Asynchronous ResetThis section discusses 4-Bit Unsigned Up Counter With Asynchronous Reset.

Figure 2-11: 4-Bit Unsigned Up Counter With Asynchronous Reset

X10526

COUNT

C

CLR

Q4XST User Guide www.xilinx.com 419.1i

Chapter 2: HDL Coding Techniques RVHDL Coding Example for 4-Bit Unsigned Up Counter With Asynchronous Reset--

-- 4-bit unsigned up counter with an asynchronous reset.--

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity counters_1 is port(C, CLR : in std_logic; Q : out std_logic_vector(3 downto 0));end counters_1;

architecture archi of counters_1 is signal tmp: std_logic_vector(3 downto 0);begin process (C, CLR) begin if (CLR='1') then tmp

CountersR assign Q = tmp;endmodule

4-Bit Unsigned Down Counter With Synchronous SetThis section discusses 4-Bit Unsigned Down Counter With Synchronous Set.

VHDL Coding Example for 4-Bit Unsigned Down Counter With Synchronous Set --

-- 4-bit unsigned down counter with a synchronous set.--

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;

entity counters_2 is port(C, S : in std_logic; Q : out std_logic_vector(3 downto 0));end counters_2;

architecture archi of counters_2 is signal tmp: std_logic_vector(3 downto 0);begin process (C) begin if (C'event and C='1') then if (S='1') then tmp

Chapter 2: HDL Coding Techniques R end if; end if; end process;

Q

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