3
RESUME YUVARAJA.R [email protected] (91) 9790410872. Contact Address R.Yuvaraja. S/O, V.Rajendran. 55, Kuttai meleai street, Namakkal-637001. CAREER PROFILE Objective To work in the most challenging position with an organization that provides ample opportunities to learn and to contribute. I am flexible & willing to work on any technology. Educational Qualification Bachelor of Engineering (B.E) in Electronics and Communication Engineering (2005-2009) from Paavai Engineering college, Tamil Nadu, India with an aggregate of 75.0%. TECHNICAL SKILLS Programming skills C, Vhdl, Verilog. Tools/Packages MS Office. Operating Systems Windows 98, XP/2000 and Ubuntu. AREA OF INTEREST 1. Microprocessor (8085). 2. Digital Electronics. ACADEMICS Exam Institute Board Year of Study Percentag e

Yuvaraja

Embed Size (px)

DESCRIPTION

My Resume

Citation preview

Page 1: Yuvaraja

RESUME

YUVARAJA.R

[email protected] (91) 9790410872.

Contact AddressR.Yuvaraja. S/O, V.Rajendran.55, Kuttai meleai street,Namakkal-637001.

CAREER PROFILE

Objective

To work in the most challenging position with an organization that provides ample opportunities to learn and to contribute. I am flexible & willing to work on any technology.

Educational Qualification

Bachelor of Engineering (B.E) in Electronics and Communication Engineering (2005-2009) from Paavai Engineering college, Tamil Nadu, India with an aggregate of 75.0%.

TECHNICAL SKILLS

Programming skills C, Vhdl, Verilog.

Tools/Packages MS Office.

Operating Systems Windows 98, XP/2000 and Ubuntu.

AREA OF INTEREST

1. Microprocessor (8085).

2. Digital Electronics.

ACADEMICS

Exam Institute BoardYear of Study

Percentage

B.E (ECE)Paavai Engg

College,NamakkalAnna

University2005-2009 75.0 %

HSCAnna-Nehru

M.H.S.SState Board 2003-2005 77.58 %

SSCJack and Jill

M.H.S.SMatriculation 2001-2003 68.65 %

Page 2: Yuvaraja

RESUME

ACADEMIC PROJECT

1 Project Name

Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores Using VHDL.

Team Size 4

Description of the Project

It has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-performance floating-point arithmetic. To achieve high clock rates, floating-point cores for FPGAs must be deeply pipelined.

Duration From: JAN/09 To: FEB/09

Language used VHDL.

EXTRA CURRICULAR ACTIVITIES

1. Inplant Training in BSNL-NAMAKKAL.

2. Industrial visit in TEKL [Transformers &Electrical Limited –Kerala].

PERSONAL DETAILS

Date of Birth 22 Nov 1988.

Sex MALE.

Nationality INDIAN.

Marital Status SINGLE.

Languages Known English, Tamil, Telgu.

Permanent Address 55, Kuttai meleai Street, Namakkal.

DECLARATIONI hereby declare that the above information is true and correct to the best of my knowledge.

Place : Namakkal. Date :04.05.2010 Yours Sincerely,

R. YUVARAJA