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VHDL
Synthesis & Simulation
(Basic Language Items)
Agenda OverviewOverview Entity Architecture Library & Use Package Configuration
Basic Language Framework
library ieee;use ieee.std_logic_1164.all;---------------------------------------------entity XYZ is port ( A, B, C : in std_logic; -- Comments F : out std_logic );end XYZ;---------------------------------------------architecture XYZ_arch of XYZ isbegin F <= (A and B) or (B and C) or (C and A); end XYZ_arch;
Include…Include…
EntityEntity
ArchitectureArchitecture
Agenda Overview EntityEntity
KeywordsKeywords Port Generic
Architecture Library & Use Package Configuration
Entitylibrary ieee;use ieee.std_logic_1164.all;---------------------------------------------
entityentity XYZ isis port ( A, B, C : in std_logic; F : out std_logic );
endend XYZ;---------------------------------------------architecture XYZ_arch of XYZ isbegin F <= (A and B) or (B and C) or (C and A);end XYZ_arch;
Include…Include…
EntityEntity
ArchitectureArchitecture
Entity Definition
entityentity entity_name isis [Generics;] [Ports;] [Other Declarative Parts;] [Statements;]
endend [ entity ] [ entity_name ] ;
Entity Examples (ROM)
entityentity ROM is is port ( D0 : out bit; D1 : out bit; D2 : out bit; D3 : out bit; D4, D5, D6, D7 : out bit; A : in bit_vector(7 down to 0) );
endend ROM;
ROM
A0A1A2A3A4A5A6A7
D0D1D2D3D4D5D6D7
Entity Examples (Adder)
entityentity Full_Adder isis port (X, Y, Cin: in Bit; Cout, Sum: out Bit) ;
endend entityentity Full_Adder ; ;
X
Y
Cin
Sum
Cout
Entity Examples (n-input AND)
entityentity ANDN isis
generic (wid : integer := 2); port ( X : in bit_vector(wid-1 downto 0); F : out bit );
endend;
…
X(0) X(1) X(2)
X(wid-1)
F
Entity Example (Empty Entity)
entityentity Test_Bench isis
endend entityentity Test_Bench ;;
Test_Bench
Signal Generator
Test Target
Agenda Overview EntityEntity
Keywords PortPort Generic
Architecture Library & Use Package Configuration
Entity Definition (Ports)
entityentity entity_name isis Generics;
Ports;Ports; Other Declarative Parts; Statements;endend [ entity ] [ entity_name ] ;
Port Example (ANDN)
entity ANDN is
generic (wid : integer := 2);
portport (
X : in bit_vector(wid-1 downto 0);
F : out bit
);
end;
…
X(0) X(1) X(2)
X(wid-1)
F
Port Examples (ROM)entity ROM is
portport ( D0 : out bit;
D1 : out bit; D2 : out bit; D3 : out bit; D4, D5, D6, D7 : out bit; A : in bit_vector(7 down to 0) );end ROM;
ROM
A0A1A2A3A4A5A6A7
D0D1D2D3D4D5D6D7
Port Examples (Adder)entityentity Full_Adder isis
portport (X, Y, Cin: in Bit; Cout, Sum: out Bit) ;
end entity Full_Adder ;
X
Y
Cin
Sum
Cout
Port Examples (n-input AND)
entity ANDN is
generic (wid : integer := 2);
portport (
X : in bit_vector(wid-1 downto 0);
F : out bit
);
end;
…
X(0) X(1) X(2)
X(wid-1)
F
Port DefinitionPortPort ((Port_Name[, Port_Name] : Dir Type[:=Default_Val];;Port_Name[, Port_Name] : Dir Type[:=Default_Val];; .
.
.Port_Name[, Port_Name] : Dir Type[:=Default_Val];;
););
Each Parts of Port portport
((
A0, A1 : in std_logic;
A2 : in std_logic := ‘1’;
F0 : buffer std_logic;
F1 : out std_logic;
F2 : inout std_logic
););
Port Name Dir Type Default Value
Type of “Dir” In Out Inout Buffer Linkage
Signal Direction
D Q
D Q
A0 (IN)
A1 (IN)
A2
(IN)
F0 (BUFFER)
F1 (OUT)
F2 (INOUT)
Other ICOther IC
Dir Example
D Q
D Q
A0 (IN)
A1 (IN)
A2
(IN)
F0 (BUFFER)
F1 (OUT)
F2 (INOUT)
portport
((
A0, A1 : in std_logic;;
A2 : in std_logic := ‘1’;;
F0 : buffer std_logic;;
F1 : out std_logic;;
F2 : inout std_logic
););
Use of Dirlibrary ieee;
use ieee.std_logic_1164.all;
------------------------------
entity ABC is
port
(
A0, A1, A2A0, A1, A2 : inin std_logic;
F0F0 : bufferbuffer std_logic;
F1F1 : outout std_logic;
F2F2 : inoutinout std_logic
);
end ABC;
---------------------------------architecture ABC_arch of ABC isbegin process(A0A0) begin if rising_edge(A0A0) then F0F0 <= not F0F0; F1F1 <= F2F2; end if; end process; F2F2 <= A1A1 when A2A2 = '1' ELSE 'Z';end ABC_arch;
Type portport
((
A0, A1 : in std_logic;
A2 : in std_logic := ‘1’;
F0 : buffer std_logic;
F1 : out std_logic;
F2 : inout std_logic
););
Port Name Dir Type Default Value
Typical Port Type Bit Bit_vector Std_logic Std_logic_vector
Bit ‘1’ ‘0’
Bit_vector
port
( X : in bit_vector(3 downto 0);
F : out bit );
X0X1X2X3
F
Port ( X0 : in bit; X1 : in bit; X2 : in bit; X3 : in bit; F : out bit );
Port (
X0, X1, X2, X3 : in bit; F : out bit );
Std_logic 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care
??
Resolution Function Of Std_logicU X 0 1 Z W L H -
U U U U U U U U U U
X U X X X X X X X X
0 U X 0 X 0 0 0 0 X
1 U X X 1 1 1 1 1 X
Z U X 0 1 Z W L H X
W U X 0 1 W W W W X
L U X 0 1 L W L W X
H U X 0 1 H W W H X
- U X X X X X X X X
11
00
??
Std_logic_vector
port
( X : in std_logic_vector(3 downto 0);
F : out std_logic );
X0X1X2X3
F
Agenda Overview EntityEntity
Keywords Port GenericGeneric
Architecture Library & Use Package Configuration
Entity Definition (Generics)
entityentity entity_name isis
Generics;Generics; Ports; Other Declarative Parts; Statements;endend [ entity ] [ entity_name ] ;
An AND Gate With Unknown Inputs
entity ANDN is
genericgeneric (widwid : integer := 2);
port (
X : in bit_vector(widwid-1 downto 0); F : out bit );end ANDN;
…
X(0) X(1) X(2)
X(wid-1)
F
Generic Definition
genericgeneric (
Name [, Name] : DataType [:= DefaultValue];; Name [, Name] : DataType [:= DefaultValue];;
...... Name [, Name] : DataType [:= DefaultValue]
);
Generic Example (1)entity abcd is
genericgeneric (
p_a : integer : = 2; p_b : integer : = 7 ); port ( A : out bit_vector(0 to p_a - 1); F : in bit );end;
Use of the Generic (ANDN.vhd)
library ieee;use ieee.std_logic_1164.all;---------------------------------entityentity ANDNANDN is genericgeneric (widwid : integer := 2); port ( X : in bit_vector(widwid-1 downto 0); F : out bit );endend ANDNANDN;---------------------------------architecture ANDN_arch of ANDNANDN isbegin process(X) variable tmp : bit; begin tmp := '1'; for i in widwid-1 downto 0 loop tmp := tmp and X(i); end loop; F <= tmp; end process;end ANDN_arch;
…
X(0) X(1) X(2)
X(wid-1)
F
Use of the Generic (My_package.vhd)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;---------------------------------package my_package is componentcomponent ANDNANDN is generic (wid : integer := 2); port ( X : in bit_vector(wid-1 downto 0); F : out bit );
endend component;
end my_package;
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.my_package.all;
---------------------------------
entity SEE is
port
( A : in bit_vector(3 downto 0);
B : in bit_vector(1 downto 0);
F1, F2 : out bit );
end SEE;
---------------------------------
architecture SEE_arch of SEE is
begin
U1: ANDNANDN generic map(4)generic map(4) port map (A, F1);
U2: ANDNANDN
port map (B, F2);
end SEE_arch;
Use of the Generic (see.vhd)
U1A(0)A(1)A(2)A(3)
F1
U2B(1)
B(3)F2
Agenda Overview Entity ArchitectureArchitecture
KeywordsKeywords Block Process Subprogram
Function Procedure
Library & Use Package Configuration
Architecturelibrary ieee;use ieee.std_logic_1164.all;---------------------------------------------entity XYZ is port ( A, B, C : in std_logic; F : out std_logic );end XYZ;---------------------------------------------
architecturearchitecture XYZ_arch ofof XYZ isisbeginbegin F <= (A and B) or (B and C) or (C and A);
endend XYZ_arch;
Include…Include…
EntityEntity
ArchitectureArchitecture
Architecture Definition
architecturearchitecture arch_name ofof entity_name isis architecture_declarative_part
beginbegin architecture_statement_part
endend [ architecture ] [ arch_name ] ;
Architecture Example (ABC.vhd)
library ieee;
use ieee.std_logic_1164.all;
------------------------------
entity ABC is
port(
A0,A1,A2 : in std_logic;
F0 : buffer std_logic;
F1 : out std_logic;
F2 : inout std_logic );
end ABC;
---------------------------------
architecturearchitecture ABC_arch ofof ABC isisbeginbegin process(A0) begin if rising_edge(A0) then F0 <= not F0; F1 <= F2; end if; end process; F2 <= A1 when A2 = '1' ELSE 'Z';
endend ABC_arch;
Architecture Example (ANDN.vhd)
library ieee;use ieee.std_logic_1164.all;---------------------------------entity ANDN is generic (wid : integer := 2); port( X : in bit_vector(wid-1 downto 0); F : out bit );end ANDN;---------------------------------
architecturearchitecture ANDN_archANDN_arch ofof ANDN isisbeginbegin process(X) variable tmp : bit; begin tmp := '1'; for i in wid-1 downto 0 loop tmp := tmp and X(i); end loop; F <= tmp; end process;
endend ANDN_archANDN_arch;
…
X(0) X(1) X(2)
X(wid-1)
F
Use of the Generic (see.vhd)
library ieee;use ieee.std_logic_1164.all;library work;use work.my_package.all;---------------------------------entity SEE is port ( A : in bit_vector(3 downto 0); B : in bit_vector(1 downto 0); F1, F2 : out bit );end SEE;---------------------------------
architecturearchitecture SEE_arch ofof SEE isisbeginbegin U1: ANDN generic map(4) port map (A, F1); U2: ANDN port map (B, F2);
endend SEE_arch;
U1A(0)A(1)A(2)A(3)
F1
U2B(1)
B(3)F2
Agenda Overview Entity ArchitectureArchitecture
Keywords BlockBlock Process Subprogram
Function Procedure
Library & Use Package Configuration
Inside Architecture How to maintain large architecture? How to modulate the architecture code? Separate the architecture in to several parts How to separate the architecture? VHDL language that can separate an
architecture Block Process
Example of Block (BLKBLK.vhd)
library ieee;
use ieee.std_logic_1164.all;
---------------------------------
entity blkblk is
port(X: in std_logic;
Y: out std_logic);
end blkblk;
architecturearchitecture blkblk_arch ofof blkblk isis signal A, B: std_logic; beginbegin
u1: blocku1: block signal C, D: std_logic;
beginbegin A <= C; B <= D; C <= X; D <= X;
end block u1;end block u1;
u2: blocku2: block signal C, E: std_logic;
beginbegin C <= A; E <= B;
u3: blocku3: block signal E, F, G: std_logic;
beginbegin E <= A; F <= E; G <= u2.E;
end block u3;end block u3; end block u2;end block u2; Y <= X and (A or B);endend blkblk_arch;
Definition of Block
BlockLabel: blockblock [( GuardExpression)] [is] Declarations;
beginbegin ConcurrentStatements;
end blockend block [BlockLabel];
Example of Block (BLKBLK.vhd)
library ieee;
use ieee.std_logic_1164.all;
---------------------------------
entity blkblk is
port(X: in std_logic;
Y: out std_logic);
end blkblk;
architecturearchitecture blkblk_arch ofof blkblk isis signal A, B: std_logic; beginbegin
u1: blocku1: block signal C, D: std_logic;
beginbegin A <= C; B <= D; C <= X; D <= X;
end block u1;end block u1;
u2: blocku2: block signal C, E: std_logic;
beginbegin C <= A; E <= B;
u3: blocku3: block signal E, F, G: std_logic;
beginbegin E <= A; F <= E; G <= u2.E;
end block u3;end block u3; end block u2;end block u2; Y <= X and (A or B);endend blkblk_arch;
Example of Block (Test_16.vhd)
begin begin Blck_Test_1: blockblock (clock = '1' and Clock'EVENT)
beginbegin Destination_1 <= guarded Source;Destination_2 <= Source;
end blockend block Blck_Test_1;
Blck_Test_2: blockblock (Clock = '1' and not(Clock'STABLE))
begin begin Destination_3 <=guarded Source;Destination_4 <=Source;
end blockend block Blck_Test_2;
Monitor: processprocessvariable Source_Var : NATURAL;variable Dest_1_Var, Dest_2_Var : NATURAL;variable Dest_3_Var, Dest_4_VAr : NATURAL
begin begin Source_Var := Source;Dest_1_Var := Destination_1; Dest_2_Var := Destination_2;Dest_3_Var := Destination_3; Dest_4_Var := Destination_4;wait on Destination_1,Destination_2, Destination_3,Destination_4;
end processend process Monitor;
Tick_Tock: processprocess beginbegin
wait for 10 ns;Clock <=not clock;
end processend process Tick_Tock; Source_Wave: Source <=1 after 8 ns, 2 after 15 ns, 3 after 16 ns, 4 after 17 ns, 5 after 18 ns,6 after 19 ns;
endend Behave_1;
entityentity Test_16 is isendend Test_16;
architecture architecture Behave_1 ofof Test_16 is is signal Source : NATURAL := 0; signal Destination_1 : NATURAL := 0; signal Destination_2 : NATURAL := 0; signal Destination_3 : NATURAL := 0; signal Destination_4 : NATURAL := 0; signal Clock : BIT := '0';
Guarded Signals In Block
BlockLabel: blockblock [( GuardExpression)][( GuardExpression)] [is] Declarations;
beginbegin ConcurrentStatements;
end blockend block [BlockLabel];
Guarded Signals Example (LT1.vhd)
library ieee;
use ieee.std_logic_1164.all;
entityentity LT1 isis
port
( D, CLK : in bit;
Q : out bit;
Free_in : in bit;
Free_out : out bit );
endend LT1;
architecturearchitecture LT1_arch of of LT1 isisbegin
U1: blockblock
beginbegin Q <= guarded D;
Free_out <= not Free_in;
end blockend block U1;
endend LT1_arch;
Q <= D;
Free_out <= not Free_in;
DCLK
Free_in
Q
Free_out
Guarded Signals Example (LT.vhd)
library ieee;
use ieee.std_logic_1164.all;
entityentity LT isis
port
( D, CLK : in bit;
Q : out bit;
Free_in : in bit;
Free_out : out bit );
endend LT;
architecturearchitecture LT_arch of of LT isisbegin
U1: blockblock (CLK = '1')(CLK = '1')
beginbegin Q <= guardedguarded D;
Free_out <= not Free_in;
end blockend block U1;
endend LT_arch;
Q <= guardedguarded D;
Free_out <= not Free_in;
LatchD
CLK
Free_in
Q
Free_out
Guarded Signals Example (Wave)
Agenda Overview Entity ArchitectureArchitecture
Keywords Block ProcessProcess Subprogram
Function Procedure
Library & Use Package Configuration
Process Definition
[process_label:] processprocess [(sensitivity_list)] [is]
process_declarative_part
beginbegin process_statement_part
end processend process [process_label];
Example of Process (Test_16.vhd)
begin begin Blck_Test_1: blockblock (clock = '1' and Clock'EVENT)
beginbegin Destination_1 <= guarded Source;Destination_2 <= Source;
end blockend block Blck_Test_1;
Blck_Test_2: blockblock (Clock = '1' and not(Clock'STABLE))
begin begin Destination_3 <=guarded Source;Destination_4 <=Source;
end blockend block Blck_Test_2;
Monitor: processprocessvariable Source_Var : NATURAL;variable Dest_1_Var, Dest_2_Var : NATURAL;variable Dest_3_Var, Dest_4_VAr : NATURAL
begin begin Source_Var := Source;Dest_1_Var := Destination_1; Dest_2_Var := Destination_2;Dest_3_Var := Destination_3; Dest_4_Var := Destination_4;wait on Destination_1,Destination_2, Destination_3,Destination_4;
end processend process Monitor;
Tick_Tock: processprocess beginbegin
wait for 10 ns;Clock <=not clock;
end processend process Tick_Tock; Source_Wave: Source <=1 after 8 ns, 2 after 15 ns, 3 after 16 ns, 4 after 17 ns, 5 after 18 ns,6 after 19 ns;
endend Behave_1;
entityentity Test_16 is isendend Test_16;
architecture architecture Behave_1 ofof Test_16 is is signal Source : NATURAL := 0; signal Destination_1 : NATURAL := 0; signal Destination_2 : NATURAL := 0; signal Destination_3 : NATURAL := 0; signal Destination_4 : NATURAL := 0; signal Clock : BIT := '0';
Example of Process (Test_16.vhd zoom)
Monitor: processprocessvariable Source_Var : NATURAL;
variable Dest_1_Var, Dest_2_Var : NATURAL;
variable Dest_3_Var, Dest_4_VAr : NATURAL
begin begin Source_Var := Source;
Dest_1_Var := Destination_1; Dest_2_Var := Destination_2;
Dest_3_Var := Destination_3; Dest_4_Var := Destination_4;
wait on Destination_1,Destination_2, Destination_3,Destination_4;
end processend process Monitor;
Tick_Tock: processprocess
beginbeginwait for 10 ns;
Clock <=not clock;
end processend process Tick_Tock;
Process Example With Sensitive Table (MY_DFF.vhd)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------
entity MY_DFF is
port
( D, CP : in std_logic;
Q : out std_logic );
end MY_DFF;
architecturearchitecture MY_DFF_arch ofof MY_DFF isisbeginbegin
process process (CP)(CP) beginbegin if rising_edge(CP)rising_edge(CP) then
Q <= D; end if;
end process;end process;endend MY_DFF_arch;
D Q CLK
Process Example With ‘Wait’ (MY_DFF.vhd)
architecturearchitecture MY_DFF_arch ofof MY_DFF isis
beginbegin
processprocess
beginbegin
wait until CP'event and CP ='1';wait until CP'event and CP ='1'; Q <= D;
end process;end process;
endend MY_DFF_arch;
D Q CLK
Process Example (Latch.vhd)
library ieee;
use ieee.std_logic_1164.all;
---------------------------------
entity LT is
port
( D, CLK : in bit;
Q : out bit );
end LT;
architecturearchitecture LT_arch ofof LT isisbeginbegin
process process (CLK, D)
beginbegin if CLK = '1' then Q <= D; end if;
end process;end process;endend LT_arch;
D Q CLK
DCLK
Q
Process (PROC2 Diagram)
脉冲生成器 PA
脉冲生成器 PB
to_b
to_a
X
Process Example (Proc2.vhd)
library ieee;use ieee.std_logic_1164.all;----------------------------entity PROC2 is port ( X: in std_logic);end PROC2;
architecturearchitecture PROC2_arch ofof PROC2 isis signal to_a, to_b: std_logic := '0';
beginbegin PA: process(X, to_a) begin if (X'event and X = '1') or (to_a'event and to_a = '1') then to_b <= '1' after 20ns, '0' after 30ns; end if; end process PA; PB: process(to_b) begin if (to_b'event and to_b = '1') then to_a <= '1' after 10ns, '0' after 20ns; end if; end process PB;
endend PROC2_arch;
PA: process(X, to_a) begin if (X'event and X = '1') or (to_a'event and to_a = '1') then to_b <= '1' after 20ns, '0' after 30ns; end if; end process PA;PB: process(to_b) begin if (to_b'event and to_b = '1') then to_a <= '1' after 10ns, '0' after 20ns; end if; end process PB;
脉冲生成器 PA
脉冲生成器 PB
to_b
to_a
X
Process Example (Proc2 Wave)
脉冲生成器 PA
脉冲生成器 PB
to_b
to_a
X
Agenda Overview Entity ArchitectureArchitecture
Keywords Block Process SubprogramSubprogram
FunctionFunction Procedure
Library & Use Package Configuration
Function Definition
functionfunction Name [(ParamList)] returnreturn Type;
functionfunction Name [(ParamList)] returnreturn Type isis DeclarativePart;
beginbegin StatementPart;
end functionend function Name;
Declaration
Body
Functions Example (My_Package.vhd)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------
packagepackage my_package isis
endend my_package;
functionfunction SUM2SUM2(S1, S2: in std_logic_vector)
returnreturn std_logic_vector;
packagepackage bodybody my_package isis
endend my_package;
functionfunction SUM2SUM2(S1, S2: in std_logic_vector)
returnreturn std_logic_vector isis variable tmp: std_logic_vector(S1'range);
beginbegin tmp := S1+S2;
return tmp;
endend SUM2SUM2;
Function Call Examplelibrary ieee;
use ieee.std_logic_1164.all;
library work;
use work.my_package.all;
---------------------------------
entity SUBPROC is
port ( X : in std_logic_vector(3 downto 0);
Y : in std_logic_vector(3 downto 0);
Z : out std_logic_vector(3 downto 0) );
end SUBPROC;
architecturearchitecture SUBPROC_arch ofof SUBPROC isis
beginbegin
Z <= SUM2(X, Y);SUM2(X, Y);endend SUBPROC_arch;
XY
Z
Agenda Overview Entity ArchitectureArchitecture
Keywords Block Process SubprogramSubprogram
Function ProcedureProcedure
Library & Use Package Configuration
Procedure Definition
procedureprocedure Name [(ParamList)]
procedureprocedure Name [(ParamList)] isis DeclarativePart;
beginbegin StatementPart;
end procedureend procedure Name;
Declaration
Body
Procedure Example (My_Pachage.vhd)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
---------------------------------
packagepackage my_package isis
end end my_package;
packagepackage bodybody my_package isis
endend my_package;
procedureprocedure NOT_PROC NOT_PROC (A : in std_logic
C : out std_logic);
procedure procedure NOT_PROC NOT_PROC (A: in std_logic;
B: out std_logic) isis
beginbegin B := not A;
endend NOT_PROC;NOT_PROC;
Procedure Call Examplelibrary ieee;
use ieee.std_logic_1164.all;
library work;
use work.my_package.all;
---------------------------------
entity SUBPROC is
port( M : in std_logic;
CLK : in std_logic;
K : out std_logic );
end SUBPROC;
architecturearchitecture SUBPROC_arch ofof SUBPROC isis
beginbegin
ProcessProcess (CLK)
variable tmp: std_logic;
beginbegin
if rising_edge(CLK) then
NOT_PROC(M, tmp);NOT_PROC(M, tmp); K <= tmp;
end if;
end process;end process;
endend SUBPROC_arch;
M
CLK
D Q
CLK
K
Agenda Overview Entity Architecture Library & UseLibrary & Use Package Configuration
Library & Use (Definition)
librarylibrary LibraryName, LibraryName, …;
useuse LibraryName.PackageName.ItemName;
useuse LibraryName.PackageName.all;
useuse LibraryName.ItemName;
useuse LibraryName.all;
……
Library & Use Library
Name of library, contain pre-defined design items
Is treated as directory in most EDA tools Commonly used library
IEEE IEEE standard library STD VHDL standard library Work Used defined library
Library & Use (Example)librarylibrary ieee;
useuse ieee.std_logic_1164.all;
useuse ieee.std_logic_arith.all;
useuse ieee.std_logic_unsigned.all;
librarylibrary work;
useuse work.my_package.all;
Agenda Overview Entity Architecture Function Procedure Library & Use PackagePackage Configuration
Format of Package File
package PackageName is PackageDeclarations;
end [package] [PackageName];
package body PackageName is PackageBody;
end [package body] [PackageName];
Declaration
Body
A package file has 2 Parts, Declaration parts and Body parts
Package Example (sub-program)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;---------------------------------
packagepackage my_package isis
function SUM2(S1, S2: in std_logic_vector) return std_logic_vector; procedure NOT_PROC(A: in std_logic; B: out std_logic);
endend my_package;
package bodypackage body my_package isis
function SUM2(S1, S2: in std_logic_vector) return std_logic_vector is variable tmp: std_logic_vector(S1'range); begin tmp := S1+S2; return tmp; end SUM2;
procedure NOT_PROC(A: in std_logic; B: out std_logic) is begin B := not A; end NOT_PROC;
endend my_package;
Package Declarationspackage PackageName is ProcedureDeclaration; FunctionDeclearation; ComponentDeclaration; SubtypeDeclaration; ConstantDeclaration; SignalDeclaration; FileDeclaration; AliasDeclaration; AttributeDeclaration;end [package] [PackageName];
Declaration
Package Example (sub-program)library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;---------------------------------
packagepackage my_package isis
function SUM2(S1, S2: in std_logic_vector)return std_logic_vector; procedure NOT_PROC(A: in std_logic; B: out std_logic);
endend my_package;
package bodypackage body my_package isis function SUM2(S1, S2: in std_logic_vector) return std_logic_vector is variable tmp: std_logic_vector(S1'range); begin tmp := S1+S2; return tmp; end SUM2; procedure NOT_PROC(A: in std_logic; B: out std_logic) is begin B := not A; end NOT_PROC;
endend my_package;
Package Example (Component)
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;---------------------------------
packagepackage my_package isis componentcomponent ANDN isis generic (wid : integer := 2); port ( X: in bit_vector(wid-1 downto 0); F : out bit );
end component;end component;
endend my_package;
entityentity ANDN isis
generic (wid : integer := 2); port (X:in bit_vector(wid-1 downto 0); F:out bit );
endend;
…
X(0) X(1) X(2)
X(wid-1)
F
Package Example (Type & Constant)
library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;---------------------------------packagepackage my_package isis constant const_K : integer := 100; type state_type is (idle, s0, s1, s2, s3); subtype Byte is Std_logic_vector(7 downto 0); component XYZ is port ( A, B, C : in std_logic; F : out std_logic ); end component; component ANDN is generic (wid : integer := 2); port ( X : in bit_vector(wid-1 downto 0); F : out bit ); end component; function SUM2(S1, S2: in std_logic_vector) return std_logic_vector; procedure NOT_PROC(A: in std_logic; B: out std_logic);endend my_package;
package bodypackage body my_package isis
function SUM2(S1, S2: in std_logic_vector) return std_logic_vector is variable tmp: std_logic_vector(S1'range); begin tmp := S1+S2; return tmp; end SUM2;
procedure NOT_PROC(A: in std_logic; B: out std_logic) is begin B := not A; end NOT_PROC;
endend my_package;
Types & Constan
t
Components
Sub-program
Agenda Overview Entity Architecture Function Procedure Library & Use Package ConfigurationConfiguration
Configuration Definition (1)
configurationconfiguration ConfigName ofof EntityName isis forfor ArchitectureName
end for;end for;
endend [configuration] [ConfigName] ;;
Configuration Example (WHAT.vhd)library ieee;use ieee.std_logic_1164.all;---------------------------------entity WHAT is
port(A, B : in bit;
F : out bit);
end WHAT;
entity WHO is
port(X : in bit;
Y : out bit);
end WHO;
---------------------------------
architecture WHAT_arch0 of WHAT isbegin F <= A and B;end WHAT_arch0; architecture WHAT_arch1 of WHAT isbegin F <= A or B;end WHAT_arch1;architecture WHAT_arch2 of WHAT isbegin F <= A xor B;end WHAT_arch2;architecture WHO_arch0 of WHO isbegin Y <= not X;end WHO_arch0;architecture WHO_arch1 of WHO isbegin Y <= X;end WHO_arch1;
configuration WHO_conf0 of WHO is
for WHO_arch0 end for;end WHO_conf0;
configuration WHO_conf1 of WHO is
for WHO_arch1 end for;end WHO_conf1;
Configuration Example (WHAT)
WHAT
WHO
WHO_conf0
WHO_conf1
Configuration Definition (2)
configurationconfiguration ConfigName ofof EntityName isis forfor Label: ComponentName
USE …;
end for;end for;
endend [configuration] [ConfigName] ;;
Configuration Example (UWHAT.vhd)library ieee;use ieee.std_logic_1164.all;library work;use work.my_package.ALL;entityentity UWHAT is port (A0, A1, A2, A3: in bit; B0, B1, B2, B3: in bit; F0, F1, F2, F3 : out bit;
X0, X1 : in bit; Y0, Y1 : out bit );endend UWHAT;
architecturearchitecture UWHAT_arch0 of UWHAT isbegin U0: WHAT port map(A0, B0, F0); U1: WHAT port map(A1, B1, F1); U2: WHAT port map(A2, B2, F2); U3: WHAT port map(A3, B3, F3); P0: WHO port map(X0, Y0); P1: WHO port map(X1, Y1);endend UWHAT_arch0;
configurationconfiguration UWHAT_conf of UWHAT is for UWHAT_arch0 for U0: WHAT use entity work.WHAT(WHAT_arch0); end for; for U1: WHAT use entity work.WHAT(WHAT_arch1); end for; for others: WHAT use entity work.WHAT(WHAT_arch2); end for; for all: WHO use configuration work.WHO_conf0; end for; end for;endend UWHAT_conf;
U0:WHAT
U1:WHAT
U2:WHAT
P0:WHO
P1:WHO
A0B0
A1B1
A2B2
A3
B3
X0
X1
F0
F1
F2
F3
Y0
Y1
U3:WHAT
Configuration Example (UWHAT)UWHAT
A0B0A1B1A2B2A3B3
X0
X1
F0
F1
F2
F3
Y0
Y1
configurationconfiguration UWHAT_conf of UWHAT is for UWHAT_arch0 for U0: WHAT use entity work.WHAT(WHAT_arch0); end for; for U1: WHAT use entity work.WHAT(WHAT_arch1); end for; for others: WHAT use entity work.WHAT(WHAT_arch2); end for; for all: WHO use configuration work.WHO_conf0; end for; end for;endend UWHAT_conf;
Configuration Examplearchitecture Structure_View of Processor is component ALU port (…); end component; component MUX port (…); end component; component Latch port ( … ); end component;begin
A1: ALU port map (… ) ;
M1: MUX port map ( … ) ;
M2: MUX port map ( …) ;
M3: MUX port map ( … ) ;
L1: Latch port map ( … ) ;
L2: Latch port map ( … ) ;end Structure_View ;
library TTL, Work ;
configurationconfiguration V4_27_87 ofof Processor isis use Work.all ;
end configurationend configuration V4_27_87 ;
forfor Structure_View
forfor A1: ALU use configuration TTL.SN74LS181 ;
end forend for ;
forfor M1,M2,M3: MUX use entity Multiplex4 (Behavior) ;
end forend for ;
forfor all: Latch -- use defaults
end forend for ;
end forend for ;