LHCC February 2005Geoff Hall 1
10th LHC electronics workshop
Boston 13-17 September 2004 Organisers
Harvard University Boston University Massachusetts Institute of
Technology Chair
John Oliver (Harvard)
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LECC mandate Director of Research for Collider Physics and the
Management of the Experimental Physics Division set up the LHC Electronics Coordinating Committee (2001)
Successor to LERB and LEB Present chairperson: Lucie Linssen
Identify and implement common solutions for the electronics of the LHC experiments wherever possible.
Review and recommend support for the LHC experiments.
Facilitate the design, fabrication, testing, commissioning and maintenance of electronics for the LHC experiments.
Organize an annual LHC Electronics Workshop
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Previous LHC Electronics workshops
1995 Lisbon Portugal 1996 Balaton Hungary 1997 London UK 1998 Rome Italy 1999 Snowmass USA 2000 Cracow Poland 2001 Stockholm Sweden 2002 Colmar France 2003 Amsterdam Holland 2004 Boston USA
Second time in non-European location
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Special factors in 2004
In USA university terms begin in early September Conference location must be commercial site Both Snowmass (1999) and Boston (2004) hired hotel and had to
purchase most facilities Boston is an expensive city for hotels
Majority of participants are usually from Europe Despite important US contributions to LHC electronics
R&D activities declining as LHC construction is main activity R&D for sLHC still at an early stage
Consequences Some impact on attendance
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Participation
Number of Delegates at the LHC Electronics Workshops
110 128 128 128 12788
28
35
1 1
7 13 6 11 22
182164
16
19 15 161541
0
50
100
150
200
250
1997 1998 1999 2000 2001 2002 2003 2004
Europe USA Japan
US attendance, including invited speakers, increases when conference in US
But offset by diminished number from Europe
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Contents of workshops
Main features Overviews of technology developments & topical issues Presentations from LHC electronics projects Printed proceedings within 4-6 weeks of workshop
also available via Web since 1999 Discussion
Evolution Regular reports from some projects (never static) Early years had strong focus on R&D with many unknowns
Eg commercial rad-hard electronic technologies Presently more emphasis on board level electronics
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Organisation 2004 Local organisers Scientific organisation
John Oliver, Chair J. Christiansen CERNGeorge Brandenburg P. Farthouat CERNPeter Fisher F. Formenti CERNEric Hazen G. Hall Imperial CollegeEd Kearns M. Letheren CERNRobyn Lynn Simpson C. Parkman CERNFrank Taylor E. Petrolo INFN, Rome
S. Quinton RALV. Radeka BNL
Proceedings P. Sharp CERNSandra Claude, CERN W. Smith Wisconsin
M. Turala INP CracowV. Vuillemin CERN(L Linssen CERN)
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Presentations and Proceedings
Statistics 10+ invited plenary talks (6 in proceedings) [2003: 11] 60 parallel session talks (54 in proceedings) [2003: 65] 21 posters [2003: 18] Proceedings: CERN 2004-010 (bit later than usual) http://lhc-workshop-2004.web.cern.ch/
Presentations also available http://agenda.cern.ch/fullAgenda.php?ida=a043274
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Finances
As usual the Workshop self-financing but more risk than usual for reasons explained
We are very grateful for support from The local institutes CERN - especially proceedings and poster Industrial exhibitors and sponsors
CAEN spa Wiener Plein and Baus Ltd Universal Voltronics LeCroy Corporation
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Plenary talks The Large Synoptic Survey Telescope project C. Stubbs Harvard High luminosity upgrades of the LHC machine O. Bruning CERN Front-End Electronics for Linear Collider Detectors B. Schumm Santa Cruz BTeV electronics J. Butler FNAL
Field Programmable Gate Arrays in 2004 P. Alfke Xilinx Corp Enabling Technologies for High Performance Chip Scale Packaging T. Buck DDI Corp
LHC Optical links: experience from CMS and prospects F. Vasey CERN Trigger and Data Acquisition for the Super LHC W Smith Wisconsin
Fundamental discontinuities in silicon technology; Examples, consequences, and outlook for the future B. Meyerson IBM
Giga-channel FFT microwave spectrometers and pixilated nanosecond optical staring arrays: Some SETI technology P. Horowitz Harvard
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Comments on plenary talks Very high quality
Several exceptional - and inspirational - speakers Benefited from US location - and local and committee contacts
Important messages from machine (Oliver Bruning) For future, sLHC will be challenging
Beam structure not yet fixed but 80MHz almost excluded a clearer picture of LHC commissioning is emerging
Response from electronic community Need to stay abreast of machine plans - and dialogue needed
Machine operation in early phase impacts electronic commissioning SLHC choices need input from electronics
superbunch operation undesirable
A snapshot of a few highlights…
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FPGA & Board technology talks
Highly complementary messages from industry experts Speed increasing Feature size decreasing Requirements on technology become more demanding
Impedances, complexity, component size and density New materials and regulations
Many such boards in use in LHC experiments Scale of production from few to a few hundred boards
Packaging technology closely related to FE hybrids HEP expectations deviate from industry standards
Eg use of unpackaged components, via sizes, ….
13 LHC Boston Sept 04 PA
FPGA State of the Art 2004FPGA State of the Art 2004
90-nanometer manufacturing technology
Ten Gigahertz serial I/O (SerDes) in silicon
0.07 femtosecond asynchronous data capture windowcauses 1.5 ns metastable delay
P Alfke
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Board technology
Large boards are complex, with many layers, soexpensive and risky without careful attention
PWB =Printed Wiring
Board
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Some of this is familiar…
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ASICs
Parallel meeting on ASIC strategy for future As explained last year, HEP depends on ASIC technology
We are forced to follow industry trends eg 0.25µm CMOS available until ~2009 Successful CERN-managed common MPW runs and contract
Concern about future access and cost Characterisation and circuit development with new constraints
needs several years New design tools have to be used
View from industry…
17 LHC Boston Sept 04 PA
ASICs Are Losing GroundASICs Are Losing GroundMask set >$1M + design + verification + risk
ASICS are only for extreme designs::Extreme volume, speed, size, low power
0
0.5
1
1.5
2
250 nm 180 nm 130 nm 90 nm 65 nm
Technology Generation
0
0.5
1
1.5
2
250 nm 180 nm 130 nm 90 nm 65 nm
Technology GenerationSource:IBM
P Alfke
Some HEP requirements fit this category
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Fundamental discontinuities in silicon technology - outlook for the future
Dr. Bernard S. Meyerson, IBM Fellow Chief Technologist IBM Systems and Technology Group
CMOS scaling paradigm is breaking down Moore’s law requires constant power density- not just size reduction Size scaling gets constantly harder (physics!) Manufacturers have tweaked circuits to gain competitive edge Result: excessive power consumption & failure of notable projects New technologies will emerge but CMOS will remain for some years Future: more intelligence inside chips to moderate power usage
“innovation has overtaken scaling as driver of semiconductor technology performance”
cf well written code in days of limited memory and processor speed Manufacturer investments growing even larger
Trend for global collaboration will continue Some lessons for other fields are apparent
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Optical technology
Now a key underpinning technology
Francois Vasey (CERN) What are lessons from LHC developments in CMS?
What are the most relevant future developments? Another fast moving field where HEP must follow trends
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Optical technology lessons
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Optical conclusions
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Conclusions from workshop
Successful and interesting conference
Important messages from LHC machine and industry complemented by important messages from HEP speakers
For the future Would like to encourage true workshop format & stimulate
discussion and feedback
Maintain and increase dialogue with machine
ASIC and optical technology should feature strongly
Now planning for 2005
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11th LHC electronics workshop
Heidelberg, Germany 12-16 September 2005 Organisers
Ulrich Uwer (Chair) K.Meier M.Schmelling K.Sparenberg U.Trunk
http://lecc2005.uni-hd.de/