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VITU N I V E R S I T Y
ECE 301 - VLSI System Design(Fall 2011)
Introduction to Verilog HDL
Prof.S.Sivanantham
VIT UniversityVellore, Tamilnadu. India
E-mail: [email protected]
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Objectives
After completing this lecture, you will be able to:
Describe the basic features of the modules in Verilog HDL
Topics Levels of abstraction
The Verilog HDL
Verilog building blocks
Verilog design hierarchy
Verilog module behaviors
ECE301 VLSI System Design FALL 2011 S.Sivanantham
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Review
What is an HDL?
How is the HDL description independent of the productimplementation and why is this an advantage?
What level of abstraction is used in:
Synthesizable designs
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Modules Verilog HDL modules
module --- The basic building block in Verilog HDL.
It can be an element or a collection of lower-level desi n
blocks.module Module name
Port List, Port Declarations (if any)
Parameters (if any)
Declarations ofwires, regs, and other variables
Instantiation of lower level modules or primitives
Data flow statements (assign)
.into these blocks).
Tasks and functions.
ECE301 VLSI System Design FALL 2011 S.Sivanantham
endmodule statement
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Declaring A Module
Cant use keywords as module/port/signal names
Choose a descriptive module name
Indicate the ports (connectivity)
Declare the signals connected to the ports
Choose descriptive signal names
Declare any internal signals
Write the internals of the module (functionality)
ECE301 VLSI System Design FALL 2011 S.Sivanantham
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Declaring Ports
A signal is attached to every port
ec are type o port input
output
nou rec ona
Scalar (single bit) - dont specify a size input cin;
Vector (multiple bits) - specify size using range
Range is MSB to LSB (left to right) Dont have to include zero if you dont want to (D[2:1]) output OUT [7:0];
ECE301 VLSI System Design FALL 2011 S.Sivanantham
npu : ;
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Module Styles
Modules can be specified different ways
Structural connect rimitives and modules
Data flow use continuous assignments Behavioral use initial and always blocks
A single module can use more than one method!
W at are t e erences?
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Module Modeling Styles
Structural style
Gate level com rises a set of interconnected ate
primitives. Switch level consists of a set of interconnected switch
pr m ves.
Dataflow style
. .,registers.
is specified as a set of continuous assignment statements.
ECE301 VLSI System Design FALL 2011 S.Sivanantham
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Module Modeling Styles
Behavioral or algorithmic style
is described in terms of the desired desi n al orithm
is without concerning the hardware implementationdetails.
can be described in any high-level programminglanguage.
is the mixing use of above three modeling styles.
is commonl used in modelin lar e desi ns.
In industry, RTL (register-transfer level) means
RTL = synthesizable behavioral + dataflow constructs
ECE301 VLSI System Design FALL 2011 S.Sivanantham
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Port Declaration
Port Declaration
in ut: in ut orts.
output: output ports. inout: bidirectional ports
Port Connection Rules
Named association Pos t ona assoc at on
ECE301 VLSI System Design FALL 2011 S.Sivanantham
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Port Declaration
module half_adder(x, y, s, c);
in ut x, ;
output s, c;
// -- half adder body-- //// instantiate primitive gates
xor xor1 (s, x, ;
Instance name is optional.
module full_adder(x, y, cin, s, cout);
and and1 (c, x, y);
endmodule
input x, y, cin;
output s, cout;
wire s1,c1,c2; // outputs of both half adders
// -- full adder body-- //
// instantiate the half adderhalf_adder ha_1 (x, y, s1, c1);
half_adder ha_2 (.x(cin), .y(s1), .s(s), .c(c2));
or (cout, c1, c2);
Connecting by using named association
ECE301 VLSI System Design FALL 2011 S.Sivanantham
endmodule.
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Structural modeling
// gate-level hierarchical description of 4-bit adder-
module half_adder (x, y, s, c);input x, y;output s, c;
a a er o y// instantiate primitive gates
xor (s,x,y);and c xendmodule
ECE301 VLSI System Design FALL 2011 S.Sivanantham
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Structural modeling
// gate-level description of full adder_ , , , ,
input x, y, cin;output s, cout;wire s1, c1, c2; // outputs of both half adders
u a er o y// instantiate the half adder
half_adder ha_1 (x, y, s1, c1);half adder ha 2 cin s1 s c2_ _or (cout, c1, c2);endmodule
cin
sx
x
ycout
HA
s
c
cys1
c1
c2x
y
ECE301 VLSI System Design FALL 2011 S.Sivanantham
HA
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Structural modeling
// gate-level description of 4-bit adder
_ _ , , _ , , _
input [3:0] x, y;input c_in;
output [3:0] sum;
output c_out;
wire c1, c2, c3; // intermediate carries
// four_bit adder body// instantiate the full adder
full_adder fa_1 (x[0], y[0], c_in, sum[0], c1);
full_adder fa_2 (x[1], y[1], c1, sum[1], c2);
u _a er a_ x , y , c , sum , c ;full_adder fa_4 (x[3], y[3], c3, sum[3], c_out);
endmodule
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Hierarchical Design
xy
4-bit parallel adder
S
cout c0
x[0]x[1]x[2]x[3] y[0]y[1]y[2]y[3]
c0coutc1c2c3
y x
CinCoutS
y x
CinCoutS
y x
CinCoutS
y x
CinCoutS
x
s[0]s[1]s[2]s[3]
x
y
s
cout
cin
HA
s c
s
ys1 c2x
y
ECE301 VLSI System Design FALL 2011 S.Sivanantham
HA
c c
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Dataflow Modeling
module full_adder_dataflow(x, y, c_in, sum, c_out);
input x, y, c_in;output sum, c_out;
assign #5 {c_out, sum} = x + y + c_in;
endmodule
cin s
Full Adderxy cout
ECE301 VLSI System Design FALL 2011 S.Sivanantham
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Behavioral Modeling
module full_adder_behavioral(x, y, c_in, sum, c_out);
input x, y, c_in;output sum, c_out;reg sum, c_out; // sum and c_out need to be declared as reg types.
speci y t e unction o a u a er always @(x, y, c_in)// can also use always @(*) or always@(x or y or c_in)
#5 {c_out, sum} = x + y + c_in;endmodule
ECE301 VLSI System Design FALL 2011 S.Sivanantham
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Mixed-Style Modeling
module full_adder_mixed_style(x, y, c_in, s, c_out);
input x, y, c_in;output s, c_out;reg c_out; x
scin
sc
sx
ys1c2
x
wire s1, c1, c2;// structural modeling of HA 1.xor xor_ha1 (s1, x, y);and and ha1 c1 x
ycout
HA
HA
c c1
_// dataflow modeling of HA 2.assign s = c_in ^ s1;assign c2 = c_in & s1;
e av ora mo e ng o ou pu ga e.always @(c1, c2) // can also use always @(*)c_out = c1 | c2;endmodule
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Structural Example
mo u e ma or y ma or, , , ;
output major ;in utV1 V2 V3 V1 N1
wire N1, N2, N3;V2
V2 , , ,A1 (N2,V2,V3),A2 (N3,V3,V1);
V3ma orOr0
or Or0 (major, N1, N2, N3);
endmoduleV1 A2
majority
ECE301 VLSI System Design FALL 2011 S.Sivanantham
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Data flow Example
mo u e ma or y ma or, , , ;
output major ;in utV1 V2 V3
assign major =V1 & V2
| V2 & V3
V1
V2 majormajorityendmodule V3
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Behavioral Example
mo u e ma or y ma or, , , ;
output reg major ;in utV1 V2 V3
always @(V1,V2,V3) begin
if (V1 && V2 || V2 && V3V1
major = 1;
elsemajor = 0;
V3
end
endmodule
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Review Questions
What are the basic components of a module? Whichcomponents are mandatory?
What are the three levels of abtraction? Does a module that does not interact with its environment
ave any por s oes ave a por s n e mo u edefinition?
ECE301 VLSI System Design FALL 2011 S.Sivanantham