ํ๋ก์ ํธ 1
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ARM CPU Architecture
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์ปดํจํฐํ๊ณผ
2009๋ฐฑ์น์ฌ
ib 1383@d k k [email protected]://embedded.dankook.ac.kr/~ibanez1383
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๊ฐ์ ๋ชฉํ 2
ARM ์ข ๋ฅ์ ํน์ง ๋ฐ ์ต์ ๋ํฅ ํ์
ARM CPU Architecture ์ดํด
ARM Assembly ์์ง
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ARM 3
ARM? Advanced RISC Machines! not In 1983 at Acorn Computers Ltd.By Herman Hauser Steve Furber Sophie Wilson Robert HeatonBy Herman Hauser, Steve Furber, Sophie Wilson, Robert Heaton, Jamie UrquhartFor low power, low cost, simple, small
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Today, the ARM family accounts for approximately 75% of all embedded 32-bit RISC CPUs.
ARMยฎ 4
They do not sells ARM processorsThey sells only IP
Whatโs the IP?Whatโs the IP?As โHard macrocellโ or โSynthesizable coreโ ... To processors manufactures
They also sells various development enviroments
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An auxiliary textbooks 5
Steve Furber Andrew SlossSteve FurberAddison-Wesley
Andrew SlossMorgan Kaufmann
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ARM Core & Family & Processor 6
ARM11ARMv6M Cortex-M1
CortexCortex-A8 Cortex-A9 Cortex-A9 MPCoreCortex-R4(F)
ARMv7-AARMv7-RARMv7-M Cortex-M3
13 stage pipeline, superscalar, application profile, NEON, ...
ARM 5TEJ
ARMv6 ARM1136J(F)-SARM11
ARM1156T2(F)-SARM1176JZ(F)-S
ARMv6T2ARMv6KZARMv6K ARM11 MPCore
8 stage pipeline, SIMD9 stage pipeline, Thumb-2
1~4 core SMP
ARMv5TE
ARMv5TEJARM7EJ-SARM7TDMIARM926EJ-SARM9E
ARM10E ARM1026EJ-S
5 stage pipeline, Jazelle, Enhanced DSP instructions
ARMv4TARM7TDMI ARM719T ARM720T ARM740TARM7TDMI
ARM946E-S ARM966E-S ARM968E-S ARM966HSARM9EARM1020E ARM1022EARM10E
XScale 80200 IOP321 PXA210 PXA250 PXA255 PXA26x PXA27x Monahans PXA900 IXP42x
3 stage pipeline, Thumb
6 stage pipeline7 stage pipeline
ARMv4SA-110 SA-1110StrongARMARM810ARM8
9 0 0ARM7TDMIARM9TDMI ARM920T ARM922T ARM940TARM9TDMI
3 stage pipeline, Thumb
5 stage pipeline, static branch prediction
ARMv2ARM1 ARM2 ARM2a
ARMv3ARM60 ARM600 ARM610ARM700 ARM710 ARM7100 ARM7500 ARM7500FE
ARM2/3
ARM6ARM7
CORE
ProcessorFAMILY
MUL instruction, MMU, CPU cache
32bit addr
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ARMv1ARM1ARM1
/ Processor, ,
Case Study: Cortex-A9 MPCore 7
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Case Study: OMAP 4 8
1080 pixel full HD ๋์์ ๋ นํ.์ฌ์, DSLR๊ธ์ 2์ฒ๋ง ํ์ ์ฌ์ง ์ดฌ์, ์ฝ 1์ฃผ์ผ๊ฐ์์ค๋์ค ์ฌ์, ๊ธฐ์กด ์ค๋งํธํฐ ๋๋น 10๋ฐฐ ์ด์ ๋น ๋ฅธ ์นํ์ด์ง ๋ก๋ฉ, 7๋ฐฐ ์ด์์ ์ปดํจํ ์ฑ
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๋ฅ, ....
ARM Architecture Ver
ARM{x}{y}{z}{T}{D}{M}{I}{E}{J}{F}{S}
x : ์ ํ๊ตฐ
y : MMU/MPUhz : cache
T : Thumb 16bit decoderD : JTAG DebuggM : ๊ณ ์ ๋ง์ ๊ธฐ
I : EmbeddedICE macrocellE : DSP ํ์ฅ ๋ช ๋ น์ดE : DSP ํ์ฅ ๋ช ๋ น์ด
J : JazelleF : VFP DeviceS : Synthesizible version
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ARM pipeline
3 stage3-stageFetch : Instruction fetchDecode : Instruction decoding, operand readExecute : ALU ์ฐ์ฐ๊ฒฐ๊ณผ ์์ฑ ๋ ์ง์คํฐ์ ๊ธฐ๋กExecute : ALU ์ฐ์ฐ๊ฒฐ๊ณผ ์์ฑ, ๋ ์ง์คํฐ์ ๊ธฐ๋ก
5-stageFetch : Instruction fecthDecode : Instruction decoding operand readDecode : Instruction decoding, operand readExecute : ALU ์ฐ์ฐ๊ฒฐ๊ณผ ์์ฑ, load/store ๋ช ๋ น์ธ ๊ฒฝ์ฐ ๋ฉ๋ชจ๋ฆฌ ์ฃผ์๊ณ์ฐ
Buffer/data : ํ์ ์ data ๋ฉ๋ชจ๋ฆฌ ์ ๊ทผ / ๊ทธ๋ ์ง ์์ผ๋ฉด ๋ชจ๋ ๋ช ๋ น์ด์ ๋ํด์ ๋์ผํ ํ์ดํ๋ผ์ธ ํ๋ฆ์ ๋ง๋ค๊ธฐ ์ํด ํ ํด๋ญ ๋์buffer ๋จWrite-back : ๊ฒฐ๊ณผ๋ฅผ ๋ ์ง์คํฐ ํ์ผ์ ์ ์ฅ
6-stage
7 or 8-stage
6 stageFetch, Issue, Decode, Execute, Memory, Write
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Why?
ARM Architecture์ ๋ช๊ฐ์ง ํน์ง
Pipelined architecture
ํน์ ๋ช ๋ น์ด(load/store-multiple instructions)์ ๋ํ ์ฌ๋ฌ cycle์ ๊ฑธ์น ์คํ ํ์ฉ
2๊ฐ์ source reg (Rn, Rm)์ 1๊ฐ์ ๊ฒฐ๊ณผ reg(Rd)
Inline barrel shifterInline barrel shifterBarrel shifter๋ฅผ ํตํ operand์ ์ ์ฒ๋ฆฌ ์์ ๊ฐ๋ฅ
ARM 32-bit instruction set๊ณผ Thumb 16-bit instruction setThumb instruction set์ ์ฌ์ฉํ์ฌ ์ฝ๋ ํฌ๊ธฐ๋ฅผ 30% ์ ๋ ์ค์
Conditional ExecutionB h i t ti ์ ์๋ฅผ ์ค์ฌ ์ฝ๋ ํฌ๊ธฐ์ ์ฑ๋ฅ์ ํฅ์ ์ํดBranch instruction์ ์๋ฅผ ์ค์ฌ ์ฝ๋ ํฌ๊ธฐ์ ์ฑ๋ฅ์ ํฅ์ ์ํด
Data forwadingPipeline ๋จ๊ณ์์ ๊ฐ operand์ forwading๊ฐ๋ฅp p g
PC๊ฐ์ ๋ชจํธ์ฑ์ฆ๊ฐ๋ PC๊ฐ์ ๋ณ๋ reg์ ์ ์ฅ
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ARM Register
r 0r 1r 2
r 0r 1r 2
r 0r 1r 2
r 0r 1r 2
r 0r 1r 2
r 0r 1r 2
U b ked r 3r 4r 5r 6
r 3r 4r 5r 6
r 3r 4r 5r 6
r 3r 4r 5r 6
r 3r 4r 5r 6
r 3r 4r 5r 6
Unbanked Register
r 8r 9r 1 0
r 7r 8r 9r 1 0
r 7r 8r 9r 1 0
r 7r 8r 9r 1 0
r 7r 8r 9r 1 0
r 7r 8r 9r 1 0
r 7
r 11r12r 13(SP)r 14(LR)
r 11r12r 13(SP)r 14(LR)
r 11r12r 13(SP)r 14(LR)
r 11r12r 13(SP)r 14(LR)
r 11r12r 13(SP)r 14(LR)
r 11r12r 13(SP)r 14(LR)
Banked Register
( )r 15(PC)
CPSR
( )r 15(PC)
( )r 15(PC)
( )r 15(PC)
( )r 15(PC)
( )r 15(PC)
SPSR SPSR SPSR SPSR SPSR
User
User Mode System Mode
FIQ IRQ Supervisor Undefined Abort
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User Mode System Mode
Processor Mode
Privileged modecpsr์ ์์ ํ ์ฝ๊ณ ์ธ ์ ์๋ 6๊ฐ์ ๋ชจ๋
abort(๋ฉ๋ชจ๋ฆฌ ์ก์ธ์ค๊ฐ ์คํจํ ๊ฒฝ์ฐ) modeFIQ IRQ dFIQ, IRQ modesupervisor(๋ฆฌ์ ๊ฑธ๋ ธ์ ๋ ์ง์ , OS ์ปค๋์ด ๋์) modesystem(user mode์ ํน์ํ ๊ฒฝ์ฐ๋ก, cpsr์ ์์ ํ ์ฝ๊ณ ์ธ ์ ์์) modeundefined(๋น ์ ์๋ ๋ช ๋ น์ด ๋ฑ์ ๋ง๋ฌ์ ๋) mode
์ผ๋ฐ ๋ชจ๋User mode(์ผ๋ฐ app์ฉ)cpsr์ ์ ์ด ํ๋๋ ์ฝ๊ธฐ๋ง ๊ฐ๋ฅ, ์ํ ํ๋๊ทธ๋ ์ฝ๊ณ ์ฐ๊ธฐ๊ฐ ๊ฐ๋ฅ
ํน์ mode ์ง์ ๋ฐฉ๋ฒ์์ ์ ๊ฐ์Privileged mode์์ CPSR์ mode ๊ฐ์ set
Exception์ ๋ฐ์
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Special registers
๊ฐ ๋ ์ง์คํฐ์ ์ฉ๋
R13 : SP(Stack Pointer) ์คํ์ ์ฌ์ฉํ์ง ์์ ๊ฒฝ์ฐ ์ผ๋ฐ ๋ ์ง์คํฐ๋ก ์ฌ์ฉ ๊ฐ๋ฅ
R14 : LR(Link Register)Branch์ ๋ณต๊ท ์ฃผ์ ์ ์ฅ
์ฌ์ฉํ์ง ์์ ๊ฒฝ์ฐ ์ผ๋ฐ๋ ์ง์คํฐ๋ก ์ฌ์ฉ ๊ฐ๋ฅ
์คํ ๋น์ฌ์ฉ์ผ๋ก ์ธํ ์ฑ๋ฅํฅ์ ๊ฐ๋ฅ
R15 : PC(Program Counter)R15 : PC(Program Counter)Operand๋ก ์ฌ์ฉ๊ฐ๋ฅ
mov pc, lr ?
์ค์ฒฉ๋ b h?์ค์ฒฉ๋ branch?
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CPSR registerCurrent Program Status RegisterCurrent Program Status Register
N Z C V UNUSED I F T Mode
7 6 5 4 3 2 1 031 30 29 28
Q
27
CPSR[4:0]CPSR[4:0] Mode ์๋ฏธ Register
10000 User User mode user
10001 FIQ fast interrupt ์ฒ๋ฆฌ _fiq
10010 IRQ ์ ์ interrupt ์ฒ๋ฆฌ _irq
10011 SVC Software interrupt (SWI) ์ฒ๋ฆฌ _svc
10111 Abort Memory fault ์ฒ๋ฆฌ abt10111 Abort Memory fault ์ฒ๋ฆฌ _abt
11011 Undef ์ ์๋์ง ์์ ๋ช ๋ น์ด trap ์ฒ๋ฆฌ _und
11111 System Privileged OS task ์คํ user
CPSR[31:27] ๋น๊ต๋ช ๋ น์ด๋ S๊ฐ ๋ถ์ ๋ช ๋ น์ด์ ์ํด ๋ณ๊ฒฝN: negative
๋ง์ง๋ง ALU ์ฐ์ฐ์ ๊ฒฐ๊ณผ๊ฐ ์์ ๊ฐ
32bit ๊ฒฐ๊ณผ๊ฐ์ MSB๊ฐ 1 Z: zero
๋ง์ง๋ง ALU ์ฐ์ฐ์ ๊ฒฐ๊ณผ๊ฐ 0C: carry
๋ง์ง๋ง ALU ์ฐ์ฐ์ด๋ shift ์ฐ์ฐ์ ๊ฒฐ๊ณผ๊ฐ carry-out๋ฅผ ๋ฐ์์ํด
V: oVerflow
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๋ง์ง๋ง ALU ์ฐ์ฐ์ด sign bit์ overflow๋ฅผ ๋ฐ์์ํด
Q: Enhanced DSP instruction์์ overflow๋ saturation
ARM์ Exception
Exception, INT ๋ฐ์์ PC๊ฐ์ ๋ฏธ๋ฆฌ ์ ํด์ง ์ฃผ์๋ฅผ ๊ฐ๋ฆฌํด
Exception/INT ์ฝ์ ์ฃผ์
Reset RESET 0x0000 0000Reset RESET 0x0000 0000
Undefined Instruction UNDEF 0x0000 0004
Software Instruction SWI 0x0000 0008
Prefetch Abort PABT 0x0000 000c
Data Abort DABT 0x0000 0010
Reserved 0x0000 0014
Interrupt Request IRQ 0x0000 0018
Fast Interrupt Request FIQ 0x0000 001c
๊ทธ๋ ๋ค๋ฉด 0x00000000 ๋ฒ์ง์๋?branch ๋ช ๋ น์ด ๋ ์ด๋ธ
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Booting ๊ณผ์ ๋ฐ ์์ธํ Interrupt ์ฒ๋ฆฌ๋ ๋ค์์ ์์ธํ...
Barrel Shifter
Operand์ ์ ์ฒ๋ฆฌ ์์
Rn Rm Immediate #imm
Register Rm
Barrel Shifter
Logical shift left by immediate Rm, LSL #imm
Logical shift left by register Rm, LSL Rs
Logical shift right by immediate Rm, LSR #imm
Logical shift right by register Rm, LSR Rs
Arithmetic shift right by immediate Rm, ASR #imm
A i h i hif i h b i R ASR R
ALUArithmetic shift right by register Rm, ASR Rs
Rotate right by immediate Rm, ROR #imm
Rotate right by register Rm, ROR Rs
RdRotate right with extend Rm, RRX
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Arithmetic Shift์ Logical Shift
Logical right shift๋ shift ๋์ด ๋น์ด ์๋ ์ผ์ชฝ k๊ฐ์ bit๋ฅผ 0์ผ๋ก ์ฑ์
Arithmetic right shift๋ shift ๋์ด ๋น์ด ์๋ ์ผ์ชฝ k๊ฐ์ bit๋ฅผ ์๋์MSB(Most Significant Bit)๋ฅผ ๊ฐ์ง๊ณ ์ฑ์S ( os S g ca )๋ฅผ ๊ฐ์ง ์ฑ์
10000000001110000100000100000100X >> 8
00000000100000000011100001000001
11111111100000000011100001000001
Logical shift
Arithmetic shiftArithmetic shift
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Barrel Shifter ์ฌ์ฉ ์
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ARM Basic Instructions
binary op ์ค ๋ช
0000 AND Rd = op1 AND op2
0001 EOR Rd = op1 XOR op20001 EOR Rd op1 XOR op2
0010 SUB Rd = op1 โ op2
0011 RSB Rd = op2 โ op1
0100 ADD Rd 1 + 20100 ADD Rd = op1 + op2
0101 ADC Rd = op1 + op2 + C
0110 SBC Rd = op1 โ op2 + C โ 1
0111 RSC Rd = op2 โ op1 + C โ 1
1000 TST op1 AND op2 CPSR
1001 TEQ op1 XOR op2 CPSR
1010 CMP op1 โ op2 CPSR
1011 CMN op1 + op2 CPSR
1100 ORR Rd = op1 OR op2
1101 MOV Rd = op2
1110 BIC Rd = op1 AND (NOT op2)
1111 MVN Rd = NOT op2
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p
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์ํ ์์ (7/7)
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PSR ๊ด๋ จ, MUL, ๋ฐ์ดํฐ ์ด๋ instruction
MRS{cond} Rd, <psr> Transfer PSR contents to a reg
MSR{cond} <psr>, Rm Transfer reg contents to PSR
MUL{cond}{S} Rd, Rm, RsRd = Rm * Rs
MLA{cond}{S} Rd, Rm, Rs, RnRd R * R + RRd = Rm * Rs + Rn
LDR{cond}{B} Rd, address{!}Rd = contents of addr
LDR{cond}{B} Rd, =expressionRd iRd = expression
STR{cond}{B} Rd, address{i}contents of addr = Rd
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contents of addr Rd
Multiple reg Data Transfer
1 Post-Increment Addr
<LDM|STM>{cond}mode Rn{!}, {reg_list}{^}
1. Post-Increment Addr2. Pre-Increment Addr3 Post Decrement Addr3. Post-Decrement Addr4. Pre-Decrement Addr
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Swap instruction & SWI
SWP{cond}{B} Rd, Rm, [Rn]
Temp = Rn; Rn = Rm; Rd = tempB: bit 0 ~ 7๊น์ง๋ง ์ํฅ ๋ฏธ์นจ
Int disable์์ด semaphore์ฐ์ฐ ๊ฐ๋ฅ
SWI{cond} <expression>
Software interrupt instructionExpression์ ๋ด์ฉ์ด SWI๋ช ๋ น์ low24bit์ ์ธ์ฝ๋ฉ๋จExpression์ ๋ด์ฉ์ด SWI๋ช ๋ น์ low24bit์ ์ธ์ฝ๋ฉ๋จ
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์ํ ์์ (1/2)
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์ํ ์์ (2/2)
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Branch Instruction
24๋นํธ์ offset์ 2๋นํธ left๋ก shiftํ์ฌ, +/-32MB ์ ๊ทผ
๋ง์ฝ 32MB๊ฐ ๋์ ๋๋ Register๋ฅผ ์ด์ฉ
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ARM Procedure Call Standard(APCS)
Reg i s ter APCS name APCS ro l e0 a1 Argument 1 / integer result / scratch register1 a2 Argument 2 / scratch register2 a3 Argument 3 / scratch register2 a3 Argument 3 / scratch register3 a4 Argument 4 / scratch register4 v1 Register variable 15 v2 Register variable 26 v3 Register variable 37 v4 Register variable 48 v5 Register variable 59 sb/v6 Static base / register variable 69 sb/v6 Static base / register variable 610 sl/v7 Stack limit / register variable 711 fp Frame pointer12 ip Scratch reg. / new sb in inter-link-unit calls
d f k f13 sp Lower end of current stack frame14 lr Link address / scratch register15 pc Program counter
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Stack
Why? When?Stack addressing mode
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49Stack Mode
HighSP
HighSP
base baseLow
Full AscendingLow
base
Empty Ascending
High base High basebase g base
Low
SP
LowSP
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Full Descendingo
Empty Descending
Addressing Mode and Stack 50
Addressing ModePost-increment Addressing (IA)Pre-increment Addressing (IB)g ( )Post-decrement Addressing (DA)Pre-decrement Addressing (DB)
StackStackFull Assending (FA)Empty Assending (EA)Full Decending (FD)Full Decending (FD)Empty Decending (ED)
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์กฐ๊ฑด๋ถ ์คํ
๋๋ชจ๋ ์๋ฏธ ์ํํ๋๊ทธ
EQ equal Z
NE not equal zq
CS HS carry set / unsigned higher ๋๋ same C
CC LO carry clear / unsigned lower c
MI minus / negative N
PL plus / positive ๋๋ zero n
VS overflow VVS overflow V
VC no overflow v
HI unsigned higher zC
LS unsigned lower ๋๋ same Z or c
GE signed greater than ๋๋ equal NV or nv
LT signed less than Nv or nVLT signed less than Nv or nV
GT signed greater than NzV or nzv
LE signed less than ๋๋ equal Z or Nv or nV
๋จ๊ตญ๋ํ๊ต ๋ฐฑ์น์ฌ
AL always(๋ฌด์กฐ๊ฑด ์คํ) ignored
ARM Assembly Test 52
-O3
ARM compiler
IA compiler
-O3
๋จ๊ตญ๋ํ๊ต ๋ฐฑ์น์ฌ
IA compiler