EE414 Embedded Systems
Ch 1. Introduction to Embedded Systems
Part 2/2
Byung Kook KimSchool of Electrical Engineering
Korea Advanced Institute of Science and Technology
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Overview 1.1 Embedded Systems Overview 1.2 Design Challenge – Optimizing Design Metrics
Technologies 1.3 Processor Technologies 1.4 IC Technologies 1.5 Design Technologies
1.6 Trade-offs
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1.3 Processor Technology Technology
A manner of accomplishing a task, especially using technical processes, methods, or knowledge.
Three key technologies for embedded systems: 1.3 Processor technology 1.4 IC technology 1.5 Design technology
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Processor Technology The architecture of the computation engine used
to implement a system’s desired functionality
Processor Does not have to be programmable Not equal to (contains) general-purpose processor
General-purpose processor Application-specific processor Single-purpose processor
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Processor technology Processors vary in their customization for the
problem at hand Summing function
total = 0for i = 1 to N loop
total += M[i]end loop
General-purpose processor
Single-purpose processor
Application-specific processor
Desired functionality
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Processor Technology
Application-specific
Registers
CustomALU
DatapathController
Program memory
Assembly code for:
total = 0for i =1 to …
Control logic and State register
Datamemory
IR PC
Single-purpose (“hardware”)
DatapathController
Controllogic
State register
Datamemory
index
total
+
IR PC
Registerfile
GeneralALU
DatapathController
Program memory
Assembly code for:
total = 0for i =1 to …
Control logic and State
register
Datamemory
General-purpose (“software”)
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A. General-purpose processors Programmable device used in a variety of
applications Maximize the number of devices sold Also known as “microprocessor”: Central
Processing Unit on a chip Features
Program memory General datapath with large register file and
general ALU User benefits
Programming the functionality (software): Low time-to-market and NRE costs High flexibility
“Pentium” the most well-known, but there are hundreds of others.
IR PC
Registerfile
GeneralALU
DatapathController
Program memory
Assembly code for:
total = 0for i =1 to …
Control logic and
State register
Datamemory
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B. Single-purpose processors Digital circuit designed to execute exactly one
program a.k.a. coprocessor, accelerator or peripheral JPEG codec
Features Contains only the components needed to
execute a single program No program memory
Benefits Fast, Low power, and Small size Low unit cost for large volumes
Drawbacks High NRE cost Low flexibility High per-product cost for small volumes.
DatapathController
Control logic
State register
Datamemory
index
total
+
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C. Application-specific [instruction-set] processors (ASIP)
Programmable processor optimized for a particular class of applications having common characteristics Compromise between general-purpose and single-
purpose processors Features
Program memory Optimized datapath Special functional units
Benefits Some flexibility, good performance, size and
power Types
Microcontrollers Digital Signal Processors: Multiply-accumulate unit
IR PC
Registers
CustomALU
DatapathController
Program memory
Assembly code for:
total = 0for i =1 to …
Control logic and
State register
Datamemory
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1.4 IC technology The manner in which a digital (gate-level) implementation
is mapped onto an IC (Integrated Circuit or chip) IC technologies differ in their customization to a design
Most popular: CMOS IC’s consist of numerous layers (perhaps 10 or more)
IC technologies differ with respect to who builds each layer and when.
Layout Feature size (submicron, nano).
source drainchannel
oxide
gate
Silicon substrate
IC package IC
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IC technology (II)
Three types of IC technologies: A. Full-custom/VLSI (Very Large Scale Integration)
B. Semi-custom ASIC (Application Specific Integrated Circuit)
C. PLD (Programmable Logic Device)
Independent from processor technology.
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A. Full-custom/VLSI All layers are optimized for an embedded system’s
particular digital implementation Designing down to transistor level
Placing transistors Sizing transistors Routing wires
Send mask spec to fabrication plant. Benefits
Excellent performance, small size, and low power. Drawbacks
Very high NRE cost (e.g., $300k), long time-to-market Used for high-volume or extremely performance-critical applications.
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B. Semi-custom ASIC Lower layers are fully or partially built
Devices Gate Array Standard Cell: AND gate or AND-OR-INVERT
Designers are left with routing of wires and maybe placing some blocks (Mask design)
The most popular IC technology
Benefits Good performance and size Less NRE cost than a full-custom implementation (perhaps $10k
to $100k)
Drawbacks Still require weeks to months to develop
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C. PLD (Programmable Logic Device) All layers already exist
Designers can purchase an IC Programmable circuit: Connections on the IC are either created
or destroyed to implement desired functionality
Devices Programmable Logic Array (PLA)
Programmable array of AND gates and programmable array of OR gates Programmable Array Logic (PAL)
One programmable array Field-Programmable Gate Array (FPGA)
More general connectivity among blocks. Very popular
Benefits Very low NRE costs, almost instant IC availability
Drawbacks Bigger, expensive (perhaps $30 per unit), power hungry, slower.
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Moore’s lawTRENDS – Moore’s Law The most important trend in embedded systems
Predicted in 1965 by Intel co-founder Gordon MooreIC transistor capacity has doubled roughly every 18 months
for the past several decades
10,000
1,000
100
10
1
0.1
0.01
0.001
Logic transistors per chip
(in millions)Note:
logarithmic scale
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Graphical illustration of Moore’s law
1981 1984 1987 1990 1993 1996 1999 2002
Leading edgechip in 1981
10,000transistors
Leading edgechip in 2002
150,000,000transistors
Something that doubles frequently grows more quickly than most people realize! A 2002 chip can hold about 15,000 1981 chips inside itself
Low-cost high-performance embedded systems proliferate.
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1.5 Design Technology The manner in which we convert our concept of desired
system functionality into an implementation
Top-down design process: popular Refines the system through several abstraction levels System level
System specification: in C, English Distributing into several processors.
Behavioral specification Behavior of each processor.
Register Transfer (RT) specification Assembly code level or Register transfer level
Logic specification Boolean equations.
Design Technology (II) Design Approaches – Increased productivity
Compilation/Synthesis Automates exploration and insertion of implementation details
for lower level.
Libraries/IP Incorporates pre-designed implementation from lower
abstraction level into higher level.
Test/Verification Ensures correct functionality at each level, thus reducing
costly iterations between levels.
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Design Technology (III) Ideal top-down design process & Design
approachesSystem
specification
Behavioralspecification
RTspecification
Logicspecification
To final implementation
Compilation/Synthesis
Libraries/IP
Test/Verification
Systemsynthesis
Behaviorsynthesis
RTsynthesis
Logicsynthesis
Hw/Sw/OS
Cores
RTcomponents
Gates/Cells
Model simulators/checkers
Hw-Swcosimulators
HDLsimulators
Gatesimulators
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A. Compilation/Synthesis Specify desired functionality in an abstract manner Automatically generates lower-level implementation
details. Improve productivity by reducing the amount of details
Tools Logic synthesis tools: Boolean expr. -> Connection of logic gates
(netlist) Register-transfer (RT) synthesis tool: FSM, RT -> Datapath &
controller of Boolean eq. Behavioral synthesis tool: Sequential -> FSM, RT
Software compiler: Sequential program -> Assembly code (RT) System synthesis tool: System spec. -> Sequential programs.
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B. Libraries/IP Library: Reuse of preexisting implementations
Improve productivity (Find rather than design)
Libraries Logic level library: Layout of logic gates and cells RT-level library: Layout of RT components Behavioral-level library: Components, such as compression, bus,
processor etc. System level library: Complete systems solving particular
problems.
Intellectual Property (IP) Cores in an intellectual form Copy protected.
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C. Test/Verification Ensure that functionality to be correct.
Tools Simulation
Gate level simulator RT level (HDL: Hardware Description Language)
Provide output waveforms, given input waveforms. Processor level: HW & SW co-verification. System level: model simulator, model checker.
Formal verification Growing in popularity.
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Design productivity exponential increase
Exponential increase over the past few decades. 1981: 100 TRs/month 2002: 5000 TRs/month.
100,000
10,000
1,000
100
10
1
0.1
0.01
1983
1987
1989
1991
1993
1985
1995
1997
1999
2001
2003
2005
2007
2009
Prod
uctiv
ity(K
) Tra
ns./S
taff
–M
o.
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1.6 Trade-offs In the past:
Hardware and software design technologies were very different
Recent maturation of synthesis enables a unified view of hardware and software
Hardware/software “codesign” The co-design ladder -> Unified view
Implementation
Assembly instructions
Machine instructions
Register transfers
Compilers(1960's,1970's)
Assemblers, linkers(1950's, 1960's)
Behavioral synthesis(1990's)
RT synthesis(1980's, 1990's)
Logic synthesis(1970's, 1980's)
Microprocessor plus program bits: “software”
VLSI, ASIC, or PLD implementation: “hardware”
Logic gates
Logic equations / FSM's
Sequential program code (e.g., C, VHDL)
The choice of hardware versus software for a particular function is simply a tradeoff among various design metrics, like performance, power, size, NRE cost, and especially flexibility;
there is no fundamental difference between what hardware or software can implement.
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Independence of processor and IC technologies Basic tradeoff
General vs. custom With respect to processor technology or IC technology The two technologies are independent
General-purpose
processorASIP
Single-purpose
processor
Semi-customPLD Full-custom
General,providing improved:
Customized, providing improved:
Power efficiencyPerformance
SizeCost (high volume)
FlexibilityMaintainability
NRE costTime- to-prototype
Time-to-marketCost (low volume)
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Design productivity gap While designer productivity has grown at an impressive rate over the
past decades, the rate of improvement has not kept pace with chip capacity
10,000
1,000
100
10
1
0.1
0.01
0.001
Logic transistors per chip
(in millions)
100,000
10,000
1000
100
10
1
0.1
0.01
Productivity(K) Trans./Staff-Mo.IC capacity
productivity
Gap
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Design productivity gap (II) 1981 leading edge chip required 100 designer months
10,000 transistors / 100 transistors/month 2002 leading edge chip requires 30,000 designer months
150,000,000 / 5000 transistors/month Designer cost increase from $1M to $300M
10,0001,000
100101
0.10.01
0.001
Logic transistors per chip
(in millions)
100,00010,00010001001010.10.01
Productivity(K) Trans./Staff-Mo.IC capacity
productivity
Gap
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The mythical man-month The situation is even worse than the productivity gap indicates In theory, adding designers to team reduces project completion time
In reality, productivity per designer decreases due to complexities of team management and communication
In the software community, known as “the mythical man-month” (Brooks 1975) At some point, can actually lengthen project completion time! (“Too many cooks”)
10 20 30 400
10000
20000
30000
40000
50000
60000
43
24
1916 15 16
18
23
Team
Individual
Months until completion
Number of designers
1M transistors, 1 designer=5000 trans/month
Each additional designer reduces for 100 trans/month
So 2 designers produce 4900 trans/month each
…
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Summary Three key technologies
Processor: general-purpose, application-specific, single-purpose
IC: Full-custom, semi-custom, PLD Design: Compilation/synthesis, libraries/IP,
test/verification
A unified view of hardware and software is necessary to improve productivity Hardware and software codesign.
References [1] Frank Vahid, “Embedded system design: A
unified hardware/software introduction”, John Wiley & Sons, 2002.
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