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3D Stacked Architectures withInterlayer Cooling - CMOSAICProf. John Thome, LTCM-EPFL, Project PI
Prof. Yusuf Leblebici, LSM-EPFL
Prof. Dimos Poulikakos, LTNT-ETHZProf. Wendelin Stark, FML-ETHZ
Prof. David Atienza Alonso, ESL-EPFLDr. Bruno Michel, IBM
Dr. Thomas Brunschwiler, IBM PCB
Micro-Heater
Liquid
Micro-Channels
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CMOSAIC: Technological Aims CMOSAIC aims to make animportant contribution to thedevelopment of the first 3D
computer chip with interlayer
cooling for extremely high
computational power with reduced
power consumption. Very ambitious project that
combines significant microchannel
cooling research, 3D thermal
simulations and novel new micro-
fabrication techniques for TSVs,interconnects, bonding, etc. to
make the first 3D thermal/electrical
test vehicle.
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Two-Phase Cooling of 3D StackedMicroprocessors: 3D Test VehicleY Madhour, et al..
Si IC dieCu TSV
Fluid inlet
DRIE microchannels
Fluid outlet
Flip-chip bonded (sequential)Force-controlled reflow processTotal Force on chip: 12.6 [N] at265C (2.2MPa)Force on individual joint: 0.6g
Individual joint after reflow Cross section polished sampleContact area: 70% of initial plated surface
Test vehicle
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Wafer-level TSV Process Compatible with Interlayer Cooling
3 4
Deep TSV Fabrication process
A deep TSV process, where thewafer thickness is greater than
50m, is needed toaccommodate cooling channels
with depth greater than 50m.
Aspect ratio of the TSV is morethan 1:6.
M Zervas, Y Leblebici
80 100 120 140 160 180 200 220 240 260 280 3000
10
20
30
40
50
60
70
TSVDistance[m]
Couplingc
apacitance[
fF]
TSVcouplingcapacintaceoverthecoolingliquid
liquid=1
liquid=3
liquid=5
liquid=7
liquid=9
liquid=11
Si
Cooling
channel
TSV
Ctsv Ccoupling
Si
Ctsv
TSV
Average TSV resistance below 1,withapeakat13. Parasitic MOS capacitance Ctsv 0.8pF (Cu SiO2- Si) Parasitic coupling capacitance Ccoupling over the dielectric cooling
liquid up to 60fF
Histogram of theTSV resistance
TSV coupling capacitance
simulations in the presence of
liquid channels.
7/28/2019 CMOSAIC, Nano-Tera Conferencde, Bern May 2013
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CMOS-Compatible Chip-to-Chip IntegrationChip-level 3D integration platform based on wafer
reconstitution, bonding, and TSV fabrication
Y Temiz, Y LeblebiciMicroprocessor post-CMOS processing and stacking
TCp
BomCp
Two 50m thick chips arebonded and electrically
connected by Cu TSVs.
Daisy-chain measurementsdemonstrate 0.5 resistance
with 99% yield for 1280 TSVs.
Top chip thinningand etching
Bottom chippassivation andredistribution layer
patterning
Bonding and TSVfabrication
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3D Heat Transfer Test Vehicle
Y Madhour, M Zervas, T Brunschwiler, G Schlottig, B Michel, Y Leblebici and JR Thome
7/28/2019 CMOSAIC, Nano-Tera Conferencde, Bern May 2013
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2D Multi-Microchannel Flow Boiling ExperimentS Szczukiewicz, N Borhani, JR Thome 2D visualisation of two-phase refrigerant flow
Multi-microchannel evaporator having 67 channels with the inlet orifices e=2 and 100x100mcross-section areas, Tsat=31.96oC,Tsub=5.63K,q=30.69W/cm2G=496.1kg/m2,s, slow motion (30fps), CCD recorded @2000fps,IR recorded @60fps
G=1643.02kg/m2s, slow motion (30fps), CCD recorded @2000fps,IR recorded @60fps
Flow directionFor the test section havingthe orifices with theexpansion ratio e=2, theflow tends to stabilize atthe relatively high mass
fluxes and heat fluxes.
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S. Szczukiewicz, N. Borhani, JR Thome
Footprint temperature
maps of the test sections
base provided IR camera
for two-phase flow boiling
of R236fa forGch=2299 kg/m2s, qb=48.6 W/cm2.
600000 temperature pixels
per second using inhouse
IR camera calibration.
2D Flow Boiling Tests for Characterizing 3D-ICs
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Benefits of enhanced flowfluctuations for liquid
cooling
Higher heat transfer andbetter hot-spot cooling
Planned: measure andevaluate
Impact on coolingperformance in 3D chips
Detailed heat transfer studyincluding fluid temperaturemaps
Water Cooled Electronic Chips 2D Experiments
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Full 3D Heat Transfer/Fluid Flow Simulator
Yassir Madhour, Brian P DEntremont and John R Thome
Novel 3D model for chip stacks with interlayer microchannel two-phase
cooling with combined heatandflow spreadingAdvantages: Mechanistic, flow-pattern-based methods for
microchannel boiling and 2-phase pressure drop.
Heat/fluid flow spreading, TSVs and non-uniform q. Resolves vertical distribution of heat and thermal
resistance between evaporator channels.
Over three-fold increased performancewhen properly laying out hot spot
locations in the multiple layers
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Fast Simplified 3D Thermal Simulator
Arvind Sridhar and David Atienza
7/28/2019 CMOSAIC, Nano-Tera Conferencde, Bern May 2013
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Active Run-Time Thermal Management
Mohamed Sabry and David Atienza
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Superhydrophobic Surfaces: Enhanced Flow
3 4
M. Rossier, D. Paunescu, W.J. Start
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3D ALE-FEM for Microscale Two Phase Flows
Development:[1] Comparison of surface representations;[2] Arbitrary Lagrangian-Eulerian Technique;[3] Test case: 3D microchannel
G. Rabello, N. Borhani, JR Thomesur
face
surfac
e
standard approach Lagrangian approach
D(u)
Dt+p =
1
N1/2 [(u +uT)] + g +
1
Eof
u
t+ (u u) u
u = 0
u = u
u = 0
Lagrangian
Eulerian
surface
tension
gravitymesh velocity
[1]
[2]
[3]
dd
cross section
Goals:
3D Arbitrary Lagrangian-Eulerian FiniteElement code; Coupled heat transfer and two-phase flow Predict flows in microscale complexgeometries;
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CMOSAIC - Project SummaryCMOSAIC project has:
Developed numerous micro-fabrication
techniques necessary for making 3D-IC
stacked computer chips a future reality.
Undertaken extensive micro-scale heat
transfer research to understand the
physical mechanisms of the flows.
Developed new thermal predictionmethods to describe the h.t. process.
Developed simulation tools to emulate
the 3D cooling process and proposed a
run-time thermal control code.
Developed hydrophobic surfaces.
CMOSAIC is the most sophisticated 3D-
IC test vehicle available to date!
CMOSAIC makes an important industrial
statement towards 3D-IC computing.
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