Constraint-Based Embedded Program Composition
IMPACT• Rapid Construction of Efficient Embedded Systems.
• Multiple System Variants for Little Cost.
• Rapid, Low Cost System Evolution.
• Traceabilty from Requirements to Implementation
• Ability to Customize Tools for Specific Domains
• New Design Methodology: AO + Model-Based
NEW IDEAS• AO Merging a Model-Based & Language Approaches
• Model-Based System Design Space Spec• Textual Constraints/Requirements Spec.
• System-Level Constraint Expression Language• AO-Based Strategy Language for Constraint Distribution and Application• Weaver Infrastructure for Automated Constraint Application• Meta-Weaver for Specification of Weavers• Automated Application of RT Constraints
SCHEDULE
. 3/01 Spec. & Strategy Lang. V1
. 6/01 Constraint Weaver & ATR Demo
. 3/02 Spec. & Strategy Lang. V2
. 9/02 Resource Constr. Weaver/Demo
. 3/03 Complete Spec/Strat Lang
. 11/03 Meta-Weaver Descr.
. 9/04 SW Radio Demo
System SW/HW Description
WaveformDescr. #1
AOConstraint
Specs
ConstraintWeaver
SystemComposition
WaveformDescr. #N
ConstraintWeaver
SystemComposition
System Design Space/Embedded Object
Specification
Customized/OptimizedEmbedded
System SW-Based Radio
Institute for Software Integrated SystemsVanderbilt University
Constraint-Based Embedded Program
Composition
Institute for Software Integrated SystemsVanderbilt University
PI: Ted BaptyJeff Gray, Sandeep Neema
Project Goals
• Investigate the Interactions between MBS+AO
• Extend Existing Model-Based Embedded System Design System– Language-based Constraints, – Strategy Language for Constraint Distribution
• Customize the tools for Communications• Demonstrate on Software-Based Radio
Application
ReconfigurableRuntime Environment
Adaptive Computing SystemsModel-Integrated Design Environment
Behavioral ModelsMODELSGraphical
ModelBuilder
ModelAnalysis
ToolsAlgorithmModels
ResourceModels
ATR
SW HWSW HW
Simulation Environment
SystemGeneration
Multi-AspectModeling
Environment
Model-Integrated Design Environment (MIDE)
• Design Capture for HW/SW Codesign: Multiple Aspects– Software/Algorithm Data Flow with Multiple Design Alternatives– Hardware Resources: Heterogeneous (DSP,RISC,FPGA)– Dynamic System Behavior: Multi-modal systems– Constraint Specification Language: Link SW/HW/Behavior– Result: Comprehensive, Flexible HW/SW System Model
• Analysis of Models (Design)– Design-Space Exploration:
• Optimize design, select best configurations from alternative designs
• Highly scalable using OBDD– Numerical/Algorithmic Simulation with Matlab– Multiple-Resolution Performance Simulation with Discrete Event
Simulator
Model-Integrated Design Environment (MIDE)
• HW/SW System Synthesis– Generate Real-Time Schedules– Generate VHDL for FPGA or ASIC– Generate Interconnection Topology/Communication Maps– Generate Reconfiguration Manager Configuration– Result: Functional HW/SW System w/ Dynamic Reconfiguration
Capabilities. Compatible with Industry-standard VHDL Compilers
• Runtime Support– Microkernel for Heterogeneous Distributed DSP’s– Virtual Hardware Microkernel for FPGA/ASIC– Dynamic System Reconfiguration Controller– Real-Time, reconfiguration support.– Result: Portable, heterogeneous uniform execution
environment
Multiple-View Graphical Modeling/Flexible Design Space
BehavioralStructuralResource
Modeling ParadigmStructural/Algorithmic Description
Compound
Compound
Software
Hardware
Compound
Primitive Template
Primitive
Primitive
Template
Compound Primitive
Primitive
Compound
Compound
Primitive
Primitive
PrimitiveCompound
Model/Object Hierarchy Example Model
Primitive
Defining A Design SpaceTemplates for Algorithm Alternatives
Long RangeTrack
AlgorithmAlternatives
Preprocess Filter
XCorr
Error Comp
Image DB
Spatial DomainPreprocess 2D FFT
Mult
Error Comp
Img Spec DB
Spectral DomainSensor
GuidanceLoss of Track
Modeling ParadigmResource Models
Processor
Network
Ports
ASIC
Core PortsCore
FPGA
Ports
ObjectHierarchy
ExampleModel
Network
Processor
Processor
Processor
FPGA FPGA
ASIC
Modeling Paradigm Behavioral Description: Hierarchical State Machine
Mode A Mode B
Mode C
AttributesAlgorithms
Performance SpecsConstraints (Power/Size/User Defined)
TransitionRules
TransitionRules
TransitionRules
TransitionRules
S1 S3S2
hierarchicalparallelFSM
Behavior Model
Processing Structure Models
Behavior andCompatibilityConstraints
P1
P3
P2
e1[S21]// /../
/../
Pr2Pr1 Pr3
C1
Resource Models
ResourceConstraints
hierarchicalinterconnectalternatives
(mode=(S1 or S2))implies(P1=P1i))(mode!=S3)implies
(Pr2.assignees =(P1i or P2j))and(Pr2=Pr2j)
(D1.time - D2.time) < 2
TimingConstraints
Constraint Modeling
PowerConstraints
(mode=S2 implies (Proc.Powr<10))
Design Space Exploration
Behavior Mod.(Hier. Par. FSM)
Structural Mod.(Hier. Altern.)
Constraints(OCL)
Binary Encoding
Binary Encoding
Binary Encoding
BDD Representation
BDD Representation
BDD Representation
FullSymbolic
DesignSpace
Pruned DesignSpace
ResourceModel
Binary Encoding
BDD Representation
OBDDAnalysis
System Synthesis
Kernel
Kernel
BIDIRIFC
XC4010 FPGAC40 DSP
C40 DSP Altera FPGA
DATA I/O
HOSTPC
STREAMSIFC - BIDIR
STREAMSIFC OUT
STREAMSIFC IN
IN IFC
OUT IFC
P2
P2
P1
P1
P1
P1
OUT IFC IN IFC
P2
P3
IN IFC OUT IFC
ASIC IFC
P3P2
Multiple Data Streams
P1ASIC
Real-Time Schedules,Communication Maps
VHDL forFPGA Configs
I/OInterfaces
I/OInterfaces
COMMInterfaces
Difficulties in ManagingGraphically Specified
Constraints
A
B
c d e1 2
3
B
c d e1’’ 2’’ 4
F
B
c d e1’ 2’
3’
4Multiple Levelsof Hierarchy Replicated
Structures
ContextSensitive
ChangeMaintenance???
Constraints Are Critical!!
• Define functional properties of system
• Ensure proper component interaction
• Designer’s leverage to guide synthesis
• Bad Constraint Management = Inflexible,
unwieldy development.
Develop Constraint Language
Aspect-OrientedConstraint Language
• Develop Language for Specifying Constraints– Operational
• Mode-dependent behavior
– Performance• Timing• Cost: Power/Parts $/Volume/Weight
– Composibility: (Part A ~ Part B, Part C !~ Part D)
– Resource: Process X requires Part D– Relationships to Modeling Aspects
Constraint ApplicationStrategy Language
• Specify how to apply constraints across object hierarchy.
• Determines how constraints are divided/responsibility shared among components.
• Flexible to permit different goals– Latency optimization– Throughput optimization– ….
Object Hierarchy
Propagation/Distribution Strategy
System Constraints
Constrained Object Hierarchy
C
C C
C C C C C C
C C C C C C C C
Weaving/Constraintdistribution
Pruned Object Hierarchy
ConstraintSatisfaction/ComponentSelection(OBDD)
void main(void){ Task t1, t2, t3;
Mutex m1, m2; Semaphore s1;
t1 = CreateTask (. t2 = CreateTask (. t3 = CreateTask (. m1 = CreateMut . m2 = CreateMu .
System Synthesis
C
CC
C
CC
C
CC
C
CC
C
CC
C
AO Strategies and Constraints
Constraint Weaver
Object Graph
Constrained Object Graph
AO Strategies
Constraint Weaver
Object Graph
Strategized Object Graph
C
CC
C
CC
C
CC
C
CC
C
CC
C
AO Constraints
Constraint Weaver
Constrained Object Graph
Strategized Object Graph
(1) Constraint aspect(from weaver, or parent strategy)
(3) Propagated Constraint(to sub-objects)
(2)
Con
stra
int a
ppli
cati
on
1. Core.def
3. Core.parse
Syntax TreeGenerator
2. Aspect..def
4. Aspect..parse
Parser(core) Parser(aspect)
Syntax TreeDefinition
(core)
Syntax TreeDefinition(aspect)
5. interpreter.def
InterpreterGenerator
PCCTS
Interpreter
Wea
ver
Parser(core) Parser(aspect)
Syntax TreeDefinition
(core)
Syntax TreeDefinition(aspect)
Syntax Tree(core)
Syntax Tree(aspect)
Interpreter
Weaved Program
Core Program Aspect Program
Wea
ver
Demonstration Plans
SW “RF”Components
Runtime Infrastructure
Synthesis
Waveform#1
Waveform#2
Weaver
UnconstrainedSW Radio
Real-Time DesignStrategy