Convertidores para sensores 1 de 23 F. Medeiro
Ingeniero en Electrónica, 2º Curso
Convertidores A/D
Instituto de Microelectrónica de Sevilla
Fernando Medeiro
Universidad de Sevilla
para señales de sensores
CNM, CSIC
Dpto. Electrónica y Electromagnetismo
Universidad de Sevilla
Escuela Superior de Ingenieros
Convertidores para sensores 2 de 23 F. Medeiro
Interface A/DA/DAmplification
Filtering
Analogsignal
digitalsignal
0 2e+05 4e+05 6e+05 8e+05 1e+06Frequency (Hz)
-120
-100
-80
-60
-40
-20
0
Am
plitu
de (d
BV
)
Resolution (DR)
Speed
Output spectrum
log(Freq.)1G100M10M1M100K10K1K1002468
101214161820
Thermal noise limit↑ (bit)
Video
Personal Comm.Disk Drivers
HDTV
Seismology
DC Instrum
22
10
Audio
SpeechRadar
Hz
Integrating ADC Σ∆ ADC Flash, Pipeline,Interpolative
ADSL
DR
Algo-rithmic
2dB(0.33bit)/year
[Nishimura Ph.D. 1993] Σ∆ modulation-based converters suitable for
a large number ofapplications
Incremental ADC
& sensor interfaces.
Convertidores A/D para sensores
Convertidores para sensores 3 de 23 F. Medeiro
Conversión Sigma-Delta Principios básicos
H z( )
D/A
−+
DecimatorModulator
Digital filter “Downsampling”
Antialiasing filter
fS 2⁄
fd 2⁄
x y yd
Nnxa
yf
t
...
xa t( ) xsh t( ),
S/H
xsh
n...
y n( )
n...
yf n( )
n...
yd n( )
X f( )
fb fS 2⁄ fS
antialiasing filterspurious
Xsh f( )
fb fS 2⁄ fS
Y f( )
fb fS 2⁄ fS
quantization errorwith noise-shaping
Y f f( )
fb fS 2⁄ fS
digital filter Yd f( )
fb fS
...
fd
OversamplingNoise-shaping
Gross quantization
Digital processing
Convertidores para sensores 4 de 23 F. Medeiro
Conversión Sigma-Delta “Ruído” de cuantización y sobremuestreo
i
y
e
i
∆
∆ 2⁄
∆– 2⁄
imax
imaximin
imin
y
i
i
e ∆ 2⁄
∆– 2⁄
∆gq
• Quantization error = deterministic function of the input, however [Benn48]
♦ If varies randomly from sample to sample
♦ If the number of quantization levels is large
• Total quantization noise power integrated in the signal band (In-band noise)
i SE f( ) ∆2
12 fS------------ Constant( )≅
quantization noise
PQ SE f( ) fd
fd– 2⁄
fd 2⁄
∫∆2
12------
fdfS-----
∆2
12------ if fS fd=
∆2
12M------------ if fS Mfd=
= = =
i y
y gq i e+=
fS1fd/2 fS2
M = oversampling ratio
Convertidores para sensores 5 de 23 F. Medeiro
Conversión Sigma-Delta El modulador Sigma-Delta
STF z( ) cte=
NTF z( ) 0→for
z 1→low-frequency( )
H z( ) ∞→⇒ for z 1→
+i gq
e
y
H z( )
D/A
−+
Σ∆ Modulator
xS/H
y
n bit
Quantizermodel
Z-domain relationships
Y z( ) STF z( )X z( ) NTF z( )E z( )+= Y z( ) H z( )1 H z( )+---------------------- X z( ) 1
1 H z( )+---------------------- E z( )+=
H z( )z 1–
1 z 1––-----------------=
g1
− g1'
D/A
xi
ey
First-order Σ∆ Modulator [Inose, Tran. S. Elect. & Tel.1962]
Convertidores para sensores 6 de 23 F. Medeiro
Conversión Sigma-Delta Modulador Sigma-Delta de 1er orden
g1
− g1'
D/A
xi
ey
H z( )z 1–
1 z 1––-----------------=
Z-domain relationships:
Y z( ) z 1– X z( ) 1 z 1––( )E z( )+=
Y z( ) H z( )1 H z( )+---------------------- X z( ) 1
1 H z( )+---------------------- E z( )+=
f-domain relationships:
First-ordernoise-shaping
Delay
SQ f( ) SE f( ) 1 j– 2π ffS-----
exp–2
SE f( ) 4 π ffS-----
sin2⋅= =
z j2π ffS-----
exp=Noise Shaping
fSfb
digital filterNTF f( ) 2
noise
SE f( )
PQ SQ f( ) fd
fd– 2⁄
fd 2⁄
∫ ∆2
12------ π2
3M3-----------≅= M
fS
fd----- 1 fd;» 2fb= =
Decrease in PQ by increasing M = 9dB/octave(3dB/octave for a single quantizer)
g1' g1=
Convertidores para sensores 7 de 23 F. Medeiro
Conversión Sigma-Delta Caracterización dinámica
• Signal-to-noise ratio (SNR): " " at the modulator output
♦ Often given in dB. For a sinusoidal input of amplitude :
♦ Signal-to-(noise+distortion) ratio (TSNR)
• Dynamic range (DR): " " at the modulator output
♦ Full-scale input range = output range of the in-loop D/A converter
♦ For single-bit quantization,
• Effective resolution (b):
♦ 0.5bits/3dB DR♦ ∆(b) / ∆(M) = 1.5bit/octave (1st-order Σ∆M) or 0.5bit/octave (quantizer)
Signal powerIn-band noise power-------------------------------------------
A
SNR dB( ) 10log10A2 2⁄PQ
-------------- =
SN
R(d
B)
Amplitude (dBV)
Overloading
Full-scale signal powerIn-band noise power
------------------------------------------------
AF S ∆ 2⁄= DR dB( )⇒ 10log10∆ 2⁄( )2
2PQ------------------=
b bit( )DR dB( ) 1.76–
6.02---------------------------------------= DR 3 2 2b 1–( )⋅=[ ]
Convertidores para sensores 8 de 23 F. Medeiro
g1
− g1'
D/A
xi
ey• How to increase resolution?
♦ Increasing M; if fb↑ => fS↑↑
♦ Increasing the order of NTF(z)
♦ Increasing the number of quantizer levels
1st-order Σ∆ Modulator
For the same Msmaller
noise power
PQ∆2
12------ π2
3M3-----------=
g2− g2'
g1
− g1'
D/A
i1 i2x e
yZ-domain relationships :
Y z( ) z 2– X z( ) 1 z 1––( )2E z( )+=
2nd-ordernoise-shaping
Delay
frequency-domain relationships:
2nd-order Σ∆ Modulator [Candy, Trans. Comm. 1985]
SQ f( ) SE f( ) 1 j2π ffS-----
exp–4
SE f( ) 16 π ffS-----
sin4⋅= =
PQ SQ f( ) fd
fd– 2⁄
fd 2⁄
∫∆2
12------ π4
5M5-----------≅=
∆(DR) vs. M = 15dB/octave (2.5bit/octave) 10-6 10-5 10-4 10-3 10-2 10-1 10010-21
10-17
10-13
10-9
10-5
10-1
f fS⁄
NT
Ff()
2
1st-order
2nd-ord
er
g1' g1= g2' 2g1g2=
Conversión Sigma-Delta Arquitecturas-I
Convertidores para sensores 9 de 23 F. Medeiro
g2
− g2'
g1
− g1'
D/A
gL
gL'−
eyx
Single-loop Lth-order Σ∆ Modulator
Z-domain relationships :
Y z( ) z L– X z( ) 1 z 1––( )LE z( )+=
frequency-domain relationships :
SQ f( ) SE f( ) 22L π ffS-----
sin2L⋅=
PQ∆2
12------ π2L
2L 1+( )M 2L 1+( )--------------------------------------------=
∆(DR) vs. M = 3(2L+1)dB/octave(L+1/2bit/octave)
Problems:
• High-order modulators (L>2) are not unconditionally stable
• Instability occurs for some input levels and initial conditions that cannot be predicted analytically
• Techniques to stabilize high-order loops cause a significant loss of resolution respect to the ideal case
L integrators
Conversión Sigma-Delta Arquitecturas-II
Convertidores para sensores 10 de 23 F. Medeiro
STF z( )
A i z 1–( )N i–
i 0=
L
∑
z z 1–( ) L B i z 1–( )L i–
i 1=
L
∑– A i z 1–( )L i–
i 0=
L
∑+
--------------------------------------------------------------------------------------------------------------------------=
+
+
+
...
D/A
...
A0
A1
A2
AL
B1
B2
BL
y
x
Z-domain relationships:[Lee & Sodini, ISCAS 1987]Y z( ) STF z( )X z( ) NTF z( )E z( )+=
eNTF z( )
z 1–( )L Bi z 1–( )L i–
i 1=
L
∑–
z z 1–( )L Bi z 1–( )L i–
i 1=
L
∑– A i z 1–( )L i–
i 0=
L
∑+
--------------------------------------------------------------------------------------------------------------------------=
• Reduced |NTF(f)| out of the band => increase stability
♦ All Bi = 0 => all zeros at DC (Butherworth or Chebychev)
♦ Otherwise, zeros in the stop-band => max-imize filter selectivity (Inverse Cheb. or Elliptic)
Goods: Problems:
• Increased hardware complexity
• Optimum coefficients imply large capacitors in SC implementations
♦ Increased occupation area
♦ Increased power consumption
Conversión Sigma-Delta Arquitecturas-III
Convertidores para sensores 11 de 23 F. Medeiro
g1' g= 1 g 3' g 1g2g( )⁄–= H1 z( ) z–=
2' 2g1'g= g 3'' g1g2g( )⁄= 2 z( ) 1 z 1––( )=
g4' g3''g= 1g3'
g1g2g 3------------------–
1g4'
g3''g4--------------–
= H3 z( ) z–=
g4'' g1g2g3g( )⁄= 4 z( ) 1 z 1––( )=
Σ∆1
Σ∆2
Σ∆N
L 1
L2
LN
CA
NC
ELL
ATI
ON
LO
GIC
e1
e2
eL
yN
y2
y1
y
x
x3
x2
xN
y1
E1g2− g2'
g1− g 1'
D/A
g3g3'g3''−
− y2
E2
D/A
H1 (z )
++d 1 H 2 z( )
d 0
−
g4g4'g4''−
−y3
E3
D/Ad 3 +
H3
z( )
+ H 4 z( )
d2
−
Cancellation logic
y
x
[Yin & Sansen, JSSC94]
2-1-1 Cascade 4th-order Σ∆ Modulator
Y z( ) STF z( )X z( ) NTF1 z( )E1 z( )NTF2 z( )E2 z( ) NTF3 z( )E3 z( )
++ +
=
Z-domain relationships:
STF z( ) z 4–∼NTF1 z( ) NTF2 z( ), 0=
NTF3 z( ) 1 z 1––( )4∼Y z( ) z 4– X z( ) d3 1 z 1––( )4E3 z( )+=
Conversión Sigma-Delta Arquitecturas-IV
Convertidores para sensores 12 de 23 F. Medeiro
Conversión Sigma-Delta Cuantización “multibit”
SE f( )q2
12fS------------= q Full scale
2B 1–--------------------=
∆ resolution( ) 3.32log10 2B 1–( )=
H z( )
D/A
−+
Multi-bit Σ∆ Modulator
xS/H
y
B bits
-1.0000
001
010
011
100
101
110
111
-1.0Analog input
Binary input / output
Analog output
Non-linearity
e
q
• Reduced quantization noise
• Improved stability
• Better fitting to approximate analysis
Goods:
Problems!
• Modulator linearity limited by that of the DAC
♦ Need of correction techniques or proper architectures
Convertidores para sensores 13 de 23 F. Medeiro
g1
− g1'
D/A
xi
ey
FreqFO
LD
ED
BA
CK
NO
ISE
Input Level
SNR (dB)
-1.0 DI
AO
Linearity error
Defective settling errors
Finite DC-gain
Non-linear DC-gain
vo (V)
Av
(dB
)
A0
Thermal noise
Weight mismatch
Comparator hysteresis
DAC non-linearity
ClockJitter PT PQ PSt PTh ...+ + +=
Conversión Sigma-Delta Otros mecanismos de error
Convertidores para sensores 14 de 23 F. Medeiro
g1
− g1'
D/A
xi
y
H z( )z 1–
1 z 1––-----------------=
Not possible in practice
C1
C2
v1vo
−
+
S1(φ1)
S’1(φ1)
S2(φ2)
S’2(φ2 )
+- AVv−–v−
H z( )g1z 1–
1 1 µ–( )z 1––-----------------------------------=
AV 1»µ g1 AV⁄=g1 g1' C1 C2⁄= =
e
Y z( ) z 1– X z( ) 1 z 1––( )E z( )+=
In practice: Lossy integrator
Y z( ) z 1– X z( ) 1 z 1–– µz 1–+( )E z( )+≅
Implies infinite DC-gain!
frequency-domain:
PQ µ( ) ∆2
12------
µ2
M------ π2
3M3-----------+
≅
SQ f( ) ∆2
12fS------------ µ2 4 π f
fS-----
sin2+=
NT
Ff()2
f
µ 2
Ideal
Lossy
for Lth-order single-loop Σ∆M:
PQ µ( ) ∆2
12------ µ2π2L 2–
2L 1–( )M2L 1–---------------------------------------
π2L
2L 1+( )M2L 1+----------------------------------------+
≅
dominant extra term ~ 1/M2L-1
Conversión Sigma-Delta Ganancia finita
Convertidores para sensores 15 de 23 F. Medeiro
g1' g= 1 g 3' g 1g2g( )⁄–= H1 z( ) z–=
2' 2g1'g= g 3'' g1g2g( )⁄= 2 z( ) 1 z 1––( )=
g4' g3''g= 1g3'
g1g2g 3------------------–
1g4'
g3''g4--------------–
= H3 z( ) z–=
g4'' g1g2g3g( )⁄= 4 z( ) 1 z 1––( )=
Σ∆1
Σ∆2
Σ∆N
L 1
L2
LN
CA
NC
ELL
ATI
ON
LO
GIC
e1
e2
eL
yN
y2
y1
y
x
x3
x2
xN
y1
E1g2− g2'
g1− g 1'
D/A
g3g3'g3''−
− y2
E2
D/A
H1 (z )
++d 1 H 2 z( )
d 0
−
g4g4'g4''−
−y3
E3
D/Ad 3 +
H3
z( )
+ H 4 z( )
d2
−
Cancellation logic
y
x2-1-1 Cascade 4th-order Σ∆ Modulator
Y z( ) STF z( )X z( ) NTF1 z( )E1 z( )NTF2 z( )E2 z( ) NTF3 z( )E3 z( )
++ +
=
Z-domain relationships:
STF z( ) z 4–∼NTF1 z( ) NTF2 z( ), 0=
NTF3 z( ) 1 z 1––( )4∼Y z( ) z 4– X z( ) d3 1 z 1––( )4E3 z( )+=
Conversión Sigma-Delta Desapareamiento de condensadores
Convertidores para sensores 16 de 23 F. Medeiro
Ci
Co
vivo
−
+
S1(φ1)
S’1(φ1)
S2(φ2 )
S’2(φ2 )
φ1
φ2t
SC Integrator
t0
vo(t)
t
nTSnTS-TS/2
SR
vo nTS TS–[ ]
voi
vof
Ci
Co
vo−
+
va
Cl
Cp
ε TS 2⁄( )
Integrating configuration Output voltage
OTA
OTA
ginl vi( )
gi 1 βe–( ) vi vL≤;
gi 1 βe vi vL⁄–( ) vi vL>;
=
Equivalent to...
lineal range
gi
ginl vi( )
vi
Modelling...
gmva
Clgo
va
Cp
voC i
Coi1 Io
Io–
vo TS( )
vo n 1–, viCi
C o------- 1
Ci C p+
C i------------------- ς
gm
Ceq---------
TS
2------–
exp⋅–+
if vi Io gm ς( )⁄≤
vo n 1–, viC i
C o-------
Ci C p+
C o-------------------
Io v i( )sgn
gm------------------------
gm
Ceq---------
TS
2------ t0–
–exp–+
if vi Io gm ς( )⁄>
=
ςCi
Ceq--------- 1
Cl
C o-------+
=
t0Ce q
gm---------–
Ci
Io----- vi 1
C l
C o-------+
+=
Ceq Ci Cp Cl 1Ci C p+
Co-------------------+
+ +=
vLv– L
gi Ci Co⁄=
β 1Cp
Ci-------+
ςgm
Ceq---------
TS
2------– 1–
exp⋅=
vL
Iogmς----------=
vo f vo i g ivi+=
Conversión Sigma-Delta Establecimiento incompleto
Convertidores para sensores 17 de 23 F. Medeiro
Conversión Sigma-Delta Ruido térmico
C11
C2
v1 vo-
+
C12S3(φ 2 )
S’4(φ 1)S4
(φ 1)
S ’3(φ 2)
v2
S1(φ 1)
S ’1(φ 1)S2
(φ 2)
S’2(φ 2)
φ1
φ2
Thermal noise (switches, OTA) flicker noise (OTA)
-
+
Clk(t)
y(t)x(t)
C
Folded-back noise in a SH circuit
S0
BWn/2
f
-BWn /2
sx f( )
Sy f( )
S0
τSHTS
----------- 2
1τSHTS
-----------– 2
+ fS BWn≥;
S0
BWnfS
-------------τSHTS
----------- 2
fS BWn<;
≅
Clk
0
1
0 τT TS
g1
− g1'
D/A
x
ye
Calculation technique:
For each thermal noise contributioncalculate equivalent BWn and apply
Seq C, 11f( )
τSHTS---------
2
1C12
C11---------+
kTfSC 11-------------- 1
C122
C112
---------+ 2kT
3fSC i--------------+≅
τT
TS------
2
1C 12
2
C 112
---------+ 2kTgmR on
fSCi----------------------------+
SH equation
P th 1C 12
C 11---------+
kT4MC11------------------
1C12
2
C112
---------+ kT
6MC i--------------
kTgm Ron
2M Ci------------------------+
+
=
104 105 106 107 108-190
-180
-170
-160
-150
Input level
Noi
se P
SD
(dB
/Hz)
Freq.
Calculated
HSPICE
Folded noise
τSH
f fS⁄ 1«
Convertidores para sensores 18 de 23 F. Medeiro
Capacitor non-linearity
C v( ) Co 1 α v β v2 …+ + +( )=
C v( ) Co 1 αv+( )≅
C1
C2
v1 −
+
S1(φ1)
S’1(φ1)
S2(φ2)
S’2(φ2 )
v2
v
g1− g1'
D/A
φ1
vv1
v2
y
C2o vn
α2---vn
2+ C 1
0 v1α2---v1
2+ C 2
o vn 1–α2---vn 1–
2+ +=
vn vn 1– g1 v1 1 α2---v1+
v2– α– g1vn 1– v1 v2–( ) α2---g1
2 v1 v2–( )2+ +=
v1 v2– 2π fb fS⁄( ) vn vn 1– g1 v1 1 α2---v1+
v2–+≅⇒∼
For sinusoidal inputs v1 A 2πfbn TS( )sin=AH 2,
14--- α A2=g1 C 1 C2⁄=
Opamp DC-gain non-linearity
vn
AVvi
AV 1 g1+ +-----------------------------
AV 1+( )vn 1–
AV 1 g1+ +----------------------------------+≅ vi g1 v1 V r±( )=
AV A0 1 γ 1v γ2v2 …+ + +( )=
vn vn 1– g1 vi
v i vn+
A0----------------– γ 1vn
v i vn+
A0---------------- γ 2vn
2vi vn+
A0----------------+ ++≅
-4.0 -2.0 0.0 2.0 4.0
Output voltage (V)65
70
75
80 DC-gain (dB)
γ1 γ2 1«,
Using harmonic analysis
AH 2,γ1
2A0---------- Vo V i
2 Vo2+= AH 3,
γ2
4A0---------- Vo
2 Vi2 Vo
2+=
Vi 2π fbTsA Vo«≅ g1A= AH 2,γ1
2A0---------- g1
2A2= AH 2,γ2
4A0---------- g1
3A3=
Clock Jitter
v1 nT δ+( ) v1 nT( ) 2π fbAδ 2 πfbnTS( )cos≅–
sampling time error (gaussian, σ t)SJ f( ) A2
2------
2πfbσ t( )2
fS------------------------= PJ
A2
2------
2π fbσt( )2
M------------------------=
φ1
φ2
Conversión Sigma-Delta No linealidad y “jitter”
Convertidores para sensores 19 de 23 F. Medeiro
g1
− g1'
D/A
x ie
yQ
Quantizers:
single-bit (comparator)
Hysteresis
Ph 4h2 π2L
2L 1+( )M 2L 1+( )--------------------------------------------=
hOffset Attenuated by the integrator DC-gain
Multi-bit D/A converter
Main problem: Non-linearity
10-5 10-4 10-3 10-2 10-1 100
Error (LSBs)
50
60
70
80
90
100
110
120
SN
R (d
B)
Gain errorOffset errorINL
DACIdealb xa
x
Φwa
γya
DAC model
+
off
Φ xa( ) 1 ε0–( )xaε0
A2------xa
3+=
ε027
2b 2–--------------- INL= A 2 b 1– 1–( )q=
σD2 1
2--- INL LSB's( )2q2≅
Non-linear block
d[Boser88]
Conversión Sigma-Delta Errores en el cuantizador
Convertidores para sensores 20 de 23 F. Medeiro
Convertidores A/D incrementales Principio de funcionamiento
YVin
− g1'
DAC
V ref–
V ref+
g1Filtro D
Reset
Digital
Integrador
ComparadorVo
• Tras un ciclo de reloj...
• Tras dos ciclos...
• ...
• Tras p ciclos...
• En p+1, Vo se compara otra vez con 0V, lo cual equivale acomparar Vi con
Vo 1, Vin Y1– Vref=
Vo 2, 2V in Y1 Y2+( )– Vref=
Vo p, pV in Vref Yii 1=
p
∑–= Vin⇒Vo p,
p-----------
2Vref
p--------------
Yii 1=
p
∑2
---------------+=
Vref
p---------- Yi
i 1=
p
∑ para j 1…p=
Yi
i 1=
p
∑2
---------------
p+1 niveles discretos
-1 -1 ... -1
-1 +1 ... -1
-1 +1 ... +1
+1 +1 ... +1
p valores
• Separación entre nivelesVLSB =
• Si lo igualamos al LSB deun convertidor A/D idealde B bits:
• 12bit requiere 4096 cic-los; 16bit requiere 65536ciclos; etc.
2Vref( ) p⁄
B log2p=
Convertidores para sensores 21 de 23 F. Medeiro
Convertidores A/D incrementales de segundo orden
Y1Vin g1
− g1'
DAC
g2
g2'
g2''−−
Y2
DAC
Dig
ital P
ost-P
roce
ssin
g
Digital
1-1 ADC
V ref–
V ref+
V re f–
Vref+
Reset Reset
Reset
• Código de salida
• LSB interno
D g 1'g2 p i–( )Y1 ii 1=
p
∑ g2'Y1i g2''Y2i+( )i 1=
p 1+
∑+=
VLSB
2V re f
g1g2p p 1+( )----------------------------------=
• Segundo orden en “Cascada”
• Realimentación adicional para limitarel rango de salida necesario en losintegratores => necesario en baja tensión
• => sólo 90
ciclos para 12 bit y 362 para 16 bits =>la velocidad puede aumentar
• Ganancia en velocidad:
B log2 g1g2p p 1+( )[ ]=
p1
p1 1–------------- 2 B
22B 2⁄--------------------≅ 2
B 1–2
-------------=
Convertidores para sensores 22 de 23 F. Medeiro
Y1Vin g1
− g1'
DAC
g2
g2'
g2''−−
Y2
DAC
g3
g3'
g3''−−
Y3
DAC
Dig
ital P
ost-P
roce
ssin
g
Digital
1-1-1 ADC
V ref–
V ref+
V re f–
Vref+
V ref–
Vre f+
Reset Reset
Reset
Reset
• Tercer orden en “Cascada”
• => sólo 30
ciclos para 12 bit y 74 para 16 bits =>la velocidad puede aumentar
• Inconvenientes:♦ Mayor sensibilidad a la ganacia finita♦ Problemas de desapareamiento entre
procesado analógico y digital♦ Mayor complejidad del filtro digital
B log216---p p2 1–( )
=
VLSB, eff
12Vref
p 1–( )p p 1+( )---------------------------------------=
Convertidores A/D incrementales de tercer orden
Convertidores para sensores 23 de 23 F. Medeiro
Convertidores integradores ( “dual-ramp” ) Principio de funcionamiento
YVin,DC
g1Control
D<N:1>
Start
logic
Integrator
ComparatorVo
-Vref
End
CounterPuede ser de tiempo discreto o detiempo continuo...
+
-
CR
τ RC=
CLK
Vin1 constantslope
Vin 1 τ⁄∼
2N periods
Start
CLK
Y
Vo
D<N:1> periods
T1 T2
φi r
φ ir
Vin2 Vin1<
Integrating Vin Integrating Vref–
Vo T1( ) 1τ--- V in td
0T1
∫V in T1
RC--------------= =
Vo T1 T2+( ) Vo T1( ) 1τ--- V re f td
T1
T1 T2+( )∫–
V inT1
RC--------------
V re fT2
RC----------------– 0 T2⇒ T1
V in
Vre f----------
=
= = =
D<N:1> 2N Vin
V ref----------= Vin
D<N:1>2N
--------------------- V re f=
• Robusto: insensible a imprecisiones en con-stante de tiempo y frecuencia de reloj
• Mínimo contenido analógico
• Ruidos periódicos (como por ejemplo inter-ferencias a 50Hz) son eliminados si esmultiplo entero del periodo del ruido
• Muy lento: periodos para N bits
• ha de ser muy preciso y estable
τ
T1
2 N 1+( )
Vre f