Crosslight Software, Inc., Burnaby, Canada
• Technology Computer Aided Design for semiconductor devices
What is TCAD?
• TCAD is critical for semiconductor device industry, both discrete and
integrated
• It saves time and money, provides deep understanding of the physics
Why TCAD?
• More realistic
• Device nature requires 3D (i.e. Superjunction Power Device, CIS)
Why 3D TCAD?
A Canadian company with a history
of more than 15 years
A pioneer and global leader of
optics and photonics TCAD
A fast growing TCAD provider for
silicon devices
APSYS
(Device Simulator)
CSuprem
(Process Simulator)
PICS3D
(Photonic IC
Simulator)
LASTIP
(Laser Diode)
2D/3D
TCAD
•Traditionally 3D bulk TCAD is time consuming, may take even longer than real
fabrication time
•Not Acceptable for today’s semiconductor industry
Time is the Money! Efficiency is the Key!
•Instead of bulk simulation, Crosslight adopted a new way to stack the 2D planes
in the z direction to ensure efficiency and accuracy
Crosslight’s New Approach
•Quasi-3D neglects the inter-plane dopant diffusion to save time at first, when
everything is ok, full 3D will take account all the plane to plane interaction
Quasi-3D vs. Full 3D
Power
NPN BJT
Metal
Debiasing
LDMOS
SJ LDMOS
CIS
3D-FDTD
FINFET
Specialty
MEMS
We use a vertical power NPN BJT as anexample. From layout, generate the GDSII file
Emitter
STI (Shallow Trench Isolation)
Base
Collector
Spacer/Nitride
BEOL is neglected for simplicity
Mask Layers (.msk file)
GDS2MASK.exe
Z structure (.zst file)
Z Direc. Cut(.cut file)
Crosslight provides anintegrated 3D structurecreation tool to simplifythe 3D modeling process.
1•Load the GDSII file
2•Cut the layout in the z
direction
3•The .msk and .zst files are
automatically generated
2D planes (x,y)
z direction
The z structure file (.zst file) isused to control the cut locationand planes in the z direction
The mask file (.msk file) is usedto generate mask layers in theinput file for CSuprem
CSuprem is Crosslight’sversion of SUPREM IV,originally developed by theStanford University.
You can choose from quasi3 dimensional or full 3Dsimulation, quasi3d meansthe diffusion between thez planes is not consideredto boost up speed
Emitter
Base
Collector
Nitride Spacer
STI
Advanced Physical Models ofSemiconductor Devices, is basedon 2D/3D finite element analysisof electrical, optical and thermalproperties of the semiconductordevices, with silicon as a specialcase.
1.00E-19
1.00E-17
1.00E-15
1.00E-13
1.00E-11
1.00E-09
1.00E-07
1.00E-05
1.00E-03
1.00E-01
0.00E+00 2.00E-01 4.00E-01 6.00E-01 8.00E-01 1.00E+00 1.20E+00
Ic &
Ib
(A
/m
)
Vbe (V)
Gummel Plot
2D center cut: Total(electron and hole)Current Contour Plot
Power
NPN BJT
Metal
Debiasing
LDMOS
SJ LDMOS
BCD
CIS
3D-FDTD
FINFET
Specialty
MEMS
LDMOS from ST
Huge Size! Metal Resistant is no longer
negligible
•Metal resistant comparable to device Rdson
•Different metal pattern will yield different Res.
Lump model is not good
•3D nature, too complicated to model using
lump elements.
The metal interconnect for large sized power MOSFET generally contribute toconsiderable amount of total resistance, a 3D model is generally necessary to determinethe resistance from the metal lines.
Layout:
Metal2
Metal1
Gate Poly
Via1
Contact
After Contacts CMP After Via1 CMP
After Metal2 CMP
0.00E+00
5.00E-03
1.00E-02
1.50E-02
2.00E-02
2.50E-02
3.00E-02
3.50E-02
4.00E-02
0.00E+00 5.00E-02 1.00E-01 1.50E-01
2D cut from center
I-V Curve
Contact
Metal1
Via1
Metal2
Power
NPN BJT
Metal
Debiasing
LDMOS
SJ LDMOS
CIS
3D-FDTD
FINFET
Specialty
MEMS
2D cut:Net Doping
Drain
Gate
Source
2D cut: Electric Field
Highest Electric Field islocated under gate edgein the STI, other areasare pretty flat
Contour Plot of E. Field
0.0 0.5 1.0 1.5 2.0 2.5 3.0
0.0000000
0.0000005
0.0000010
0.0000015
0.0000020
0.0000025
0.0000030
0.0000035 Id
Gm
Vg (V)
Id
0.0000000
0.0000005
0.0000010
0.0000015
0.0000020
0.0000025
0.0000030
Gm
Vth=0.8V
Threshold and Transconductance
0 20 40 60 80 100
1E-13
1E-12
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
Id (
Lo
g S
ca
le)
Vd (V)
Id
Reverse Breakdown
BVds0=95V
Quasi-saturation
Hot carrier pick upI-V curve
Vg=12V Vd=55V Self Heating with thermal conductance of 0.1 W/mK
2D cut to Show Net Doping
SuperJunction LDMOS Normal LDMOS
Superjunction has lower Surface field than normal LDMOS with the same drain bias.
6E+5 V/cm 8E+5 V/cm
0 10 20 30 40 50 60 70 80 90
1E-14
1E-13
1E-12
1E-11
1E-10
1E-9
1E-8
1E-7
1E-6
1E-5
Dra
in C
urr
en
t (A
)
Drain to Source Voltage (V)
Normal LDMOS
SuperJunction LDMOS
Comparison of Breakdown Voltage of SuperJunction LDMOS and normalLDMOS, a clear breakdown voltage increase for Superjunction LDMOSwith the same process condition.
Power
NPN BJT
Metal
Debiasing
LDMOS
SJ LDMOS
CIS
3D-FDTD
FINFET
Specialty
MEMS
2D-Cut of the Optical Generation
Optical Simulation 3D-FDTD
Relative Energy Density
2D-Cut of the Incident Light relative energy density
Finite-difference time-domain (FDTD) is acomputational electrodynamics modelingtechnique, dealing with electromagneticwave interactions with material structures.
Power
NPN BJT
Metal
Debiasing
LDMOS
SJ LDMOS
CIS
3D-FDTD
FINFET
Specialty
MEMS
Gate
Source
Drain
Top-Down Current Magnitude
I-V curve
Dual Channel
3D LOCOS growth UMOS with rotated planes
Hybrid IGBT
LDMOS
IGBT
UMOS Id-Vg
Electro Meter
RF Switch
V-MEMS Tunable VCSOAs
PC: HP Laptop with Intel Core2 [email protected] Memory 6G, Video card: 512M Nvidia 9600M GT
System: Windows Vista 64bit
MEMS-
Electrometer
MEMS-RF
Switch
NPN BJTQuasi3D
NPN BJT Full3D
Metal Interconnect
SJLDMOS
Quasi3D
SJ LDMOSFull3D
Time 40s 60s 22m 40m 17m 50m 92m
Mesh 1198 1068 36455 36455 115700 79049 85931
Planes 15 5 25 25 154 33 33