Department of Electrical and Computer Engineering
Vishal Saxena -1-
DAC Architectures
Vishal Saxena
Vishal Saxena -2-– 2 –
Static Performance
of DACs
Vishal Saxena -3-
DAC Transfer Characteristics
– 3 –
Note: Vout (bi = 1, for all i) = VFS - Δ = VFS(1-2-N) ≠ VFS
N-1 N-1
i-Niout FS iN-i
i=0 i=0
bV = V =Δ b 2
2
D/Abn
Digital input
Vout
Analog output
b1
...
Vref
• N = # of bits
• VFS = Full-scale range
• Δ = VFS/2N = 1LSB
• bi = 0 or 1
Vishal Saxena -4-
Ideal DAC Transfer Curve
– 4 –
Vout
000Din
001 011 101010 100 110 111
VFS-Δ
VFS
2
Vishal Saxena -5-
Offset
– 5 –
Vout
000Din
001 011 101010 100 110 111
VFS
2
VFS-Δ
Vos
Vishal Saxena -6-
Gain Error
– 6 –
Vout
000Din
001 011 101010 100 110 111
VFS
2
VFS-Δ
Vishal Saxena -7-
Monotonicity
– 7 –
Vout
000Din
001 011 101010 100 110 111
VFS
2
VFS-Δ
Vishal Saxena -8-
Differential and Integral Nonlinearities
– 8 –
• DNL = deviation of an output step from 1 LSB (= Δ = VFS/2N)
• INL = deviation of the output from the ideal transfer curve
Vout
000Din
001 011 101010 100 110 111
VFS
2INL
VFS-Δ
th
i
i Step Size -ΔDNL =
Δ
Vishal Saxena -9-
DNL and INL
– 9 –
Vout
000Din
001 011 101010 100 110 111
VFS
2
VFS-Δ
i
i j
j=0
INL = DNL
INL = cumulative sum of DNL
Vishal Saxena -10-
DNL and INL
– 10 –
• DNL measures the uniformity of quantization steps, or incremental (local)
nonlinearity; small input signals are sensitive to DNL.
• INL measures the overall, or cumulative (global) nonlinearity; large input
signals are often sensitive to both INL (HD) and DNL (QE).
Vout
000Din
001 011 101010 100 110 111
VFS
2
VFS-Δ
Vout
000Din
001 011 101010 100 110 111
VFS
2
VFS-Δ
Smooth Noisy
Vishal Saxena -11-
Measure DNL and INL (Method I)
– 11 –
Vout
000Din
001 011 101010 100 110 111
VFS
2
VFS-Δ
Endpoints of the transfer characteristic are always at 0 and VFS-Δ
Endpoint
stretch
Vishal Saxena -12-
Measure DNL and INL (Method II)
– 12 –
Vout
000Din
001 011 101010 100 110 111
VFS
2
VFS-Δ
Least-square
fit and stretch
(“detrend”)
Endpoints of the transfer characteristic may not be at 0 and VFS-Δ
Vishal Saxena -13-
Measure DNL and INL
– 13 –
Method I (endpoint stretch)
Σ(INL) ≠ 0
Method II (LS fit & stretch)
Σ(INL) = 0
Vout
000Din
001 011 101010 100 110 111
VFS
2
VFS-Δ
Vout
000Din
001 011 101010 100 110 111
VFS
2
VFS-Δ
Vishal Saxena -14-– 14 –
DAC Architectures
Vishal Saxena -15-
DAC Architecture
– 15 –
• Nyquist DAC architectures
– Binary-weighted DAC
– Unit-element (or thermometer-coded) DAC
– Segmented DAC
– Resistor-string, current-steering, charge-redistribution DACs
• Oversampling DAC
– Oversampling performed in digital domain (zero stuffing)
– Digital noise shaping (ΣΔ modulator)
– 1-bit DAC can be used
– Analog reconstruction/smoothing filter
Vishal Saxena -16-– 16 –
Binary-Weighted DAC
Vishal Saxena -17-
Binary-Weighted CR DAC
– 17 –
• Binary-weighted capacitor array → most efficient architecture
• Bottom plate @ VR with bj = 1 and @ GND with bj = 0
Cu = unit capacitance
VX
2Cu Cu Cu8Cu 4Cu
VR
Vo
b3 b2 b1 b0
CP
Vishal Saxena -18-
Binary-Weighted CR DAC
– 18 –
• Cp → gain error (nonlinearity if Cp is nonlinear)
• INL and DNL limited by capacitor array mismatch
R
u
N
p
N
1j
u
jN
jN
RN
1j
u
jN
up
N
1j
u
jN
jN
o
VC2C
C2b
V
C2CC
C2b
V
N
1jj
j-N
R
u
N
p
u
N
o2
bV
C2C
C2V
VX
2Cu Cu Cu8Cu 4Cu
VR
Vo
b3 b2 b1 b0
CP
Vishal Saxena -19-
Stray-Insensitive CR DAC
– 19 –
VX
2Cu Cu
16Cu
8Cu 4Cu
VR
Vo
b3 b2 b1 b0
CP
A
N
1jj
j-N
R
uu
1N
p
u
N
u
N
o2
bV
A
CC2CC2
C2V
Large A needed
to attenuate
summing-node
charge sharing
Vishal Saxena -20-
MSB Transition
– 20 –
Largest DNL error occurs at the midpoint where MSB transitions, determined
by the mismatch between the MSB capacitor and the rest of the array.
R4
1j
j4
p
4o V
C2CC
C1000V
R4
1j
j4
p
321o V
C2CC
CCC0111V
δC,CCCCC :Assume u3214
uu
oo
CδCC
C
C
δC
1LSB1LSB0111V1000VDNL
Code 0111 Code 1000
Vishal Saxena -21-
Midpoint DNL
– 21 –
• δC > 0 results in positive DNL
• δC < 0 results in negative DNL or even nonmonotonicity
δC > 0 δC < 0
Di
Ao
00111 1000
+DNL
Di
Ao
00111 1000
-DNL
Vishal Saxena -22-
Output Glitches
– 22 –
• Glitches cause waveform distortion, spurs and elevated noise floors
• High-speed DAC output is often followed by a de-glitching SHA
• Cause: Signal
and clock skew
in circuits
• Especially
severe at MSB
transition where
all bits are
switching –
0111…111 →
1000…000
Time
Vo
Vishal Saxena -23-
De-Glitching SHA
– 23 –
Time
Vo
DAC...
b1
bN
VoSHA
SHA output must be smooth (exponential settling can be viewed as pulse
shaping → SHA BW does not have to be excessively large).
SHA samples the output
of the DAC after it settles
and then hold it for T,
removing the glitching
energy.
Vishal Saxena -24-
Frequency Response
– 24 –
f
|H(f)|
0 fs 2fs 3fs
SHA
ZOH
2ωT
2ωTsin
ejωH 2
ωTj
ZOH
3dB
SHA
ωωj1
1jωH
Vishal Saxena -25-
Binary-Weighted Current-Steering DAC
– 25 –
• Current switching is simple and fast
• Vo depends on Rout of current sources without op-amp
• INL and DNL depend on matching, not inherently monotonic
• Large component spread (2N-1:1)
VX
Vo
b3 b2 b1 b0 A
I/2 I/4 I/8 I/16
R
N
1jj
j-N
o2
bIRV
Vishal Saxena -26-
R-2R DAC
– 26 –
• A binary-weighted current DAC
• Component spread greatly reduced (2:1)
N
1jj
j-N
o2
bIRV
VX
Vo
b3 b2 b1 b0 A
R
R R R
2R 2R 2R 2R
I
2R
I/2 I/4 I/8 I/16
Vishal Saxena -27-– 27 –
Unit-Element DAC
Vishal Saxena -28-
Resistor-String DAC
– 28 –
• Simple, inherently monotonic → good DNL performance
• Complexity ↑ speed ↓ for large N, typically N ≤ 8 bits
VR
Vo
Vo
Di
0
b0 b0 b1 b1
1
2
3
Vishal Saxena -29-
Code-Dependent Ro
– 29 –
• Ro of ladder varies with signal (code)
• On-resistance of switches depend on tap voltage
t
Vo
VR
Vo
Ro
Di
b0 b0 b1 b1
Co
Signal-dependent
RoCo causes HD
Vishal Saxena -30-
DNL
– 30 –
RN
1
k
1j
1
k
RN
1
k
1j
1
k
j V
ΔRNR
ΔRR1j
V
R
R
V
R+ΔRNR+ΔRN-1R+ΔR1 R+ΔR2
VR...
V1 V2 VN VN+1
RN
1
k
2j
1
k
1j- V
ΔRNR
ΔRR2j
V
j 1 j 1Rj j-1 R RN
k
1
j 1 RR Rj j j-1 DNL
R ΔR ΔRVV V V V
N NRNR ΔR
ΔR σV VDNL V V DNL 0, σ
N N R R
Rσ0,ΔR
Vishal Saxena -31-
INL
– 31 –
R2
N
j
k
1j
1
k
RRN
1
k
1j
1
k
RN
1
k
1j
1
k
j VRN
ΔR1jΔR1j-N
VN
1jV
ΔRNR
ΔRR1j
V
R
R
V
RRj j R INL
σNVj-1INL V V INL 0, σ max
N N 2 R
j
j
22 2R
j R V R3 2
22 2R
V R2
j 1 N- j 1 σj 1V V , σ V
N N R
σ1 N Nσ max V , when j 1
4N R 2 2
Vishal Saxena -32-
INL and DNL of Binary-Wtd DAC
– 32 –
RINL
RDNL
σNINL 0, σ max
2 R
σDNL 0, σ max 2 INL N
R
A Binary Weighted DAC is typically constructed using unit elements, the
same way as that of a Unit Element DAC, for good component matching
accuracy.
Vishal Saxena -33-
Current-Steering DAC
– 33 –
• Fast, inherently monotonic → good DNL performance
• Complexity increases for large N, requires B2T decoder
Io
…… …
…
Binary-to-Thermometer Decoder
...
b1 bN
I I I
Vishal Saxena -34-
Unit Current Cell
– 34 –
• 2N current cells typically decomposed into a (2N/2×2N/2) matrix
• Current source cascoded to improve accuracy (Ro effect)
• Coupled inverters improve synchronization of current switches
Io
ROW/COL
Decoder
...
b1
bN
I
Φ
Φ
...
Sj Sj
Vishal Saxena -35-– 35 –
Segmented DAC
Vishal Saxena -36-
BW vs. UE DACs
– 36 –
Binary-weighted DAC
• Pros
– Min. # of switched elements
– Simple and fast
– Compact and efficient
• Cons
– Large DNL and glitches
– Monotonicity not guaranteed
• INL/DNL
– INL(max) ≈ (√N/2)σ
– DNL(max) ≈ 2*INL
Unit-element DAC
• Pros
– Good DNL, small glitches
– Linear glitch energy
– Guaranteed monotonic
• Cons
– Needs B2T decoder
– complex for N ≥ 8
• INL/DNL
– INL(max) ≈ (√N/2)σ
– DNL(max) ≈ σ
Combine BW and UE architectures → Segmentation
Vishal Saxena -37-
Segmented DAC
– 37 –
0
VFS
…
Di
Vo
2N-10
LSB’s
MSB’s
• MSB DAC: M-
bit UE DAC
• LSB DAC: L-bit
BW DAC
• Resolution: N =
M + L
• 2M+L switching
elements
• Good DNL
• Small glitches
• Same INL as
BW or UE
Vishal Saxena -38-
Comparison
– 38 –
Example: N = 12, M = 8, L= 4, σ = 1%
Architecture σINL σDNL # of s.e.
Unit-element0.32 LSB’s
0.01 LSB’s
2N = 4096
Binary-weighted
0.32 LSB’s
0.64 LSB’s
N = 12
Segmented0.32 LSB’s
0.06 LSB’s
2M+L = 260
Max. DNL error occurs at the transitions of MSB segments
Vishal Saxena -39-
Example: “8+2” Segmented Current DAC
– 39 –
Ref: C.-H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6mm2,” IEEE
Journal of Solid-State Circuits, vol. 33, pp. 1948-1958, issue 12, 1998.
Vishal Saxena -40-
MSB-DAC Biasing Scheme
– 40 –
Common-centroid global biasing + divided 4 quadrants of current cells
Vishal Saxena -41-
MSB-DAC Biasing Scheme
– 41 –
Vishal Saxena -42-
Randomization and Dummies
– 42 –
Vishal Saxena -43-
Current-Steering DAC Unit Cell
– 43 –
Vishal Saxena -44-
Current-Steering DAC Calibration
– 44 –
Vishal Saxena -45-
References
1. Y. Chiu, Data Converters Lecture Slides, UT Dallas 2012.
2. Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters,” 2nd Ed., Springer, 2005..
3. B. Boser, Analog-Digital Interface Circuits Lecture Slides, UC Berkeley 2011.
D. K. Su and B. A. Wooley, JSSC, pp. 1224-1233, issue 12, 1993.
C.-H. Lin and K. Bult, JSSC, pp. 1948-1958, issue 12, 1998.
K. Khanoyan, F. Behbahani, A. A. Abidi, VLSI, 1999, pp. 73-76.
K. Falakshahi, C.-K. Yang, B. A. Wooley, JSSC, pp. 607-615, issue 5, 1999.
G. A. M. Van Der Plas et al., JSSC, pp. 1708-1718, issue 12, 1999.
A. R. Bugeja and B.-S. Song, JSSC, pp. 1719-1732, issue 12, 1999.
A. R. Bugeja and B.-S. Song, JSSC, pp. 1841-1852, issue 12, 2000.
A. van den Bosch et al., JSSC, pp. 315-324, issue 3, 2001.