Adib AbrishamifarEE Department
IUST
Lecture 10 – Dynamic CMOS
Digital Integrated Circuit Design
inputsNMOS LogicCircuit
CLKP
CLKN
CLK
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 20082/71
Contents
} Introduction} Dynamic CMOS Logic} CMOS Domino Logic} CD Domino Logic} Dynamic CVSL} Sample-Set Differential Logic (SSDL)} Summary
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 20083/71
} As mentioned before Digital MOS circuits can be classified into two categories:} Static Circuits: require no clock or other periodic signal for
operation (except sequential logic). In these circuits at every point in time (except when switching) the output is connected to either GND or Vdd via a low resistance path
} fan-in of N requires 2N devices (n N-type + n P-type)
} Dynamic Circuits: require periodic clock signals, synchronized with data signals, for proper operation even in combinational logic. These circuits rely on the temporary storage of signal values on the (parasitic) capacitance of high impedance nodes
} requires only N + 2 transistors (n+1 N-type + 1 P-type) } takes a sequence of precharge and conditional evaluation
phases to realize logic functions
Introduction
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 20084/71
} Why Dynamic Logic?} In the area of high speed, higher Fan-in, extremely low
power dissipation, other digital logic circuit have been considered. In this lecture, two of these alternatives to CMOS are described. The circuits are basically NMOS or CMOS Gates with slight improvements. These are:} Dynamic CMOS Logic} CMOS Domino Logic
} Each of them have specific operating advantages over NMOS or CMOS, but exhibit disadvantages in other areas
Introduction
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 20085/71
Contents
} Introduction} Dynamic CMOS Logic} CMOS Domino Logic} CD Domino Logic} Dynamic CVSL} Sample-Set Differential Logic (SSDL)} Summary
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 20086/71
} Dynamic Gates use a clocked PMOS pullup} Two modes: precharge and evaluate
1
2A Y
4/3
2/3
AY
1
1
AY
Static Pseudo-NMOS Dynamic
φ Precharge Evaluate
Y
Precharge
Dynamic CMOS Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 20087/71
} The Foot} What if pulldown network is ON during precharge?} Use series evaluation transistor to prevent fight
AY
φ
foot
precharge transistorY
inputs
Y
inputs
footed unfooted
f f
Dynamic CMOS Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 20088/71
Dynamic CMOS Logic
} Dynamic CMOS Logic} To make the gate dynamic, a
clock pulse is applied to the gate of complementary P and N channel devices. This gate consists of an NMOS Logic circuit whose output node is prechargedto Vdd by the PMOS, when the clock is zero. The output node is discharged by the NMOS transistor connected to ground when the clock is high
inputsNMOS LogicCircuit
CLKP
CLKN
CLK
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 20089/71
Precharge (Clk = 0)Evaluate (Clk = 1)
Dynamic CMOS Logic
} Dynamic CMOS Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200810/71
} Once the output of a dynamic gate is discharged, it cannot be charged again until the next precharge operation
} Inputs to the gate can make at most one transition during evaluation
} Output can be in the high impedance state during and after evaluation (PDN off), state is stored on CL
Dynamic CMOS Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200811/71
Dynamic CMOS Logic
} Canonical Forms
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200812/71
Dynamic CMOS Logic
} Properties of Dynamic Gates} Logic function is implemented by the PDN only
• should be smaller in area than static complementary CMOS} Full swing outputs (VOL = GND and VOH = VDD)} Nonratioed - sizing of the devices is not important for proper
functioning (only for performance)} Faster switching speeds
• reduced load capacitance due to lower number of transistors per gate (Cint) so a reduced logical effort
• reduced load capacitance due to smaller fan-out (Cext)• no Isc, so all the current provided by PDN goes into discharging
CL• Ignoring the influence of precharge time on the switching speed
of the gate, tpLH = 0 but the presence of the evaluation transistor slows down the tpHL
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200813/71
Dynamic CMOS Logic
} Properties of Dynamic Gates} Power dissipation should be better
• consumes only dynamic power – no short circuit power consumption since the pull-up path is not on when evaluating
• lower CL- both Cint (since there are fewer transistors connected to the drain output) and Cext (since there the output load is one per connected gate, not two)
} But power dissipation can be significantly higher due to• higher transition probabilities• extra load on CLK
} PDN starts to work as soon as the input signals exceed VTn, so set VM, VIH and VIL all equal to VTn
• low noise margin (NML)} Needs a precharge/evaluate clock
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200814/71
Dynamic CMOS Logic
} Leakage Sources} Subthreshold conduction} Transistors can’t abruptly turn
ON or OFF} Reverse-biased PN junction
diode current• Is depends on doping levels And area
and perimeter of diffusion regions, typically < 1 fA/µm2
} Gate Leakage• Carriers may tunnel thorough very thin
gate oxides• Negligible for older processes
VDD
0 0.3 0.6 0.9 1.2 1.5 1.8
J G)
A/cm
2
10-9
10-6
10-3
100
103
106
109
tox
0. 6 nm0. 8 nm
1. 0 nm1. 2 nm
1. 5 nm
1. 9 nm
VDD trend
)
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200815/71
} Leakage Sources} Output settles to an intermediate voltage determined by a resistive
divider of the pull-up and pull-down networks} Once the output drops below the switching threshold of the fan-out
logic gate, the output is interpreted as a low voltage
Dynamic CMOS Logic
-0.5
0.5
1.5
2.5
0 20 40
Time (ms)
Volta
ge (V
)
CLK
Out
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200816/71
Leakage sources
CLK
VOut
Precharge
Evaluate
Dynamic CMOS Logic
} Leakage Sources} Subthreshold leakage is dominant in modern transistors
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200817/71
Dynamic CMOS Logic
} Solution to Charge Leakage
CLCL
Clk
Clk
Me
Mp
A
B
Out
Mkp
Keeper
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200818/71
} Charge Sharing} Charge stored originally on CY is redistributed (shared) over CX
leading to static power consumption by downstream gates and possible circuit malfunction
} When ΔVout = - Vdd (CX / (CX + CY )) the drop in Vout is large enough to be below the switching threshold of the gate it drivescausing a malfunction
B = 0
AY
φ
x
Cx
CY
A
φ
x
Y
Charge sharing noise
= =+Y
x Y ddx Y
CV V VC C
Dynamic CMOS Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200819/71
} Solution to Charge Redistribution } Add secondary precharge transistors (at the cost of
increased area and power)• Typically need to precharge every other node• Secondary precharge transistors should be small because their
diffusion capacitance slows the evaluation (increase delay)• Big load capacitance CY helps as well
B
AY
x
secondaryprechargetransistor
Dynamic CMOS Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200820/71
} Charge Sharing Example} What is the worst case voltage drop on y? (Assume all
inputs are low during precharge and that all internal nodes are initially at 0V)
Dynamic CMOS Logic
y
CLK
CLK
A A
B B B
CC
y = A B C
Ca =15fF
Cc =15fF
Cb =15fF
Cd =10fF
Loadinverter
ab
dc
Cy =50fF
y = A B C
Cd =10fFCd =10fF
Loadinverter
cB
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200821/71
Dynamic CMOS Logic
} Charge Sharing Example
( ) ( )( )( )
a c a c yVout Vdd C C C C C
2.5V 30 30 50 0.94V
∆ = − + + +
= − + = −
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200822/71
Dynamic CMOS Logic
} Backgate Coupling} Susceptible to crosstalk due to
• High impedance of the output node • Capacitive coupling
– Out2 capacitively couples with Out1 through the gate-source and gate-drain capacitances of M4
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200823/71
} Capacitive coupling means Out1 drops significantly so Out2 doesn’t go all the way to ground
Dynamic CMOS Logic
} Backgate Coupling
-1
0
1
2
3
0 2 4 6
Vol
tage
Time, ns
Clk
In
Out1
Out2
Due to backgate
Due to clk feedthrough
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200824/71
Dynamic CMOS Logic
} Clock Feedthrough} A special case of capacitive
coupling between the clock input of the precharge transistor and the dynamic output node due to the gate to drain capacitance
} So voltage of Out can rise above Vdd. The fast rising (and falling edges) of the clock couple to Out
CLCL
Clk
Clk
B
AOut
Mp
Me
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200825/71
-0.5
0.5
1.5
2.5
0 0.5 1
In &Clk
Out
Time, ns
Vol
tage
Clock feedthrough
Clock feedthrough
Dynamic CMOS Logic
} Clock Feedthrough
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200826/71
} Other Effects} Capacitive coupling} Substrate coupling} Minority charge injection} Supply noise (Ground bounce)} Floating output nodes
Dynamic CMOS Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200827/71
} Floating output nodes} Solutions:
• Only connect to gates• Add staticizer to refresh the charge
Dynamic CMOS Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200828/71
} Advantages:} For n inputs, dynamic logic requires
n+2 transistors} have small area, high speed and
compact layouts} Disadvantages:
} Circuit operation is more complex due to the required clock
} The inputs can only change during the precharge phase and must be stable during the evaluate portion of the cycle
} Need Monotonicity• can not be cascaded
Dynamic CMOS Logic
inputsNMOS LogicCircuit
CLKP
CLKN
CLK
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200829/71
} Monotonicity} Dynamic gates require monotonically rising inputs
during evaluation
φ Precharge Evaluate
Y
Precharge
A
Output should rise but does not
violates monotonicity during evaluation
A
φ
Dynamic CMOS Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200830/71
} Monotonicity Woes} Dynamic gates produce monotonically falling outputs during
evaluation} Illegal for one dynamic gate to drive another!
Dynamic CMOS Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200831/71
V
t
Clk
In
Out1
Out2 ∆V
VTn
Only 0 → 1 transitions allowed at inputs!
Dynamic CMOS Logic
} Cascading
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200832/71
} Cascading} Input going from high to low during evaluation
• a is 5V when precharge b = 5V, c = 5V• During evaluation:
– Wanted: bà 0V, cà 5V– But, b takes some time to drop to 0V– Consequently, c may fall to some unknown value
} Solution} NP-CMOS} NORA Logic} Domino logic
Dynamic CMOS Logic
a
cb
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200833/71
Dynamic CMOS Logic
} NP-CMOS} Only 0 → 1 transitions allowed at inputs of PDN } Only 1 → 0 transitions allowed at inputs of PUN
In1
In2 PDNIn3
Me
Mp
Clk
Clk Out1
In4 PUNIn5
Me
MpClk
Clk
Out2(to PDN)
1 11 0
0 00 1
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200834/71
Dynamic CMOS Logic
} NORA Logic} WARNING: Very sensitive to noise!
In1
In2 PDNIn3
Me
Mp
Clk
Clk Out1
In4 PUNIn5
Me
MpClk
Clk
Out2(to PDN)
1 11 0
0 00 1
to otherPDN’s
to otherPUN’s
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200835/71
} An example
Dynamic CMOS Logic
A
Y=AB+C
BC
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200836/71
In1
In2In3
In4
Out
VDD
GNDφ
Dynamic CMOS Logic
} Dynamic 4 Input NAND Gate
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200837/71
In1
In2 PDNIn3
Me
Mp
CLK
CLK
Out
CLCL
} Power Consumption} Power only dissipated when previous Out = 0
Dynamic CMOS Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200838/71
011
001
010
100
OutBA
} Power Consumption} Dynamic Power Consumption is Data Dependent
• Assume signal probabilities (Dynamic 2-input NOR Gate)• PA=1 = 1/2• PB=1 = 1/2• Then transition probability• P1→0 = Pout=0 = ¾
} Switching activity can be higher in dynamic gates!
Dynamic CMOS Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200839/71
} Rules of Thumb} Dynamic logic is best for wide OR/NOR structure (e.g. bit-
lines), providing 50% delay improvement over static CMOS} Dynamic logic consumes 2x power due to its phase activity
(unconditional pre-charging), not counting clock power
Dynamic CMOS Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200840/71
} Notes} No need to implement the complement of the function,
leading to smaller area} We can avoid the long PMOS chains} Handle the charge sharing problem and floating output
nodes} Input transistors should not change from on to off
during evaluation
Dynamic CMOS Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200841/71
Contents
} Introduction} Dynamic CMOS Logic} CMOS Domino Logic} CD Domino Logic} Dynamic CVSL} Sample-Set Differential Logic (SSDL)} Summary
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200842/71
CMOS Domino Logic
} It is an extension of dynamic CMOS gates that allow cascading of stages
} The simple modification entails incorporating a static CMOS inverter at the output of each logic gate
A
W
φ
B C
X Y Z
domino AND
dynamicNAND
staticinverter
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200843/71
} Stage A should be precharged in Φ1 and evaluate inΦ2
} Stage B should be precharged in Φ2 and evaluate in Φ1
CMOS Domino Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200844/71
} During precharge (clk=0), the output node of the dynamic gate is precharged high and the output node of the CMOS inverter is low. Then subsequent stages will be turned off during the precharge phase
} When the clk=1, the output of the driving gate will conditionally discharge, allowing the output of the inverter to conditionally go high. Each connected gate output can then make a transition from low-to-high, in sequence
} There is no restriction on the number of logic stages that can be cascaded provided that all stages can evaluate during one clock pulse
CMOS Domino Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200845/71
n- network
ev
V
1
W
pc
2
X Y
} pc = Φ1 and ev = Φ2
CMOS Domino Logic
cycle
1
2
precharge evaluate
input latchedhere
output latchedhere
pc = 1 ev = 2
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200846/71
} Won’t work! If pc = Φ2 and ev = Φ1
CMOS Domino Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200847/71
CMOS Domino Logic
} Why Domino?} Like falling dominos!
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200848/71
} Produces monotonic outputs
φ Precharge Evaluate
W
Precharge
X
Y
Z
A
φ
B C
φ φ φ
C
AB
W X Y Z =X
ZH H
AW
φ
B C
X Y Z
domino AND
dynamicNAND
staticinverter
CMOS Domino Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200849/71
} Domino Optimizations} Each domino gate triggers next one, like a string of dominos toppling
over} Gates evaluate sequentially but precharge in parallel Thus evaluation
is more critical than precharge} HI-skewed static stages can perform logic} Static inverter can be optimized to match fan-out
S0
D0
S1
D1
S2
D2
S3
D3
φ
S4
D4
S5
D5
S6
D6
S7
D7
φ
YH
CMOS Domino Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200850/71
} Leakage} Dynamic node floats high during evaluation
• Transistors are leaky (IOFF ≠ 0)• Dynamic value will leak away over time• Formerly miliseconds, now nanoseconds!
} Use keeper to hold dynamic node• Must be weak enough not to fight evaluation
A
φH
2
2
1 kX Y
weak keeper
CMOS Domino Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200851/71
} Noise Sensitivity} Dynamic gates are very sensitive to noise
• Inputs: VIH ≈ Vtn• Outputs: floating output susceptible noise
} Noise sources• Capacitive crosstalk• Charge sharing• Power supply noise• Feedthrough noise• And … !
CMOS Domino Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200852/71
CMOS Domino Logic
} Designing with Domino Logic} If all the inputs come from other domino gates, then all the inputs will be low
during the precharge. You don’t need to explicit evaluate transistor} Need to be a little careful. When precharge begins, the first gate’s output must
precharge before the next gate can precharge. Both evaluate and prechargeripple in this scheme. But, if there is already a tall stack, transistor ratioing will let precharge win anyway. (but you waste power until the precharge ripples)
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200853/71
VDD
Clk Mp
Out1
In1
1 0
VDD
Clk Mp
Out2
In2
VDD
Clk Mp
Outn
InnIn3
1 0
0 1 0 1 0 1
1 0 1 0
CMOS Domino Logic
} Footless Domino} The first gate in the chain needs a foot switch
Precharge is rippling – short – circuit current} A solution is to delay the clock for each stage
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200854/71
} Example} During precharge, x, y, z = 1, x, y = 0} During evaluation, x = 0 when a = b = 1} Therefore, z = a b c d
CMOS Domino Logic
a
b
x
c
xy
d
y z
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200855/71
} Advantages:} Large Fan-in, fewer transistors (n+4 transistors, whereas CMOS
requires 2n)} Single clock can be used to precharge and evaluate all stages at the
same time} It is attractive for high-speed circuits} 1.5 – 2x faster than static CMOS} Widely used in high-performance microprocessors
} Disadvantages:} Each logic block must incorporate a separate inverter} Each block performs only non-inverting logic} Monotonicity} Leakage} Charge sharing} Noise
CMOS Domino Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200856/71
} Dual Rail Domino} Domino only performs noninverting
functions• AND, OR but not NAND, NOR, or XOR
} Dual-rail domino solves this problem• Takes true and complementary inputs • Produces true and complementary
outputs
invalid11‘1’01‘0’10
Precharged00Meaningsig_lsig_h
Y_h
f
φ
φ
inputs
Y_l
f
CMOS Domino Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200857/71
} Example AND/NAND} Given A_h, A_l, B_h, B_l} Compute Y_h = A * B, Y_l = ~(A * B)
} Pulldown networks are conduction complements
CMOS Domino Logic
Y_hφ
φ
Y_lA_h
B_hB_lA_l
= A*B= A*B
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200858/71
} Example XOR/XNOR} Sometimes possible to share transistors
Y_hφ
φ
Y_lA_l
B_h
= A xor B
B_l
A_hA_lA_h= A xnor B
CMOS Domino Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200859/71
} Rules of Thumb} Typical domino keepers have W/L = 5-20% of effective width
of evaluate tree} Typical domino output buffers have a beta ratio of ~ 6:1 to
push the switch point higher for fast rise-time
CMOS Domino Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200860/71
Contents
} Introduction} Dynamic CMOS Logic} CMOS Domino Logic} CD Domino Logic} Dynamic CVSL} Sample-Set Differential Logic (SSDL)} Summary
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200861/71
} We noted that dynamic inputs never make 1 to 0 transitions while in evaluation
} Two solutions:} Precharge outputs low using an inverting gate
(standard domino)} Delay the evaluate clock until inputs settle (CD
domino)
CD Domino Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200862/71
} Self-timed dynamic logic family} Consists of a dynamic gate, and an optional
delay element for the clock signal
CD Domino Logic
OR2
clk(i) clk(i+1)delay
Out = a+bMpre
Meval
a b
OR2
clk(i) clk(i+1)delay
Out = a+bMpre
Meval
a b
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200863/71
} Advantages} Uses single-rail circuits, rather than dual-rail for
standard domino} Provides both inverting and non-inverting functions} High-speed, large fan-in NOR and OR circuits
CD Domino Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200864/71
CD Domino Logic
} Delay Matching} CD domino requires delay matching between the
slowest dynamic gate at a level and a delay element} A 20% margin is typically added to the delay of the
fixed delay element to account for PVT variations} Thus, 20% of the speed gain possible with CD domino
is not realized} Average speed gain of (60+20)% is theoretically
possible} Use digitally programmable delay elements
(PDEs) to reduce the margin and attain a speed improvement without affecting the reliability in the presence of variations
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200865/71
} Clocking Scheme} The circuits are fully levelized} The delay element on each level is tuned to the
slowest gate at its level, plus a 20% margin
CD Domino Logic
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200866/71
Contents
} Introduction} Dynamic CMOS Logic} CMOS Domino Logic} CD Domino Logic} Dynamic CVSL} Sample-Set Differential Logic (SSDL)} Summary
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200867/71
} Positive feedback does not exist
Dynamic CVSL
{In }InC
F F
C NMOSLogic Array
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200868/71
Contents
} Introduction} Dynamic CMOS Logic} CMOS Domino Logic} CD Domino Logic} Dynamic CVSL} Sample-Set Differential Logic (SSDL)} Summary
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200869/71
} It is one type of Dynamic CVSL with positive feedback} By this logic the low level output is guaranteed to zero in
evaluation phase
Sample-Set Differential Logic (SSDL)
{In }In
C
F F
C
NMOSLogic Array
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200870/71
Contents
} Introduction} Dynamic CMOS Logic} CMOS Domino Logic} CD Domino Logic} Dynamic CVSL} Sample-Set Differential Logic (SSDL)} Summary
IUST: Digital IC Design LECTURE 10 : Dynamic CMOSLECTURE 10 : Dynamic CMOS Adib Abrishamifar 200871/71
Summary
} This lecture describes many basics CMOS Logic Gates which require clock or other periodic signal for operation
} These circuits rely on the temporary storage of signal values on the (parasitic) capacitance of high impedance nodes