Elsip
Adam Edström CEO
Bengt Edlund Sales Director
February 2013
© Elsip 2012. Elsip non-confidential
What we do
Software Defned Data Management
for Many-core SoC Designs
Solution:DME = Data Management
Engine
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What’s DME ?
Other specific functions
Data Shuffling;Stride Access;Transactional Ordering;Directory of Cache Coherency; Dynamic Memory Allocation
DME
Virtual-to-Physical translation DMA
Synchronization
Distributed Shared Memory private/shared memory
Different Privilege setting
Scalability
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What’s DME?
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Why choose DME?
DME supports centralized shared memory (CM) and distributed shared memory (DSM).
For medium and large system, we prefer to use DSM structures, since centralized
memory has already become a bottleneck. Memories are preferrably distributed,
featuring good scalability and less delay of memory access.
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Why choose DME
Processor 1
Network-on-Chip (NoC)
DDR Memory
DDR controllerCustom IP
Processor2
CacheCache
Memory
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Why choose DME
Processor1
Network-on-Chip (NoC)
DDR Memory
DDR controllerCustom IP
NI modules in DME are designed to support Standard bus interface, e.g. AHB,APB,AXI, OCP
Processor2
CacheCache
DME P1 M2
NI
Interface
DME can perform as a bridge connecting different IPs with Network
DME P1 M4
NI
Interface
DME P1 M0
NI
DDR-InterfaceDME P1 M2
NI
Interface
We support:1. common bus protocol, easy to integrate into
existing system;2. configurable for different
data formats;
Local Memory
LocalMemory
(Local Memory)
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DME Product
DME comes in three flavours
P1 M0 – DME Light – Small footprint, low power, for memory access and similar standard tasks
P1 M2 – DME Flex – Programmable, fully featured for maximum flexibility and customization
P1 M4 – DME Flex Plus – Programmable, fully featured, with maximum performance
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DME Product
IP-InterfaceInterconnect-
InterfaceIP Interconnect
DME
Transaction Scheduler
Memory Interface Crossbar
Local Memory Local Memory Local Memory Local Memory
DME P1 M0 – DME Light
Feature list:
1.DSM(distributed shared memory)
2.Private|Shared division 3.Synchronization
4.Privilege level setting (3/2013)
5.IP interface support (AHB,APB) (4/2013) 6.Interconnection interface support (AHB,APB)
(4/2013)
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DME Product
DME P1 M2
Transaction Scheduler
M ini-processor
M ini-processor
M emory Interface Crossbar
Local M emory
Local M emory
Bypass path
Interconnect Interface
CPU InterfaceCPU Interconnect
Data Management EngineData Management Engine
Feature list:
1.DSM(distributed shared memory)
2.Private|Shared division
3.V2P
4.Synchronization
5.Privilege level setting (3/2013)
6.IP interface support (AHB,APB) (4/2013) 7.Interconnection interface support (AHB,APB)
(4/2013)
8.DMA-1, DMA-2 (3/2013)
9.Message passing (4/2013)
10.micro-programming
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DME Product
DME P1 M4
Transaction Scheduler
M ini -processor
M ini -processor
M ini -processor
M emory Interface Crossbar
Local M emory
Local M emory
Local M emory
Bypass path
Interconnect Interface
CPU InterfaceCPU Interconnect
Data Management EngineData Management Engine
M ini-processor
Local M emory
Feature list:
1.DSM(distributed shared memory)
2.Private|Shared division
3.V2P
4.Synchronization
5.Privilege level setting (3/2013)
6.IP interface support (AHB,APB) (4/2013) 7.Interconnection interface support (AHB,APB)
(4/2013)
8.DMA-1, DMA-2 (3/2013)
9.Message passing (4/2013)
10.micro-programming
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DME Planned Features
Features
AXI Q2 2013
DMA-3 Q2 2013
Striding access Q2 2013
Data shuffling Q2 2013
SystemC Model, SIMICS Model Q3 2013
Transaction ordering support (memory consistency) Q3 2013
Dynamic memory allocation Q4 2013
OCP Q4 2013
Directory based cache coherence On Demand
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DME Configuration Tool
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Application Example: H.264 decoder
P1
MEM
P2
MEM
P3
MEM
ENTROPYITRANS/
DEQUANTINTRA
PREDICTION
3NODES
P7
MEM
P8
MEM
P9
MEM
P4
MEM
P5
MEM
P6
MEM
P10
MEM
P11
MEM
P12
MEM
12NODES
StoreLoad
TaskDistributor P1
PrivateMem
P2 P3 Pn
SharedMem
PrivateMem
SharedMem
PrivateMem
SharedMem
PrivateMem
SharedMem
without DME based on centralized memorywith DME based on distributed shared memory
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Demonstrator Performance
3 6 9 node
Performance(fps)
with DM E
without DM E25
50
75
2430 3125
51
77
6 7 7
13with DM E
without DM E
QCIF(176x144)
CIF(352x288)20
Applications
The DME is useful for many-core SoCs in: Video, signal and network processing Cloud computing Industrial automation Set-top boxes Scientific computing Solid state disks Other high-end embedded applications
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DME Features
Note: Perceived value is based on early customer input, and is application dependent.
Evaluating the DME
For evaluation of the DME, Elsip offers: Introduction Booklet DME Application Development Package, with API libraries C++ Model SIMICS Model Compiled IP Model User manual Demonstrator On-site and off-site support
Roadmap
Looking into the future, other IP we’re working on include:
Packet- and Circuit-switched NoCs (Circuit-switched can be faster than packet-switched for telecom/datacom applications)
DRRA - Dynamically Reconfgurable Resource Array (reconfgurable on bus level, better silicon usage than FPGA)
The founders
Axel Jantsch, CTO. Professor, KTH Electronic Systems since 2002. 20+ years of research, primarily within NoC and SoC. 200+ scientific papers published. Visiting professor of Fudan University in PRC and Cantabria University in Spain
Ahmed Hemani. Professor, KTH, focus on high-level system integration, design automation, NoC, asynchronous circuit, configurable system. Industrial experience from NSC, NXP/Philips, ABB, Ericsson, Newlogic, Synthesia and Spirea (co-founder).
Zhonghai Lu: Professor, KTH, expert in SoC and NoC. Reviewer of 14 international periodicals. Principal investigator of Intel, dealing with future nuclear processor chip frame.
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Contact
Sales Director Bengt EdlundMail: [email protected]: +46 708 722 800
CEO Adam EdströmMail: [email protected] +46 702 579 734
Address: c/o SICS, PO Box 1263, SE16429, Kista, Sweden
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Some ELSIP Milestones
• Founded by professors Axel Jantsch, Ahmed Hemani and Zhonghai Lu at the Royal Institute of Technology in Stockholm 2011
• Received initial funding from Vinnova• Commercial launch when Adam Edström (CEO) and
Bengt Edlund (Sales Dir) joined the company Sept 2012• Established subsidiary Memcom in Shanghai March
2012, PRC, with Zhonghai Lu as CTO and Zhuo Zou as CEO. Received initial funding from Wuxi government.
• Cooperation with Fudan-Wuxi Institute, Shanghai, PRC• Selected by SICS, the Swedish Institute of Computer
Science, as member of SICS Startup Accelerator23