Understanding OpAmp stability intuitively and with SPICE simulations
Cleveland Tech Day
September 10, 2019
Marek Lis, Senior Analog Applications Engineer
1
Stability – P1TI Precision Labs – Op Amps
2
3
Op Amp Stability Issue
Vcc
Vcc
Vcc 5
+
-
+
U1 OPA333
CLoad 1u
R1
100k
R2
100k
VREF
T
Time (s)
0.00 500.00u 1.00m
Voltag
e (V
)
0.00
2.50
5.00 T
Time (s)
0.00 500.00u 1.00m
VR
EF (V
)
0.00
2.50
5.00
Desired Measured
4
Simplified Cause of Op Amp Stability Issues
Issues happen because of too much delay from output to feedback!
V-
V+
R4 499k R5 499k
C4
25p
+
Vin
Vfb
+
-
+U2 OPA333
R6 100C3
47n
Vopa
T
Time (s)
0 125u 250u
Vopa
-2.5
0.0
2.5
Vfb
-750m
0
750m
Vin
-10m
0
ab
30p
V-
V+
R4 499k R5 499k
C4
25p
+
Vin
Vfb
+
-
+U2 OPA333
R6 100
C3
47n
Vopa
5
Delay Happens in Many Circuits
V-
V+
R1 499k RF 499k
+Vin
Vfb
Vopa
Ro 100
C_Load 47n
Vout
Cst
ray
15p
Cin 1
5p
-
+
OPA333
30p
6
Circuits with Possible Stability Issues
Output Capacitive Loads
Input Capacitance and Large Value Resistors
Transimpedance Amplifiers
Reference Buffers Cable/Shield Drive MOSFET Gate Drive
Large Value Resistors for Low-Power Circuits
-
+
IO P2
R3 4 9 9 kR4 4 9 9 k
+
V G 2
Cin 2 5 p V o u t
-
+
O PA
Cin 1 u
C1 1 u
C2 1 u
V IN 5V in
T e m p
G ND
V o u t
T r im
U1 REF5 0 2 5
C3 1 0 u
A DC_ V REF
C4 1 0 0 n
-
+
O PA
RL 2 5 0
Rf 2 0 kR g 1 k
+
V in
-
+
O PA
C_ Ca b le 1 0 nV o u t
V REF 2 .5
V REF
S h ie ld e d C a b le
-
+
O PA
V Re f 2 .5
R1 2 0 k
R2 2 0 k
V in 1 0
V Re g
Q 1
RL 2 0 0
Transient SuppressionV +
-
+
O PA
Rf 4 9 kRg 4 .9 9 M
Cd 2 0 0 p V o u t
+V in
D1
D2TV S
V o
Rf 1 M
Rd 4 .9 9 G Cd 1 0 p-
+
O PA
Id
P ho to d io d e M o d e l
Identify Stability Issues in the Lab
7
• Suggested Tools:– Oscilloscope
– Signal Generator
• Other Useful Tools:– Gain / Phase Analyzer
– Network / Spectrum Analyzer
• Oscilloscope – Time Domain Analysis:– Oscillations
– Overshoot and Ringing
– Unstable DC Voltages
– High Distortion
Identify Stability Issues in the Lab
8
Output Response to Square Wave Input
Output Response to Step Input
Sustained Output Oscillation with DC Input
Identify Stability Issues in the Lab
9
• Gain / Phase Analyzer - Frequency Domain:
- Peaking, Unexpected Gains, Rapid Phase Shifts Simulated Measured
T
Gain
(dB)
-60.00
-40.00
-20.00
0.00
20.00
Frequency (Hz)
1k 10k 100k 1M 10M
Phase
[deg]
-180.00
-90.00
0.00
T
Time (s)
0.00 2.50m 5.00m
Out
put
2.49
2.50
2.51
Vin Vload Vopa
Solving Op Amp Stability Issues
10
T
Time (s)
0.00 500.00u 1.00m
Vol
tage
(V)
1.81
2.34
2.88
Vcc
Vcc 5
+
-
+
U1 OPA333
CLoad 1u
VREF
+
Vin
Vcc
Vcc 5CLoad 1u
R3 499
R4 49k
C1 22n
Vopa
+
Vin
VloadR1
100k+
-
+U1 OPA333
Vcc
Vcc 5
CLoad 1u
R3 499
Vopa
+
Vin
R1
100k
+
-
+U1 OPA333 Vload
T
Time (s)
0.00 2.50m 5.00m
Out
put
2.50
2.51
2.53
Vin Vload Vopa
Riso 499
Riso 499
Bode Plots – Pole
11
10
Pole Location = fP (Cutoff Freq)
Magnitude (f < fP) = Gdc (e.g. 100dB)
Magnitude (f = fP) = -3dB
Magnitude (f > fP) = -20dB/Decade
Phase (f = fP) = -45°
Phase (0.1fP < f < 10fP) = -45°/Decade
Phase (f > 10fP) = -90°
Phase (f < 0.1fP) = 0°
Gv/v =Vout
Vin=
Gdc
𝑖f
fP+ 1
As a complex number
Gv/v =Vout
Vin=
Gdc
ffP
2
+ 1
Magnitude
Θ = − tan−1f
fP Phase
GdB = 20Log Gv v⁄ Magnitude in dB
Bode Plots – Zero
12
10
Zero Location = fZ
Magnitude (f < fZ) = 0dB
Magnitude (f = fZ) = +3dB
Magnitude (f > fZ) = +20dB/Decade
Phase (f = fZ) = +45°
Phase (0.1fZ < f < 10fZ) = +45°/Decade
Phase (f > 10fZ) = +90°
Phase (f < 0.1fZ) = 0°
Gv/v =Vout
Vin= Gdc 𝑖
f
fZ+ 1
As a complex number
Gv/v =Vout
Vin= Gdc
f
fZ
2
+ 1 Magnitude
Θ = tan−1f
fZ Phase
GdB = 20Log Gv v⁄ Magnitude in dB
Op Amp Open Loop Model
13
Op Amp Closed Loop Model
14
Aol = Open loop Gain
β = Feedback Factor = Vfb
Vout=
R1
R1 + Rf
Acl = Closed Loop Gain =Aol
1 + Aol β
Aol β = Loop Gain
Acl = limAol β→∞
Aol
1 + Aol β=
1
β= 1 +
Rf
R1
When is an Amplifier Unstable?
15
AOLβ = -1 when the phase at VFB has shifted 180⁰ relative to Vin
• A circuit is unstable when AOLβ = -1
• AOLβ = -1 sets the denominator of ACL = 0
• AOLβ = -1 when AOLβ(dB) = 0dB and
phase shift(AOLβ) = 180°
• Phase shift is relative to the DC phase
Phase Margin (PM)How close the system is to a 180° phase shift in AOLβ• PM = Phase(AOLβ) when Gain(AOLβ) = 0dB• Ex: 10° phase margin = 170° phase shift in AOLβ
𝐂𝐋𝐎𝐋
𝐎𝐋
Loop Gain Magnitude – AOLβ
16
1
β=
V
V=
R
R+ 1 = 10 V V⁄
1
βdB = 20log 10 = 20dB
AOL
1/β
AOLβ
Loop gain in dB:
20 log A β = 20 log A − 20 log1
βA β dB = A (dB) −
1
β(dB)
Note: A β dB = 0dB when
A and1
βintersect
fC
Loop Gain Phase – Phase(AOLβ)
17
1
β=
𝑍
𝑍+ 1
C1 introduces a zero in 1
β
At DC the capacitor is open, so gain = 10V/V. At high frequency the capacitor causes Z1 to decrease, so gain increases by +20dB/decade
Phase Margin
18
Rule of thumb:Phase margin > 45° is required for optimal stability!
Phase margin < 45° is considered “marginally stable.”This does not ensure a robust design over process variation.
Rate of Closure – Unstable Example
19
Rate of Closure = Slope A − Slope1
β
Rate of Closure = −20dB − (+20dB) = 40dB
Unstable because rate of closure > 20dB!
1
β=
V
V= 10
f
f+ 1
1/β(dB) = 20dB at DC, then increases by +20dB/decade afterthe zero frequency
Rule of thumb:Rate of closure = 20dB is required for optimal stability!
Rate of Closure – Stable Example
20
Rate of Closure = Slope A − Slope1
β
Rate of Closure = −20dB − 0dB = 20dB
Stable because rate of closure = 20dB!
1
β=
V
V=
R
R+ 1 = 10 V V⁄
1
βdB = 20log 10 = 20dB
Rule of thumb:Rate of closure = 20dB is required for optimal stability!
Rate of Closure (ROC) and Phase Margin
21
ROC(dB/decade)
Phase Margin (°)
20 45 < PM < 90
20 < ROC < 40 45
40 0 < PM < 45
Indirect Phase Margin Measurements
22
Time Domain Percent Overshoot AC Gain/Phase AC Peaking
Phase Margin can be measured indirectly on closed-loop circuits!
T
Ga
in (
dB
)
-30.00
-20.00
-10.00
0.00
10.00
Frequency (Hz)
100.00k 1.00M 10.00MP
ha
se [
de
g]
-270.00
-180.00
-90.00
0.00
T
Time (s)
2.00u 3.50u 5.00u
Vol
tage
(V
)
0.00
3.75m
7.50m
11.25m
15.00m
Indirect Phase Margin Measurements
23
T
Time (s)
2.00u 3.50u
Volta
ge (V)
0.00
2.50m
5.00m
7.50m
10.00m
12.50m
15.00m14.3mV
%Overshoot =14.3mV − 10mV
10mV∗ 100% = 𝟒𝟑%
43% overshoot 29° phase margin
Indirect Phase Margin Measurements
24
T
Frequency (Hz)
100.00k 1.00M 10.00M
Gai
n (d
B)
-30.00
-20.00
-10.00
0.00
10.00
6dB
6dB AC peaking 29° phase margin
AC peaking = 6dB − 0dB = 𝟔𝐝𝐁
Multiple-Choice Quiz
25
What are some possible signs of an unstable op amp circuit? a) oscillations
b) large overshoot and ringing
c) unpredictable or unexpected response
d) all of the above
Many common circuits inadvertently cause delay in the feedback network, resulting in stability issues.a) true
b) false
Multiple-Choice Quiz
26
Which of these is not a cause of amplifier instability? a) capacitance on the amplifier’s output to GND
b) capacitance on the amplifier’s inverting input
c) large value feedback resistors
d) low valued resistors on the amplifier’s output to GND
Which common application is most likely to have a stability issue?a) photodiode transimpedance amplifier
b) low-noise gain stage
c) summing amplifier
d) integrator
Multiple-Choice Quiz
27
Amplifiers with stability problems are __________________? a) only sensitive to transients on the input
b) sensitive to transients on the input, output, and power supplies
Amplifiers with DC inputs (eg. reference buffer) will not have stability issues.a) true
b) false
Multiple-Choice Quiz
28
• Which of the following is a common method for stability testing? a) apply a sinusoidal input signal, monitor the amplifier output with an oscilloscope
b) apply a square wave input signal, monitor the amplifier output with an oscilloscope
c) apply a triangle wave input signal, monitor the amplifier output with an oscilloscope
• Which of these is not a sign of stability issues in closed loop gain/phase analyzer measurements?a) steep magnitude roll-offs
b) rapid phase shifts
c) unexpected gains
d) AC gain peaking
QuizWhich one of these AOL and 1/β curves is unstable?
QuizWhich one of these AOL and 1/β curves is unstable?
QuizFind the phase margin of each system according to the % overshoot.
0102030405060708090
0 20 40 60 80 100
Phas
e Mar
gin (d
eg)
Percentage Overshoot (%)
Phase margin vs Percentage Overshoot
0102030405060708090
0 20 40 60 80 100Ph
ase M
argin
(deg
)Percentage Overshoot (%)
Phase margin vs Percentage Overshoot
%Overshoot =16.4mV − 10mV
20mV∗ 100% = 𝟑𝟐% %Overshoot =
19.6mV − 10mV
20mV∗ 100% = 𝟒𝟖%
38° phase margin 25° phase margin
32
0
10
20
30
40
50
60
70
0 5 10 15 20
Phas
e Mar
gin (d
eg)
ac Peaking (dB)
Phase Margin vs ac Peaking
0
10
20
30
40
50
60
70
0 5 10 15 20
Phas
e Mar
gin (d
eg)
ac Peaking (dB)
Phase Margin vs ac Peaking
QuizFind the phase margin of each system according to the AC peaking.
35° phase margin
4.4dB peaking
12° phase margin
~14dB peaking
33
QuizFind the phase margin of each system according to the Bode plot.
45° phase margin ~15° phase margin
Stability – P2TI Precision Labs – Op Amps
34
Simulating Open-Loop Circuits
35
No DC biasing produces erroneous results!
Wrong open loop response
Output saturated
V-
V+
V- V+
Vo
R2 1kR1 1k
Vfb
V1 -15 V2 15
-
+ +3
2
6
74
OP AMP
+
Vin
R3
10k
24.99nV
14.44V
Simulating Open-Loop Circuits
36
DC: closed loop needed for SPICE operationAC: open loop needed for stability analysisDC
AC
DC+ACV-
V+
Vo
R2 1kR1 1k
+
Vin
Vfb
C1
L1
-
+ +3
2
6
74
OP AMP
R6
10k
100uV
200uV
V-
V+
Vo
R2 1kR1 1k
+
Vin
Vfb
C1
L1
-
+ +3
2
6
74
OP AMP
R7
10k
V-
V+
Vo
R2 1kR1 1k
+
VG1
Vfb
-
+ +3
2
6
74
OP AMP
L1 1T
C1 1T
R5
10k
RL
R L
RL
Standard Open-Loop SPICE Configuration
37
We need an open-loop circuit (no feedback) to generate open-loop gain (AOL), 1/β, and loop gain (AOLβ) curves
AOL_LOADED = Vo / Vfb1/β = 1 / Vfb
AOLβ = Vo
V-
V+
Vo
R2 1kR1 1k
+
VG1
Vfb
-
+ +3
2
6
74
OP AMP
L1 1T
C1 1TR5
10k
AOL
AOLβ
1/β
Check DC Operating Point
38
V-
V+
Vo
R2 1kR1 1k
+
VG1
Vfb
-
+ +3
2
67
4
OP AMP
L1 1T
C1 1T
R5
10k
C3 1n
100uV
200uV
Click Analysis DC Analysis Calculate Nodal Voltages
Generating Open-Loop Curves
39
Run an AC transfer characteristic analysis over the appropriate frequency range:Click Analysis AC Analysis AC Transfer Characteristic
Generating Open-Loop Curves
40
Click the “Post-Processor” button to add the desired curves
Generating Open-Loop Curves
41
Perform math on the existing curves to create the new curves:
AOL = Vo / Vfb1/β = 1/VfbAOLβ = Vo
Generating Open-Loop Curves
42
Unformatted results with all curves:
Generating Open-Loop Curves
43
Use a cursor to determine the frequency where Aolβ = 0dB, fC, and place legend to show corresponding magnitudes and phases
Phase Margin = Aol*βPhase @ fC
fC
Why Do Capacitive Loads Cause Instability?
44
45
Simulate the Effects of Output CapacitanceRun open-loop analysis on buffer circuit with capacitive load
V-
V+
V- V+
+
Vin
-
+ +3
2
6
74
OP AMP
L1 1T
C1 1T
V1 -15 V2 15
CLoad 10n
Vfb
Vo
1/β
AOL_LOADED
AOLβ
ROC = 40dB/dec
Phase Margin = 4°
fC
Pole
Capacitive Loads – Stability Theory
V-
V+
Vo
+
Vin
CLoad 10n
Vfb
-
+
-
+
Aol 1M
Ro 100
V-
V+
Vo
+
Vin
-
+ +3
2
6
74
OP AMP
L1 1T
C1 1T
CLoad 10n
Vfb
+
Aol
Ro 100
Vo
CLoad 10n
46
(AOL_LOADED)
(AOL_LOADED)
Capacitive Loads – Stability Theory
+
Vin
Ro 100
Vo
CLoad 10n
47
V
V(s) =
1
1 + s ∗ Ro ∗ CTransfer Function:
f =1
2 ∗ π ∗ Ro ∗ CPole Equation:
Capacitive Loads – Stability Theory
X
AOL (from data sheet) AOL Load
Loaded AOL =
48
Compensation Method 1: RISO
V+
V-
VLoad
+
Vin
-
+ +3
2
67
4
OP AMPCLoad 10n
Riso 108
49
Vo
Method 1: RISO – ResultsTheory: Adds a zero to cancel the pole in loaded AOL
V-
V+
+
Vin
-
+ +3
2
6
74
OP AMP
L1 1T
C1 1T
CLoad 10n
Vfb
Riso 108
Vo
50
1/β
AOL_LOADED
AOLβ
ROC = 20dB/dec
Phase Margin = 64°
PoleZero
fC
V-
V+
Vo+
Vin
-
+ +3
2
6
74
OP AMP
L1 1T
C1 1T
CLoad 10n
Vfb
Riso 108
Method 1: RISO – Theory
V-
V+
Vo
+
Vin
CLoad 10n
Vfb
-
+
-
+
Aol 1M
Ro 100
Riso 108
+
Aol
Ro 100
Vo
CLoad 10n
Riso 108
51
(AOL_LOADED)
(AOL_LOADED)
Resistor Divider Analogy
52
+
Vin
R1 100
R2 100
Vo +
Aol
Ro 100
Vo
CLoad 10n
Riso 108
Zero: RISO & CLOAD
Pole: RO, RISO, and CLOAD
Z1
Z2Vin
V
V=
R
R + RV
V=
Z
Z + Z
V
V=
R +1
s ∗ C
R +1
s ∗ C+ R
V
V=
1 + s ∗ R ∗ C
1 + s ∗ R + R ∗ C
Method 1: RISO – Theory
X
AOL (from data sheet) AOL Load
Loaded AOL =
53
Method 1: RISO – Theory+
Vin
Ro 100
Vo
CLoad 10n
Riso 108
54
V
Vs =
1 + s ∗ R ∗ C
1 + s ∗ R + R ∗ C
f =1
2 ∗ π ∗ R ∗ C
f =1
2 ∗ π ∗ (R + R ) ∗ C
Transfer Function:
Zero Equation:
Pole Equation:
Method 1: RISO – Design
Design Steps:1.) Find the zero frequency, fZERO, where AOL_Loaded = 20 dB2.) Calculate Riso to set the zero at fZERO
This will yield between 60° and 90° degrees of phase margin
55
R =1
2 ∗ π ∗ f ∗ C
R =1
2 ∗ π ∗ 146.5kHz ∗ 10nF
R = 𝟏𝟎𝟖𝛀
RISO Equation: AOL_LOADED
1/β
fC
fZERO = 146.5kHz
20dB
1/β
AOL_LOADED
AOLβ
ROC = 20dB/dec
PoleZero
fC
Method 1: RISO – Design Summary
56
V-
V+
-
++3
2
6
74
OP AMP
+
Vin
Riso 108
Cload 10n
Vload
Vo
Phase Margin= 64°
Unstable vs. Stable Transient Results
57
No compensation - Unstable
Riso compensation - Stable
T
Time (s)
0.00 10.00u 20.00u 30.00u
Volta
ge (V)
0.00
5.00m
10.00m
15.00m
20.00m
Vin Vo
T
Time (s)
0.00 10.00u 20.00u 30.00u
Volta
ge
(V)
0.00
5.00m
10.00m
15.00m
20.00m
Vin
Vo
V-
V+
Vo
-
++3
2
6
74
OP AMP
+
Vin C1
10n
Riso 108
SW_Riso
Method 1: RISO – Disadvantage
Disadvantage:Voltage drop across RISO may not be acceptable for certain applications!
V+
V-
Vload
+
Vin
-
+ +3
2
6
74
OP AMPCLoad 10n
Riso 108
Vo
RLoad 250
58
Method 2: RISO + Dual Feedback
59
V-
V+
-
+ +3
2
6
74
OP AMP
+
Vin
Riso 108
Cload 10n
Vload
Vo
C1 470p
R1 15k
Rload 250
Cf
Rf
Method 2: RISO + Dual Feedback – TheoryDC Circuit AC Circuit
V+
V-
+
Vin
-
+ +3
2
6
74
OP AMPCLoad 10n
Riso 108
Vo
RF 15k
R2
250
VLoad
CF
Vin 1V
1V
1.43V
CF: OpenRF: Closes the feedback around RISO
VLOAD = VIN
CF: ShortRF >> ZCF, therefore RF is effectively openBehaves like RISO circuit
60
V-
V+
-
++3
2
6
74
OP AMP
+
Vin
Riso 108
Cload 10n
Vload
Vo
Rload 250
RF
CF 470p
Method 2: RISO + Dual Feedback - DesignDesign Steps:1) Set RISO using Method 1: RISO techniques2) Set RF: RF ≥ (RISO * 100)
3) Set CF: ∗ ∗ ∗ ∗
lower values of CF = faster settling, higher overshoot
Rule 3 ensures that the two feedback paths will never create a resonance that would cause instability
61
6 ∗ R ∗ C
C≤ C ≤
10 ∗ R ∗ C
C
R = 108Ω
R ≥ R ∗ 100
R ≥ 10.8kΩ
𝟒𝟐𝟎𝐩𝐅 ≤ C ≤ 𝟕𝟐𝟎𝐩𝐅
1/β
AOL_LOADED
AOLβ
ROC = 20dB/dec
PoleZero
fC
Phase Margin = 66°
𝑅𝐹 ≥ 100 × 𝑅𝑖𝑠𝑜 = 100 × 787Ω = 78.7𝑘Ω
5 × 𝑅𝑖𝑠𝑜 × 𝐶𝐿
𝑅𝐹≤ 𝐶𝐹 ≤
10 × 𝑅𝑖𝑠𝑜 × 𝐶𝐿
𝑅𝐹
𝑅𝐹 ≥ 100 × 𝑅𝑖𝑠𝑜 = 100 × 787Ω = 78
5 × 𝑅𝑖𝑠𝑜 × 𝐶𝐿
𝑅𝐹≤ 𝐶𝐹 ≤
10 × 𝑅𝑖𝑠𝑜 × 𝐶𝐿
𝑅𝐹
Method 2: RISO + Dual Feedback - Results
62
V+
V-
+
Vin
-
+ +3
2
6
74
OP AMPCLoad 10n
Riso 108
Vo
R1 15k
R2
250
C1 470p
VLoad
• VLOAD matches VIN – No voltage divider error!• This topology has some limitations on settling time and capacitive load range
T
Time (s)
0.00 2.50m 5.00m
Out
put
2.49
2.50
2.51
Vin Vload Vopa
Summary – Solving Op Amp Stability
63
T
Time (s)
0.00 500.00u 1.00m
Vol
tage
(V)
1.81
2.34
2.88
Vcc
Vcc 5
+
-
+
U1 OPA333
CLoad 1u
VREF
+
Vin
Vcc
Vcc 5CLoad 1u
R3 499
R4 49k
C1 22n
Vopa
+
Vin
VloadR1
100k+
-
+U1 OPA333
Vcc
Vcc 5
CLoad 1u
R3 499
Vopa
+
Vin
R1
100k
+
-
+U1 OPA333 Vload
T
Time (s)
0.00 2.50m 5.00m
Out
put
2.50
2.51
2.53
Vin Vload Vopa
Riso 499
Riso 499