A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
Cover Sheet
Custom
1 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Schematics Document
REV:0.3
2009-03-15
Mobile AMD S1G3 CPU with ATI
RS880M(NB) & SB710(SB) core logic
Compal confidential
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
Block Diagram
Custom
2 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Compal Confidential
Thermal Sensor
ADM1032ARMZ
Fan conn
AMD S1G3 CPU
638-PIN uFCPGA 638
Mini-Card*2
16X16
ATI RS880M
Power On/Off CKT.
LPC BUS
DC/DC Interface CKT.
Page 4, 5, 6, 7
Page 10, 11, 12, 13, 14
Page 8, 9
Page 19, 20, 21, 22, 23
Page 24
Page 24
SATA ODD Connector
Page 25
Page 19
RTC CKT.
ATI SB710
Power OK CKT.
Touch Pad CONN. Int.KBD
KBC
Realtek
8102E(10/100M)
RJ45/11 CONN
PCI-E BUS*5
BANK 0, 1, 2, 3
LED
DDR2-SO-DIMM X2
SATA HDD Connector
SATA Master-1
SATA Slave
A-Link Express II
4X PCI-E
Page 26
Page 26
Page 24Multi-Bay HDD/ODD Option Connector
SATA Slave
SATA Master-2
Page 31
e-SATA Connector
Consumer AMD 14" UMA - Ripley 2.0 (NBW20)
Page 17
Express Card
Page 26WLAN & WWAN
Page 28 Page 29
Page 31
Page 31
P41
Page 33
Page 33
Page 36
CRT
LVDS Panel
Interface
Page 16
Codec_IDT9271B7Audio CKT
AMP & Audio JackTPA6017A2
USB conn x2
USB2.0 X12
Azalia (HDA I/F)
BT Conn
Mini-Card WWAN
Page 6
Page 4
HDMIPage 18
Clock Generator
SLG8SP626VTRPage 15
72QFN
ENE KB926-C0
Page 34
P35
P35
Page 12
Side-Port DDR2 SDRAM
1024Mbits(64Mbx16)
DDR2 400MHz
Hyper Transport Link
Page 25
SPI ROMMX25L1605
AM2C-12GPage 32
Page 17
USB WebCam
Page 34
Consumer IRSPI
Docking CONN.
*RJ-45(LED*2)
*RJ-11(Pass Through)
*CRT
*COMPOSITE Video Out
*S-VIDEO OUT
*SPDIF
*Headphone/Line Out L/R
*Stereo Mic L/R
*Volume Control
*Consumer IR
*USB x1
*DC JACK
page 35Module
FingerPrinter AES1610
USBx1
Module
New Module
Page 35
DDR2 800MHz 1.8V
Dual Channel
Page 34MDC V1.5 daughter board
Accelerometer
ST LIS302DLTRPage 30
Page 27
CardReader
JMicron
JMB385-LGEZ0A
daughter board
Page 31USB conn x1
Page 27
CardReader Socket
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
Notes List
Custom
3 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Voltage Rails O MEANS ON X MEANS OFF
O
O
X
+0.9V
S3
+3VS
X
X
+3VALW
+5VS
S1
O
+2.5VS
+CPU_CORE
OO
OO
X
X X
+VCCP
powerplane
O
O
O
O
O
X
S5 S4/ Battery only
X X X
+B
State
+1.5VS
+1.8V
S5 S4/AC & Batterydon't exist
S5 S4/AC
+5VALW
S0
O
O
Symbol Note :
: means Digital Ground
: means Analog Ground
SERIAL SENSOR
SMB_EC_CK2
SOURCE
KB926
INVERTER BATT EEPROM
THERMAL
SODIMM CLK CHIP
SMBUS Control Table
MINI CARD
SMB_EC_DA2
SMB_EC_CK1
SMB_EC_DA1
KB926
LCDADM1032
X
X X X
X
X X
X
X
X X
X
V V
V
1 0 1 0 0 1 0 0A4
I2C / SMBUS ADDRESSING
1 0 1 0 0 0 0 0
D2
A0
CLOCK GENERATOR (EXT.)
HEX
DDR SO-DIMM 1
ADDRESS
DDR SO-DIMM 0
1 1 0 1 0 0 1 0
DEVICE
+VGA_CORE
+1.8VS
+0.9VGA
+1.2VS
HEX
98H
HEX
16H
EC SM Bus1 address
Device
A0H 1010 000X b
Address Address
EC SM Bus2 address
Device
1001 100X b0001 011X bSmart Battery
24C16
CPU
9AH 1001 101X bADI1032-2 CPU
L Layout Notes
Slot 2I / IICPU &
VI2C_CLK
I2C_DATARS780M X X X X X X X
V VSCL0
SDA0SB700 X X X X X
HDMI
X
X
XDDC_CLK0
DDC_DATA0RS780M X X X X X
DDC_CLK1
DDC_DATA1RS780M X X X X X
X X X V
X X X X
XX
XX XXSDA3 XSB700SCL3
XX
XX XXSDA1SB700
SCL1
XXX X V
X X
XX XXSDA2 XSB700SCL2
XXX X
Please see VGA@ as no install. No support RX780M.
G-Sensor
X
X
X
X
X
X
V
X
X
: Question Area Mark.(Wait check)
"*" as default BOM setting*PA@ : means install when Ripley PA. PR@ : means install when Ripley PR. RM@ : means install when Rachman.*RP@ : means install when Ripley. SIDE@ : means install when SidePort support. @ : means just reserve , no build 45@ : Install when 45 level Assy
VCPU
ADM1032
DAZ=DAZ03Y00201 DAZ=DAZ03Y00101
SB700RS780
PCB for 1.0/1.0a
R3 NB and SB: RS780R3@,SBR3@R1 NB and SB: RS780R1@,SBR1@
DAZ=DAZ03Y00203 DAZ=DAZ03Y00102
PCB for 1.1
For Riply PA-> PA@/RP@/RPZ@ For Rachman UMA-> RM@/PRM@/RMZ@
For Riply PA-> PA@, RP@For Riply PR-> PR@, RP@, PRM@For Rachman UMA-> RM@, PRM@
1.0/1.0a
2.0
RP11@,RM11@:For 1.A PCBRP10@,RM10@:For 1.0 PCB.
For Riply PA-> PA@, RP@,RPZ@For Riply PR-> PR@, RP@, PRM@,RPZ@For Rachman UMA-> RM@, PRM@,RMZ@
1.1
DAZ=DAZ09100102DAZ=DAZ09000102
PCB for 2.0
ZZZ
PCB-Ripley MB
RP10@
ZZZ
PCB-Rachman UMA MB
RM11@
ZZZ
PCB-Rachman UMA MB
RM@ZZZ
PCB-Ripley MB
RP@
ZZZ
PCB-Ripley MB
RP11@
U15
SB700 R1SBR1@
U3
RS780 R1RS780R1@
X76
X76
ZZZ
PCB-Rachman UMA MB
RM10@
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
H_CADIN1
H_CADIN0
H_CADIP3H_CADIN2H_CADIP2
H_CADIP1
H_CADIN3H_CADIP4
H_CADIN5
H_CADIN4H_CADIP5
H_CADIN6
H_CADIN8
H_CADIN7
H_CADIN9
H_CADIP8
H_CADIP6
H_CADIP7
H_CADIN10H_CADIP10
H_CADIN11H_CADIP11
H_CADIP9
H_CADIN13
H_CADIN12
H_CADIP14
H_CADIP12
H_CADIN14
H_CADIP0
H_CADIN15H_CADIP15
H_CADIP13
H_CADON15
H_CADOP13
H_CADON2
H_CADON3
H_CADON9
H_CADON6
H_CADON0
H_CADOP11
H_CADOP8
H_CADOP6
H_CADON13
H_CADOP1
H_CADOP2
H_CADOP4
H_CADOP5
H_CADON12
H_CADON7
H_CADON5
H_CADON10
H_CADON8
H_CADON4
H_CADON1
H_CADOP12
H_CADOP15
H_CADOP9
H_CADOP10
H_CADOP14
H_CADOP7
H_CADOP3
H_CADOP0
H_CADON14
H_CADON11
+VCC_FAN
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CADIP[0..15]
+VLDT_B
H_CADON[0..15] <10>H_CADIN[0..15]<10>
H_CADOP[0..15] <10>
H_CLKIN0<10>
H_CLKIN1<10>H_CLKIP1<10>
H_CTLIN1<10>
H_CLKIP0<10>
H_CTLIP1<10> H_CTLOP1 <10>
H_CLKOP1 <10>
H_CADIP[0..15]<10>
H_CLKOP0 <10>H_CLKON0 <10>
H_CLKON1 <10>
H_CTLON1 <10>
H_CTLOP0 <10>H_CTLON0 <10>H_CTLIN0<10>
H_CTLIP0<10>
FAN_PWM<33>
+1.2V_HT
+1.2V_HT
+5VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
AMD CPU S1G2 HT I/F
Custom
4 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
250 mil
VLDT=500mA
PWM Fan Control circuit
Athlon 64 S1
Processor Socket
Near CPU Socket
VLDT CAP.
If VLDT is connected only on one side, one
4.7uF cap should be added to the island
side.
9/20 SP07000DM00/SP07000EQ00
C14.7U_0805_10V4Z
1
2
HT LINK
JCPUA
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
VLDT_A3D4
VLDT_A2D3
VLDT_A1D2
VLDT_A0D1
VLDT_B3AE5
VLDT_B2AE4
VLDT_B1AE3
VLDT_B0AE2
L0_CADIN_H15N5
L0_CADIN_L15P5
L0_CADIN_H14M3
L0_CADIN_L14M4
L0_CADIN_H13L5
L0_CADIN_L13M5
L0_CADIN_H12K3
L0_CADIN_L12K4
L0_CADIN_H11H3
L0_CADIN_L11H4
L0_CADIN_H10G5
L0_CADIN_L10H5
L0_CADIN_H9F3
L0_CADIN_L9F4
L0_CADIN_H8E5
L0_CADIN_L8F5
L0_CADIN_H7N3
L0_CADIN_L7N2
L0_CADIN_H6L1
L0_CADIN_L6M1
L0_CADIN_H5L3
L0_CADIN_L5L2
L0_CADIN_H4J1
L0_CADIN_L4K1
L0_CADIN_H3G1
L0_CADIN_L3H1
L0_CADIN_H2G3
L0_CADIN_L2G2
L0_CADIN_H1E1
L0_CADIN_L1F1
L0_CADIN_H0E3
L0_CADIN_L0E2
L0_CADOUT_H15T4
L0_CADOUT_L15T3
L0_CADOUT_H14V5
L0_CADOUT_L14U5
L0_CADOUT_H13V4
L0_CADOUT_L13V3
L0_CADOUT_H12Y5
L0_CADOUT_L12W5
L0_CADOUT_H11AB5
L0_CADOUT_L11AA5
L0_CADOUT_H10AB4
L0_CADOUT_L10AB3
L0_CADOUT_H9AD5
L0_CADOUT_L9AC5
L0_CADOUT_H8AD4
L0_CADOUT_L8AD3
L0_CADOUT_H7T1
L0_CADOUT_L7R1
L0_CADOUT_H6U2
L0_CADOUT_L6U3
L0_CADOUT_H5V1
L0_CADOUT_L5U1
L0_CADOUT_H4W2
L0_CADOUT_L4W3
L0_CADOUT_H3AA2
L0_CADOUT_L3AA3
L0_CADOUT_H2AB1
L0_CADOUT_L2AA1
L0_CADOUT_H1AC2
L0_CADOUT_L1AC3
L0_CADOUT_H0AD1
L0_CADOUT_L0AC1
L0_CLKIN_H1J5
L0_CLKIN_L1K5
L0_CLKIN_H0J3
L0_CLKIN_L0J2
L0_CTLIN_H1P3
L0_CTLIN_L1P4
L0_CTLIN_H0N1
L0_CTLIN_L0P1
L0_CLKOUT_H1Y4
L0_CLKOUT_L1Y3
L0_CLKOUT_H0Y1
L0_CLKOUT_L0W1
L0_CTLOUT_H1T5
L0_CTLOUT_L1R5
L0_CTLOUT_H0R2
L0_CTLOUT_L0R3
JP2
ACES_88231-02001CONN@
11
22
GND3
GND4
D1CH751H-40PT_SOD323-2
21
C7 4.7U_0805_10V4Z1 2
S
G
D Q1
SI3456BDV-T1-E3_TSOP6
3
624
51
C90.1U_0402_16V4Z
1
2
C8
4.7U_0805_10V4Z
1
2
C30.22U_0603_16V4Z
1
2
C24.7U_0805_10V4Z
1
2
C5180P_0402_50V8J
1
2
D2
RLZ5.1B_LL34
@
12
C6180P_0402_50V8J
1
2
C40.22U_0603_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+MCH_REF
DDR_B_MA10
DDR_B_MA7
DDR_B_MA1
DDR_B_MA12
DDR_B_MA6
DDR_B_MA11
DDR_B_MA0
DDR_B_MA9
DDR_B_MA15
DDR_B_MA3
DDR_B_MA5
DDR_B_MA8
DDR_B_MA13
DDR_B_MA2
DDR_B_MA4
DDR_CKE1_DIMMB
DDR_B_D0
DDR_CKE0_DIMMB
DDR_B_DQS6DDR_B_DQS#6
DDR_B_DQS2DDR_B_DQS#2
DDR_B_DQS5DDR_B_DQS#5
DDR_B_DQS1DDR_B_DQS#1
DDR_B_DQS4DDR_B_DQS#4
DDR_B_DQS0DDR_B_DQS#0
DDR_B_DQS7DDR_B_DQS#7
DDR_B_DQS3DDR_B_DQS#3
DDR_A_CLK1
DDR_A_CLK#1
DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1
DDR_A_DQS0DDR_A_DQS#0
DDR_A_DQS3DDR_A_DQS#3
DDR_A_DQS2DDR_A_DQS#2
DDR_A_DQS1DDR_A_DQS#1
DDR_A_DQS4DDR_A_DQS#4DDR_A_DQS5DDR_A_DQS#5DDR_A_DQS6DDR_A_DQS#6
DDR_A_DQS#7DDR_A_DQS7
VTT_SENSE
DDR_A_CLK0
DDR_A_CLK#0
+MCH_REF
DDR_B_ODT0DDR_B_ODT1
DDR_A_ODT1DDR_A_ODT0
DDR_B_CLK#0DDR_B_CLK0
DDR_B_CLK1DDR_B_CLK#1DDR_A_CLK#1
DDR_A_CLK#0DDR_A_CLK0
DDR_A_CLK1
DDR_CKE0_DIMMADDR_CKE1_DIMMA
DDR_B_D28
DDR_B_D16
DDR_B_D22
DDR_B_D19
DDR_B_D9
DDR_B_D50
DDR_B_D35
DDR_B_D46
DDR_B_D5
DDR_B_D37
DDR_B_D26
DDR_B_D3
DDR_B_D8
DDR_B_D29
DDR_B_D14
DDR_B_D7
DDR_B_D59
DDR_B_D51
DDR_B_D10
DDR_B_D17
DDR_B_D44
DDR_B_D41
DDR_B_D38
DDR_B_D47
DDR_B_D63
DDR_B_D32
DDR_B_D20
DDR_B_D52
DDR_B_D30
DDR_B_D53
DDR_B_D40
DDR_B_D27
DDR_B_D45
DDR_B_D55DDR_B_D56
DDR_B_D11
DDR_B_D48
DDR_B_D39
DDR_B_D1
DDR_B_D42
DDR_B_D36
DDR_B_D2
DDR_B_D58
DDR_B_D33
DDR_B_D62
DDR_B_D31
DDR_B_D21
DDR_B_D54
DDR_B_D24
DDR_B_D15
DDR_B_D60
DDR_B_D12
DDR_B_D49
DDR_B_D43
DDR_B_D18
DDR_B_D61
DDR_B_D34
DDR_B_D4
DDR_B_DM6
DDR_B_DM4
DDR_B_DM2
DDR_B_DM0
DDR_B_DM5
DDR_B_DM3
DDR_B_DM1
DDR_B_DM7DDR_A_DM6DDR_A_DM5DDR_A_DM4DDR_A_DM3DDR_A_DM2DDR_A_DM1DDR_A_DM0
DDR_A_DM7
DDR_A_D59
DDR_A_D3
DDR_A_D13
DDR_A_D60
DDR_A_D40
DDR_A_D29
DDR_A_D56
DDR_A_D20
DDR_A_D28
DDR_A_D36
DDR_A_D19
DDR_A_D23
DDR_A_D34
DDR_A_D61
DDR_A_D15
DDR_A_D4
DDR_A_D0
DDR_A_D53
DDR_A_D47
DDR_A_D43
DDR_A_D33
DDR_A_D24
DDR_A_D39
DDR_A_D46
DDR_A_D22
DDR_A_D51
DDR_A_D9
DDR_A_D5DDR_A_D6
DDR_A_D54
DDR_A_D8
DDR_A_D31
DDR_A_D7
DDR_A_D50
DDR_A_D57
DDR_A_D12
DDR_A_D21
DDR_A_D26
DDR_A_D63DDR_A_D62
DDR_A_D42
DDR_A_D48
DDR_A_D44
DDR_A_D25
DDR_A_D58
DDR_A_D32
DDR_A_D1
DDR_A_D17
DDR_A_D2
DDR_A_D55
DDR_A_D38
DDR_A_D11DDR_A_D10
DDR_A_D27
DDR_A_D18
DDR_A_D14
DDR_A_D41
DDR_A_D49
DDR_A_D16
DDR_A_D52
DDR_A_D37
DDR_A_D35
DDR_A_D30
DDR_B_D6
DDR_A_D45
DDR_B_RAS#DDR_B_CAS#DDR_B_WE#
DDR_B_BS#0DDR_B_BS#1DDR_B_BS#2
DDR_A_WE#
DDR_B_D25
DDR_A_CAS#DDR_A_RAS#
DDR_B_D23
DDR_B_D57
DDR_B_D13
DDR_A_BS#2DDR_A_BS#1DDR_A_BS#0
DDR_A_MA15
DDR_A_MA12
DDR_A_MA14DDR_A_MA13
DDR_A_MA11DDR_A_MA10
DDR_A_MA6
DDR_A_MA1
DDR_A_MA7
DDR_A_MA2DDR_A_MA3
DDR_A_MA8
DDR_A_MA5DDR_A_MA4
DDR_A_MA9
DDR_A_MA0
DDR_B_MA14
DDR_CS1_DIMMA# DDR_CS0_DIMMB#DDR_CS1_DIMMB#
DDR_CS0_DIMMA#
DDR_CKE1_DIMMB <9>DDR_CKE0_DIMMB <9>
DDR_CS0_DIMMA#<8>DDR_CS1_DIMMA#<8> DDR_CS0_DIMMB# <9>
DDR_CS1_DIMMB# <9>
DDR_B_D[63..0]<9>
DDR_B_DM[7..0]<9> DDR_A_DM[7..0] <8>
DDR_A_D[63..0] <8>
DDR_B_DQS7<9>DDR_B_DQS#7<9>
DDR_B_DQS6<9>
DDR_B_DQS5<9>
DDR_B_DQS4<9>
DDR_B_DQS3<9>
DDR_B_DQS2<9>
DDR_B_DQS1<9>
DDR_B_DQS0<9>
DDR_B_DQS#6<9>
DDR_B_DQS#5<9>
DDR_B_DQS#4<9>
DDR_B_DQS#3<9>
DDR_B_DQS#2<9>
DDR_B_DQS#1<9>
DDR_B_DQS#0<9>
DDR_A_DQS3 <8>
DDR_A_DQS2 <8>
DDR_A_DQS1 <8>
DDR_A_DQS0 <8>
DDR_A_DQS#3 <8>
DDR_A_DQS#2 <8>
DDR_A_DQS#1 <8>
DDR_A_DQS#0 <8>
DDR_A_DQS4 <8>DDR_A_DQS#4 <8>DDR_A_DQS5 <8>DDR_A_DQS#5 <8>DDR_A_DQS6 <8>DDR_A_DQS#6 <8>DDR_A_DQS7 <8>DDR_A_DQS#7 <8>
DDR_B_RAS# <9>DDR_B_CAS# <9>DDR_B_WE# <9>
DDR_B_BS#0 <9>DDR_B_BS#1 <9>DDR_B_BS#2 <9>
DDR_A_RAS#<8>DDR_A_CAS#<8>DDR_A_WE#<8>
DDR_A_BS#0<8>DDR_A_BS#1<8>DDR_A_BS#2<8>
DDR_A_MA[15..0]<8> DDR_B_MA[15..0] <9>
DDR_B_ODT0 <9>DDR_B_ODT1 <9>
DDR_A_ODT0<8>DDR_A_ODT1<8>
DDR_B_CLK0 <9>DDR_B_CLK#0 <9>DDR_B_CLK1 <9>DDR_B_CLK#1 <9>
DDR_A_CLK0<8>DDR_A_CLK#0<8>
DDR_A_CLK1<8>DDR_A_CLK#1<8>
DDR_CKE0_DIMMA<8>DDR_CKE1_DIMMA<8>
+1.8V
+0.9V+0.9V
+1.8V
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
AMD CPU S1G2 DDRII I/F
Custom
5 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH
Athlon 64 S1
Processor
Socket
Athlon 64 S1
Processor Socket
Place them close to CPU within 1"
Processor DDR2 Memory Interface
T1PAD
C111.5P_0402_50V9C
1
2
R2
1K_0402_1%
12
C12
0.1U_0402_16V4Z
1
2
T3PAD
R1
1K_0402_1%
12
T2 PAD
R4 39.2_0402_1%
1 2
MEM:DATAJCPUC
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
MB_DATA63AD11
MB_DATA62AF11
MB_DATA61AF14
MB_DATA60AE14
MB_DATA59Y11
MB_DATA58AB11
MB_DATA57AC12
MB_DATA56AF13
MB_DATA55AF15
MB_DATA54AF16
MB_DATA53AC18
MB_DATA52AF19
MB_DATA51AD14
MB_DATA50AC14
MB_DATA49AE18
MB_DATA48AD18
MB_DATA47AD20
MB_DATA46AC20
MB_DATA45AF23
MB_DATA44AF24
MB_DATA43AF20
MB_DATA42AE20
MB_DATA41AD22
MB_DATA40AC22
MB_DATA39AE25
MB_DATA38AD26
MB_DATA37AA25
MB_DATA36AA26
MB_DATA35AE24
MB_DATA34AD24
MB_DATA33AA23
MB_DATA32AA24
MB_DATA31G24
MB_DATA30G23
MB_DATA29D26
MB_DATA28C26
MB_DATA27G26
MB_DATA26G25
MB_DATA25E24
MB_DATA24E23
MB_DATA23C24
MB_DATA22B24
MB_DATA21C20
MB_DATA20B20
MB_DATA19C25
MB_DATA18D24
MB_DATA17A21
MB_DATA16D20
MB_DATA15D18
MB_DATA14C18
MB_DATA13D14
MB_DATA12C14
MB_DATA11A20
MB_DATA10A19
MB_DATA9A16
MB_DATA8A15
MB_DATA7A13
MB_DATA6D12
MB_DATA5E11
MB_DATA4G11
MB_DATA3B14
MB_DATA2A14
MB_DATA1A11
MB_DATA0C11
MA_DATA63AA12
MA_DATA62AB12
MA_DATA61AA14
MA_DATA60AB14
MA_DATA59W11
MA_DATA58Y12
MA_DATA57AD13
MA_DATA56AB13
MA_DATA55AD15
MA_DATA54AB15
MA_DATA53AB17
MA_DATA52Y17
MA_DATA51Y14
MA_DATA50W14
MA_DATA49W16
MA_DATA48AD17
MA_DATA47Y18
MA_DATA46AD19
MA_DATA45AD21
MA_DATA44AB21
MA_DATA43AB18
MA_DATA42AA18
MA_DATA41AA20
MA_DATA40Y20
MA_DATA39AA22
MA_DATA38Y22
MA_DATA37W21
MA_DATA36W22
MA_DATA35AA21
MA_DATA34AB22
MA_DATA33AB24
MA_DATA32Y24
MA_DATA31H22
MA_DATA30H20
MA_DATA29E22
MA_DATA28E21
MA_DATA27J19
MA_DATA26H24
MA_DATA25F22
MA_DATA24F20
MA_DATA23C23
MA_DATA22B22
MA_DATA21F18
MA_DATA20E18
MA_DATA19E20
MA_DATA18D22
MA_DATA17C19
MA_DATA16G18
MA_DATA15G17
MA_DATA14C17
MA_DATA13F14
MA_DATA12E14
MA_DATA11H17
MA_DATA10E17
MA_DATA9E15
MA_DATA8H15
MA_DATA7E13
MA_DATA6C13
MA_DATA5H12
MA_DATA4H11
MA_DATA3G14
MA_DATA2H14
MA_DATA1F12
MA_DATA0G12
MB_DM7AD12
MB_DM6AC16
MB_DM5AE22
MB_DM4AB26
MB_DM3E25
MB_DM2A22
MB_DM1B16
MB_DM0A12
MB_DQS_H7AF12
MB_DQS_L7AE12
MB_DQS_H6AE16
MB_DQS_L6AD16
MB_DQS_H5AF21
MB_DQS_L5AF22
MB_DQS_H4AC25
MB_DQS_L4AC26
MB_DQS_H3F26
MB_DQS_L3E26
MB_DQS_H2A24
MB_DQS_L2A23
MB_DQS_H1D16
MB_DQS_L1C16
MB_DQS_H0C12
MB_DQS_L0B12
MA_DM7Y13
MA_DM6AB16
MA_DM5Y19
MA_DM4AC24
MA_DM3F24
MA_DM2E19
MA_DM1C15
MA_DM0E12
MA_DQS_H7W12
MA_DQS_L7W13
MA_DQS_H6Y15
MA_DQS_L6W15
MA_DQS_H5AB19
MA_DQS_L5AB20
MA_DQS_H4AD23
MA_DQS_L4AC23
MA_DQS_H3G22
MA_DQS_L3G21
MA_DQS_H2C22
MA_DQS_L2C21
MA_DQS_H1G16
MA_DQS_L1G15
MA_DQS_H0G13
MA_DQS_L0H13
R3 39.2_0402_1%
1 2
MEM:CMD/CTRL/CLK
JCPUB
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
VTT1D10
VTT2C10
VTT3B10
VTT4AD10
VTT5W10
VTT6AC10
VTT7AB10
VTT8AA10
VTT9A10
MA1_ODT1V19
MA1_ODT0U21
MA0_ODT1V22
MA0_ODT0T19
MB1_ODT0Y26
MB0_ODT1W23
MB0_ODT0W26
RSVD_M2B18
MB1_CS_L0U22
MB0_CS_L1W25
MB0_CS_L0V26
MA0_CS_L1U19
MA1_CS_L1V20
MA1_CS_L0U20
MA0_CS_L0T20
MA_ADD15K19
MA_ADD14K24
MA_ADD13V24
MA_ADD12K20
MA_ADD11L22
MA_ADD10R21
MA_ADD9K22
MA_ADD8L19
MA_ADD7L21
MA_ADD6M24
MA_ADD5L20
MA_ADD4M22
MA_ADD3M19
MA_ADD2N22
MA_ADD1M20
MA_ADD0N21
MA_BANK2J21
MA_BANK1R23
MA_BANK0R20
MA_RAS_LR19
MA_CAS_LT22
MA_WE_LT24
MEMZPAF10
MEMZNAE10
VTT_SENSEY10
MEMVREFW17
MA_CLK_H4P19
MA_CLK_L4P20
MA_CLK_H7Y16
MA_CLK_L7AA16
MA_CLK_H1E16
MA_CLK_L1F16
MA_CLK_H5N19
MA_CLK_L5N20
MB_CLK_H4R26
MB_CLK_L4R25
MB_CLK_H7AF18
MB_CLK_L7AF17
MB_CLK_H1A17
MB_CLK_L1A18
MB_CLK_H5P22
MB_CLK_L5R22
MA_CKE0J22
MA_CKE1J20
MB_CKE0J25
MB_CKE1H26
MB_ADD15J24
MB_ADD14J23
MB_ADD13W24
MB_ADD12L25
MB_ADD11L26
MB_ADD10T26
MB_ADD9K26
MB_ADD8M26
MB_ADD7L24
MB_ADD6N25
MB_ADD5L23
MB_ADD4N26
MB_ADD3N23
MB_ADD2P26
MB_ADD1N24
MB_ADD0P24
MB_BANK2J26
MB_BANK1U26
MB_BANK0R24
MB_RAS_LU25
MB_CAS_LU24
MB_WE_LU23
RSVD_M1H16
C13
1000P_0402_25V8J
1
2
C151.5P_0402_50V9C
1
2
C101.5P_0402_50V9C
1
2
C141.5P_0402_50V9C
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
THERMDA_CPU
THERMDC_CPU
CPU_DBRDY
CPU_TDO
CPU_TMS
CPU_TCK
CPU_TDI
CPU_TRST#
CPU_DBREQ#
HDT_RST#LDT_RST#
CPU_VDD1_FB_H
CPU_THERMTRIP#_R
VDD_NB_FB_H
CPU_VDD0_FB_L
VDD_NB_FB_LCPU_VDD1_FB_LVDD_NB_FB_HVDD_NB_FB_L
CPU_HTREF0
CPU_HTREF1
CPU_TEST25_L_BYPASSCLK_L
CPU_DBRDYCPU_TMS
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST19_PLLTEST0
CPU_CLKIN_SC_P
CPU_THERMTRIP#_R
LDT_RST#
H_PWRGD_CPU
LDT_STOP#
THERMDA_CPU
LDT_STOP#
THERMDC_CPUCPU_SIDCPU_SIC
CPU_LDT_REQ#
CPU_CLKIN_SC_N
CPU_VDD0_FB_H
CPU_TDICPU_TRST#CPU_TCK
CPU_DBREQ#
CPU_TDO
CPU_SVCCPU_SVD
CPU_TEST12_SCANSHIFTENB
CPU_TEST20_SCANCLK2CPU_TEST21_SCANEN
CPU_TEST24_SCANCLK1CPU_TEST22_SCANSHIFTEN
CPU_TEST29_L_FBCLKOUT_NCPU_TEST29_H_FBCLKOUT_P
CPU_TEST17_BP3CPU_TEST16_BP2
CPU_TEST14_BP0CPU_TEST15_BP1
CPU_TEST28_L_PLLCHRZ_NCPU_TEST28_H_PLLCHRZ_P
H_PWRGD_CPULDT_RST#
CPU_TEST23_TSTUPD
CPU_MEMHOT#_1.8V
CPU_LDT_REQ#
CPU_TEST27_SINGLECHAIN
CPU_PROCHOT#_1.8
CPU_TEST18_PLLTEST1
CPU_PRO CHOT#_1.8
CPU_VDD0_FB_HCPU_VDD0_FB_L
CPU_VDD1_FB_HCPU_VDD1_FB_L
CPU_TEST21_SCANEN
CPU_TEST27_SINGLECHAIN
CPU_TEST18_PLLTEST1CPU_TEST19_PLLTEST0
CPU_TEST15_BP1
CPU_TEST20_SCANCLK2
CPU_TEST22_SCANSHIFTENCPU_TEST12_SCANSHIFTENB
CPU_TEST24_SCANCLK1
CPU_TEST14_BP0
CPU_SVDCPU_SVC
SMB_EC_CK1
SMB_EC_DA1CPU_SID
CPU_SIC
SB_PWRGD <20,33,43>
CPU_SVD <43>CPU_SVC <43>
H_PWRGD_CPU<19>
LDT_RST#<19>
LDT_STOP#<11,19>
VDD_NB_FB_H <43>VDD_NB_FB_L <43>
CPU_VDD0_FB_H<43>CPU_VDD0_FB_L<43>
CLK_CPU_BCLK<15>
CLK_CPU_BCLK#<15>
CPU_LDT_REQ# <11,19>
H_THERMTRIP# <20>
EN0 <37,39>
H_PROCHOT# <19>
H_THERMTRIP#_EC <33>
SMB_EC_CK2 <33>
SMB_EC_DA2 <33>
SMB_EC_CK1 <32,33,34,37>
SMB_EC_DA1 <32,33,34,37>
+3VS
+1.8V
+3VS
+1.8V
+1.2V_HT
+2.5VDDA
+2.5VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+CPU_CORE_NB
+1.8V
+1.8V
+CPU_CORE_0
+CPU_CORE_0
+1.8V
+1.8V
+3VS
+1.8V
+1.8V
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
AMD CPU S1G2 CTRL
Custom
6 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
2200p change to
100p
Address:100_1101
HDT Connector
NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.
Address:100_1100
+1.8V sense no support
0718 AMD , need check with AMD
0718 Silego -- 216 ohm
Place close to CPU wihtin 1.5"
VDDA=300mA
as short as possibleroute as differential
testpoint under package
Close to CPU
Close to CPU
9/20 SP020016900
0718 AMD --> 1K ohm
FDV301N, the Vgs is:min = 0.65VTyp = 0.85VMax = 1.5V
EC is PU to 5VALW
2.09V for Gate
02/12 Remove R59.
02/15 Follow Trinity design.
02/15 Change R18 and R19 from 390 to 2.2K ohm.
02/27 Change net name to EN0.
03/04 Reserve R175, R814, C939, Q127 and Q129.
Reserve the R488 and R489 for S1G3 CPU
R484 10_0402_5%
1 2
R175
20K_0402_5%
@
12
T11 PAD
R3
82
20
_0
40
2_
5%
@1
2
R5 300_0402_5%
1 2+C16
100U_D2_10VM@
1
2
T10PAD
C174.7U_0805_10V4Z
1
2
R13 44.2_0402_1%1 2
R22 1K_0402_5%
1 2
G
DSQ129
FDV301N_NL_SOT23-3
@
2
13
C203900P_0402_50V7K 1 2
C190.22U_0603_16V4Z
1
2
R33 300_0402_5%@12
C
B
E
Q3
PMBT3904_SOT23
1
2
3
R4
02
20
_0
40
2_
5%
@1
2
R11 10K_0402_5%@12
C23
0.1U_0402_16V7K
1
2
R8169_0402_1%
12
L1
FBM_L11_201209_300L_08051 2
SAMTEC_ASP-68200-07
JP3
CONN@
2468
101214161820222423
21191715131197531
26
R14 44.2_0402_1%1 2
R23 1K_0402_5%1 2
R6 0_0402_5%@
1 2
R486 10_0402_5% 1 2
R16 0_0402_5%1 2
T5PAD
E
B
C
Q2MMBT3904_NL_SOT23-3@
2
3 1
R7 0_0402_5%1 2
C18
3300P_0402_50V7K
1
2
U2
ADM1032ARMZ-2REEL_MSOP8
VDD1
ALERT#6
THERM#4
GND5
D+2
D-3
SCLK8
SDATA7
R814
34.8K_0402_1%~N
@
12
R29 300_0402_5%@12
R36
300_0402_5%
12
T12PAD
C27
100P_0402_25V8K
C220.01U_0402_25V4Z
@
1
2
U1
NC7SZ08P5X_NL_SC70-5@
B2
A1
Y4
P5
G3
R9 300_0402_5% 1 2
C240.01U_0402_25V4Z
@
1
2
C939 0.1U_0402_16V4Z@
1 2
R25 0_0402_5%1 2
R28 300_0402_5%12
R489 10_0402_5%@
1 2
R488 10_0402_5% @
1 2
R27 300_0402_5%@12
C21 3900P_0402_50V7K 1 2
T6PAD
T42PAD
G
DS
Q127FDV301N_NL_SOT23-3
@
2
13
R59 0_0402_5%@1 2
R19
2.2K_0402_5%
12
T7PAD
R31 300_0402_5%@12
JCPUD
FOX_PZ6382A-284S-41F_GRIFFINCONN@
VDDA1F8
VDDA2F9
RESET_LB7
PWROKA7
LDTSTOP_LF10
SICAF4
SIDAF5
HT_REF1P6
HT_REF0R6
VDD0_FB_HF6
VDD0_FB_LE6
VDDIO_FB_HW9
VDDIO_FB_LY9
THERMTRIP_LAF6
PROCHOT_LAC7
RSVD2A5
LDTREQ_LC6
SVCA6
SVDA4
RSVD6C5
RSVD4B5
RSVD1A3
CLKIN_HA9
CLKIN_LA8
DBRDYG10
TMSAA9
TCKAC9
TRST_LAD9
TDIAF9
DBREQ_LE10
TDOAE9
TEST25_HE9
TEST25_LE8
TEST19G9
TEST18H10
RSVD8AA7
TEST9C2
TEST17D7
TEST16E7
TEST15F7
TEST14C7
TEST12AC8
TEST7C3
TEST6AA6
THERMDCW7
THERMDAW8
VDD1_FB_HY6
VDD1_FB_LAB6
TEST29_HC9
TEST29_LC8
TEST24AE7
TEST23AD7
TEST22AE8
TEST21AB8
TEST20AF7
TEST28_HJ7
TEST28_LH8
TEST27AF8
ALERT_LAE6
TEST10K8
TEST8C4
RSVD3B3
RSVD5C1
VDDNB_FB_HH6
VDDNB_FB_LG6
RSVD7D5
KEY2W18
MEMHOT_LAA8
RSVD10H18
RSVD9H19
KEY1M11
R24 300_0402_5%@1 2
R30
300_0402_5%
12
T13PAD
T4 PAD
R3
92
20
_0
40
2_
5%
@1
2
R3
72
20
_0
40
2_
5%
@1
2
R15
300_0402_5%
12
T9 PAD
C250.01U_0402_25V4Z
@
1
2
R10 10K_0402_5%
1 2
R485 10_0402_5% 1 2
R17
300_0402_5%@
12
T14PAD
R32 300_0402_5%@12
R487 10_0402_5%
1 2
R35 300_0402_5%@12
R18
2.2K_0402_5%
12
T43PAD
R26 300_0402_5%1 2
T8PAD
R34 300_0402_5%@12
R21
300_0402_5%
12
R4
13
00
_0
40
2_
5%
12
C26
0.1
U_
04
02
_1
6V
4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+0.9V
+CPU_CORE_0
+CPU_CORE_0
+CPU_CORE_0
+1.8V
+1.8V
+1.8V
+1.8V +1.8V
+0.9V
+0.9V
+CPU_CORE_NB
+1.8V
+1.8V
+CPU_CORE_0
+CPU_CORE_0
+CPU_CORE_0
+CPU_CORE_NB
+CPU_CORE_0+CPU_CORE_0
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
AMD CPU S1G2 PWR & GND
Custom
7 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
A: Add C165 and C176
to follow AMD Layout
review recommand for
EMI
Between CPU Socket and DIMM
180PF Qt'y follow the distance between
CPU socket and DIMM0. <2.5inch>
Under CPU Socket
Athlon 64 S1
Processor Socket
Near CPU Socket
VTT decoupling.
VDD(+CPU_CORE) decoupling.
VDDIO decoupling.+CPU_CORE_NB decoupling.
C: Change to NBO CAP
C: Change to NBO CAP
Under CPU Socket
Near CPU Socket Right side.
Near CPU Socket Left side.
Near Power Supply
Athlon 64 S1
Processor Socket
L 18A/720mil/36vias
L 4A/160mil/8vias
L 3A/120mil/6vias
Tigris platform will be 4A
01/18 Change the net name from +CPU_CORE_1 to +CPU_CORE_0
01/18 Change the net name from +CPU_CORE_1 to +CPU_CORE_0
C400.22U_0603_16V4Z
1
2
+ C29330U_X_2VM_R6M
1
2
C3322U_0805_6.3V6M
1
2
C65180P_0402_50V8J
1
2
C73180P_0402_50V8J
1
2
C754.7U_0805_10V4Z
1
2
C85180P_0402_50V8J
1
2
C3222U_0805_6.3V6M
1
2
C430.22U_0603_16V4Z
1
2
C45180P_0402_50V8J
1
2
C5422U_0805_6.3V6M
@1
2
C711000P_0402_25V8J
1
2
C4622U_0805_6.3V6M
1
2
C440.01U_0402_25V4Z
1
2
+ C28330U_X_2VM_R6M
1
2
C4722U_0805_6.3V6M
1
2
C690.22U_0603_16V4Z
1
2
C560.22U_0603_16V4Z
1
2
C550.22U_0603_16V4Z
1
2
C48
0.22U_0603_16V4Z
1
2
C3622U_0805_6.3V6M
1
2
C794.7U_0805_10V4Z
1
2
C5222U_0805_6.3V6M
1
2
C410.01U_0402_25V4Z
1
2
C610.01U_0402_25V4Z
1
2
C86180P_0402_50V8J
1
2
C580.22U_0603_16V4Z
1
2
C63180P_0402_50V8J
1
2
JCPUE
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
VDD1_25AC4
VDD1_26AD2
VDD0_1G4
VDD0_2H2
VDD0_3J9
VDD0_4J11
VDD0_5J13
VDD0_7K6
VDD0_8K10
VDD0_9K12
VDD0_10K14
VDD0_11L4
VDD0_12L7
VDD0_13L9
VDD0_14L11
VDD0_15L13
VDD0_17M2
VDD0_18M6
VDD0_19M8
VDD0_20M10
VDD0_21N7
VDD0_22N9
VDD0_23N11
VDD1_1P8
VDD1_2P10
VDD1_3R4
VDD1_4R7
VDD1_5R9
VDD1_6R11
VDD1_7T2
VDD1_8T6
VDD1_9T8
VDD1_10T10
VDD1_11T12
VDD1_12T14
VDD1_13U7
VDD1_14U9
VDD1_15U11
VDD1_16U13
VDD1_18V6
VDD1_19V8
VDD1_20V10
VDD1_21V12
VDD1_22V14
VDD1_23W4
VDD1_24Y2
VDD0_6J15
VDDNB_1K16
VDD0_16L15
VDDNB_2M16
VDDNB_3P16
VDDNB_4T16
VDD1_17U15
VDDNB_5V16
VDDIO1H25
VDDIO2J17
VDDIO3K18
VDDIO4K21
VDDIO5K23
VDDIO6K25
VDDIO7L17
VDDIO8M18
VDDIO9M21
VDDIO10M23
VDDIO11M25
VDDIO12N17
VDDIO13P18
VDDIO14P21
VDDIO15P23
VDDIO16P25
VDDIO17R17
VDDIO18T18
VDDIO19T21
VDDIO20T23
VDDIO21T25
VDDIO22U17
VDDIO23V18
VDDIO24V21
VDDIO25V23
VDDIO26V25
VDDIO27Y25
C3822U_0805_6.3V6M
1
2
C680.22U_0603_16V4Z
1
2
C3722U_0805_6.3V6M
1
2
C810.22U_0603_16V4Z
1
2
C64180P_0402_50V8J
1
2
+ C59
220U_Y_4VM
1
2
C804.7U_0805_10V4Z
1
2
C841000P_0402_25V8J
1
2
C5322U_0805_6.3V6M
1
2
C62180P_0402_50V8J
1
2
C674.7U_0805_10V4Z
1
2
C820.22U_0603_16V4Z
1
2
C42180P_0402_50V8J
1
2
C764.7U_0805_10V4Z
1
2
C744.7U_0805_10V4Z
1
2
C701000P_0402_25V8J
1
2
C3922U_0805_6.3V6M
1
2
C51
180P_0402_50V8J
1
2
C3422U_0805_6.3V6M
1
2
C664.7U_0805_10V4Z
1
2
C774.7U_0805_10V4Z
1
2
C570.22U_0603_16V4Z
1
2
C49
0.22U_0603_16V4Z
1
2
+ C78
220U_Y_4VM
@
1
2
+ C31330U_X_2VM_R6M
1
2
JCPUF
FOX_PZ6382A-284S-41F_GRIFFIN
CONN@
VSS1AA4
VSS2AA11
VSS3AA13
VSS4AA15
VSS5AA17
VSS6AA19
VSS7AB2
VSS8AB7
VSS9AB9
VSS10AB23
VSS11AB25
VSS12AC11
VSS13AC13
VSS14AC15
VSS15AC17
VSS16AC19
VSS17AC21
VSS18AD6
VSS19AD8
VSS20AD25
VSS21AE11
VSS22AE13
VSS23AE15
VSS24AE17
VSS25AE19
VSS26AE21
VSS27AE23
VSS28B4
VSS29B6
VSS30B8
VSS31B9
VSS32B11
VSS33B13
VSS34B15
VSS35B17
VSS36B19
VSS37B21
VSS38B23
VSS39B25
VSS40D6
VSS41D8
VSS42D9
VSS43D11
VSS44D13
VSS45D15
VSS46D17
VSS47D19
VSS48D21
VSS49D23
VSS50D25
VSS51E4
VSS52F2
VSS53F11
VSS54F13
VSS55F15
VSS56F17
VSS57F19
VSS58F21
VSS59F23
VSS60F25
VSS61H7
VSS62H9
VSS63H21
VSS64H23
VSS65J4
VSS66J6
VSS67J8
VSS68J10
VSS69J12
VSS70J14
VSS71J16
VSS72J18
VSS73K2
VSS74K7
VSS75K9
VSS76K11
VSS77K13
VSS78K15
VSS79K17
VSS80L6
VSS81L8
VSS82L10
VSS83L12
VSS84L14
VSS85L16
VSS86L18
VSS87M7
VSS88M9
VSS89AC6
VSS90M17
VSS91N4
VSS92N8
VSS93N10
VSS94N16
VSS95N18
VSS96P2
VSS97P7
VSS98P9
VSS99P11
VSS100P17
VSS101R8
VSS102R10
VSS103R16
VSS104R18
VSS105T7
VSS106T9
VSS107T11
VSS108T13
VSS109T15
VSS110T17
VSS111U4
VSS112U6
VSS113U8
VSS114U10
VSS115U12
VSS116U14
VSS117U16
VSS118U18
VSS119V2
VSS120V7
VSS121V9
VSS122V11
VSS123V13
VSS124V15
VSS125V17
VSS126W6
VSS127Y21
VSS128Y23
VSS129N6
C831000P_0402_25V8J
1
2
+ C30330U_X_2VM_R6M
1
2
C600.01U_0402_25V4Z
1
2
C3522U_0805_6.3V6M
1
2
C72180P_0402_50V8J
1
2
C50
180P_0402_50V8J
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDR_CKE1_DIMMA
+V_DDR_MCH_REF
DDR_A_MA3
DDR_A_BS#0
DDR_A_RAS#
DDR_CS1_DIMMA#
DDR_CKE0_DIMMA
DDR_A_ODT1
DDR_A_WE#
DDR_A_D4
DDR_A_CAS# DDR_A_ODT0
DDR_CS0_DIMMA#
DDR_CKE1_DIMMA
DDR_A_D29
DDR_A_D30
DDR_A_D35
DDR_A_D26
DDR_A_D38
DDR_A_BS#0
DDR_A_D28
DDR_A_D34
DDR_A_D36DDR_A_D33
DDR_A_D31
DDR_A_D32
DDR_A_D27
DDR_A_D53
DDR_A_D46DDR_A_D43
DDR_A_D48
DDR_A_D41
DDR_A_D44
DDR_A_D50
DDR_A_D45
DDR_A_D49
DDR_A_D37
DDR_A_D55
DDR_A_D39
DDR_A_D51
DDR_A_D40
DDR_A_D47DDR_A_D42
DDR_A_D63
DDR_A_D54
DDR_A_D6
DDR_A_D14
DDR_A_D52
DDR_A_D3
DDR_A_D59DDR_A_D58
DDR_A_D9
DDR_A_D61DDR_A_D60
DDR_A_D57
DDR_A_D7
DDR_A_D8
DDR_A_D56
DDR_A_D5
DDR_A_D24
DDR_A_D23
DDR_A_D12
DDR_A_D15
DDR_A_D21
DDR_A_BS#1
DDR_A_D22
DDR_A_D16 DDR_A_D20
DDR_A_BS#2
DDR_A_D10
DDR_A_D13
DDR_A_D19DDR_A_D18
DDR_A_D17
DDR_A_D11
DDR_A_DM5
DDR_A_MA11
DDR_A_DM6
DDR_A_DM4
DDR_A_D0
DDR_A_DM7
DDR_A_D62
DDR_A_DM1
DDR_A_DM0
DDR_A_MA4
DDR_A_DM2
DDR_A_D25
DDR_A_D1
DDR_A_DM3
DDR_A_D2
DDR_A_MA8
DDR_A_MA12
DDR_A_MA14
DDR_A_MA9
DDR_A_MA10
DDR_A_DQS#0
DDR_A_MA13
DDR_A_MA1 DDR_A_MA0DDR_A_MA2
DDR_A_MA7
DDR_A_MA15
DDR_A_MA3DDR_A_MA5
DDR_A_MA6
DDR_A_DQS2
DDR_A_DQS6
DDR_A_DQS1
DDR_A_DQS0
DDR_A_DQS#6
DDR_A_DQS3DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS#2
DDR_A_DQS7
DDR_A_DQS#4
DDR_A_DQS#7
DDR_A_DQS#5
DDR_A_DQS#1DDR_A_MA4
DDR_A_MA11
DDR_A_MA12
DDR_A_MA5
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
+V_DDR_MCH_REF
DDR_A_MA15
DDR_A_BS#2DDR_CKE0_DIMMA
DDR_A_MA7DDR_A_MA6
DDR_A_MA14
DDR_A_MA0DDR_A_BS#1DDR_A_MA2
DDR_A_ODT0DDR_A_MA13DDR_A_RAS#DDR_CS0_DIMMA#
DDR_A_MA8DDR_A_MA9
DDR_A_MA10DDR_A_MA1
DDR_A_CAS#DDR_A_WE#DDR_CS1_DIMMA#DDR_A_ODT1
DDR_A_CLK0 <5>DDR_A_CLK#0 <5>
DDR_CKE0_DIMMA<5>
DDR_A_BS#2<5>
DDR_A_BS#0<5>DDR_A_WE#<5>
DDR_A_CAS#<5>DDR_CS1_DIMMA#<5>
DDR_A_ODT1<5>
DDR_A_CLK1 <5>DDR_A_CLK#1 <5>
DDR_CS0_DIMMA# <5>
DDR_A_ODT0 <5>
DDR_A_RAS# <5>DDR_A_BS#1 <5>
DDR_CKE1_DIMMA <5>
DDR_A_MA[0..15] <5>
DDR_A_D[0..63] <5>
DDR_A_DQS[0..7] <5>
DDR_A_DM[0..7] <5>
DDR_A_DQS#[0..7] <5>
SMB_CK_DAT0<9,15,20,30>SMB_CK_CLK0<9,15,20,30>
+V_DDR_MCH_REF <9>
+1.8V+1.8V
+3VS
+1.8V
+1.8V+0.9V
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
DDRII SO-DIMM 0
Custom
8 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
9/20 SP07000BZ00/SP07000EU00
DDR2 SOCKET H9.2 (REV)
Cross between +1.8V and +0.9V power plan
C101 0.1U_0402_16V4Z
1 2
C91 0.1U_0402_16V4Z
1 2
C97 0.1U_0402_16V4Z
1 2
C96
0.1U_0402_16V4Z
1
2
RP4
47_0804_8P4R_5%
18273645
C95
1000P_0402_25V8J
1
2
C102 0.1U_0402_16V4Z
1 2
C1030.1U_0402_16V4Z
1
2
C87 0.1U_0402_16V4Z
1 2
C93 0.1U_0402_16V4Z
1 2
C100 0.1U_0402_16V4Z
1 2
RP3
47_0804_8P4R_5%
18273645
C90 0.1U_0402_16V4Z
1 2
C98 0.1U_0402_16V4Z
1 2
R431K_0402_1%
12
RP1
47_0804_8P4R_5%
18273645
RP2
47_0804_8P4R_5%
18273645
RP7
47_0804_8P4R_5%
18273645
C94 0.1U_0402_16V4Z
1 2
C99 0.1U_0402_16V4Z
1 2
RP6
47_0804_8P4R_5%
18273645
C92 0.1U_0402_16V4Z
1 2
C89 0.1U_0402_16V4Z
1 2
RP5
47_0804_8P4R_5%
18273645
JP4
FOX_AS0A426-N8RN-7F
CONN@
VREF1
VSS3
DQ05
DQ17
VSS9
DQS0#11
DQS013
VSS15
DQ217
DQ319
VSS21
DQ823
DQ925
VSS27
DQS1#29
DQS131
VSS33
DQ1035
DQ1137
VSS39
VSS41
DQ1643
DQ1745
VSS47
DQS2#49
DQS251
VSS53
DQ1855
DQ1957
VSS59
DQ2461
DQ2563
VSS65
DM367
NC69
VSS71
DQ2673
DQ2775
VSS77
CKE079
VDD81
NC83
BA285
VDD87
A1289
A991
A893
VDD95
A597
A399
A1101
VDD103
A10/AP105
BA0107
WE#109
VDD111
CAS#113
NC/S1#115
VDD117
NC/ODT1119
VSS121
DQ32123
DQ33125
VSS127
DQS4#129
DQS4131
VSS133
DQ34135
DQ35137
VSS139
DQ40141
DQ41143
VSS145
DM5147
VSS149
DQ42151
DQ43153
VSS155
DQ48157
DQ49159
VSS161
NC,TEST163
VSS165
DQS6#167
DQS6169
VSS171
DQ50173
DQ51175
VSS177
DQ56179
DQ57181
VSS183
DM7185
VSS187
DQ58189
DQ59191
VSS193
SDA195
SCL197
VDDSPD199
VSS2
DQ44
DQ56
VSS8
DM010
VSS12
DQ614
DQ716
VSS18
DQ1220
DQ1322
VSS24
DM126
VSS28
CK030
CK0#32
VSS34
DQ1436
DQ1538
VSS40
VSS42
DQ2044
DQ2146
VSS48
NC50
DM252
VSS54
DQ2256
DQ2358
VSS60
DQ2862
DQ2964
VSS66
DQS3#68
DQS370
VSS72
DQ3074
DQ3176
VSS78
NC/CKE180
VDD82
NC/A1584
NC/A1486
VDD88
A1190
A792
A694
VDD96
A498
A2100
A0102
VDD104
BA1106
RAS#108
S0#110
VDD112
ODT0114
NC/A13116
VDD118
NC120
VSS122
DQ36124
DQ37126
VSS128
DM4130
VSS132
DQ38134
DQ39136
VSS138
DQ44140
DQ45142
VSS144
DQS5#146
DQS5148
VSS150
DQ46152
DQ47154
VSS156
DQ52158
DQ53160
VSS162
CK1164
CK1#166
VSS168
DM6170
VSS172
DQ54174
DQ55176
VSS178
DQ60180
DQ61182
VSS184
DQS7#186
DQS7188
VSS190
DQ62192
DQ63194
VSS196
SA0198
SA1200
R441K_0402_1%
12
C88 0.1U_0402_16V4Z
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDR_B_BS#0
DDR_B_D26
DDR_B_D29
DDR_B_D27DDR_B_D30
DDR_B_D33
DDR_B_D31
DDR_B_D32
DDR_B_D28
DDR_B_D34DDR_B_D35
DDR_B_D38
DDR_B_D36
DDR_B_D39
DDR_B_D37
DDR_B_D41
DDR_B_D42
DDR_B_D44DDR_B_D40
DDR_B_D43 DDR_B_D47
DDR_B_D48
DDR_B_D45
DDR_B_D46
DDR_B_D49 DDR_B_D53
DDR_B_D51 DDR_B_D55DDR_B_D50
DDR_B_D52
DDR_B_D56
DDR_B_D54
DDR_B_D59
DDR_B_D57
DDR_B_D58
DDR_B_D61
DDR_B_D63
DDR_B_D60
DDR_B_D3
DDR_B_D8
DDR_B_D6DDR_B_D7
DDR_B_D5
DDR_B_D14
DDR_B_D13
DDR_B_D11DDR_B_D10
DDR_B_D9
DDR_B_D15
DDR_B_D12
DDR_B_D17DDR_B_D20
DDR_B_D18 DDR_B_D22DDR_B_D19
DDR_B_D24
DDR_B_D16
DDR_B_D23
DDR_B_BS#2
DDR_B_BS#1
DDR_B_D25
DDR_B_D62
DDR_B_DM7
DDR_B_DM2
DDR_B_DM4
DDR_B_DM3
DDR_B_DM1
DDR_B_DM0
DDR_B_DM6
DDR_B_DM5
DDR_B_MA4
DDR_B_D0
DDR_B_D2
DDR_B_D1
DDR_B_D4
DDR_B_MA11
DDR_B_MA10
DDR_B_MA12DDR_B_MA9
DDR_B_MA6DDR_B_MA8
DDR_B_MA5
DDR_B_MA7
DDR_B_MA3DDR_B_MA0
DDR_B_MA8DDR_B_MA9
DDR_B_MA13
DDR_B_MA15
DDR_B_MA2DDR_B_MA1
DDR_B_MA14
DDR_B_DQS2
DDR_B_DQS#0
DDR_B_DQS4
DDR_B_DQS0
DDR_B_DQS#1
DDR_B_DQS5
DDR_B_DQS7
DDR_B_DQS3
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS#4
DDR_B_DQS#2
DDR_B_DQS#6
DDR_B_DQS#3
DDR_B_DQS1
DDR_B_DQS#5
DDR_B_ODT1
DDR_CKE0_DIMMB
DDR_CS1_DIMMB#
DDR_B_RAS#DDR_B_WE#
DDR_CKE1_DIMMB
DDR_B_CAS# DDR_B_ODT0
DDR_CS0_DIMMB#
DDR_B_MA12
DDR_B_MA5
DDR_B_MA4
DDR_B_D[0..63]
DDR_B_MA[0..15]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_DQS#[0..7]
DDR_B_WE#DDR_B_CAS#DDR_CS1_DIMMB#DDR_B_ODT1
DDR_B_MA3DDR_B_MA1DDR_B_BS#0DDR_B_MA10
DDR_B_MA13DDR_B_ODT0DDR_B_BS#1DDR_B_RAS#
DDR_CS0_DIMMB#DDR_B_MA0DDR_B_MA2DDR_B_MA6
DDR_B_MA7DDR_B_MA11DDR_B_MA14
DDR_B_D21
DDR_B_MA15DDR_CKE1_DIMMB
DDR_CKE0_DIMMBDDR_B_BS#2
+V_DDR_MCH_REF<8>
DDR_B_CLK0 <5>DDR_B_CLK#0 <5>
DDR_CKE0_DIMMB<5>
DDR_B_BS#2<5>
DDR_B_BS#0<5>DDR_B_WE#<5>
DDR_B_CAS#<5>DDR_CS1_DIMMB#<5>
DDR_B_ODT1<5>
DDR_B_CLK1 <5>DDR_B_CLK#1 <5>
DDR_B_ODT0 <5>
DDR_B_RAS# <5>DDR_B_BS#1 <5>
DDR_CKE1_DIMMB <5>
DDR_CS0_DIMMB# <5>
DDR_B_MA[0..15] <5>
DDR_B_D[0..63] <5>
DDR_B_DQS[0..7] <5>
DDR_B_DM[0..7] <5>
DDR_B_DQS#[0..7] <5>
SMB_CK_DAT0<8,15,20,30>SMB_CK_CLK0<8,15,20,30>
+1.8V+1.8V
+3VS
+0.9V
+3VS
+1.8V
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
DDRII SO-DIMM 1
Custom
9 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
9/20 SP07000ET00/SP07000GN00
Cross between +1.8V and +0.9V power plan
RP8
47_0804_8P4R_5%
18273645
RP14
47_0804_8P4R_5%
18273645
C108 0.1U_0402_16V4Z
12
RP10
47_0804_8P4R_5%
18273645
C105 0.1U_0402_16V4Z
12
C113 0.1U_0402_16V4Z
1 2
C114 0.1U_0402_16V4Z
12
RP11
47_0804_8P4R_5%
18273645
C1190.1U_0402_16V4Z
1
2
C107 0.1U_0402_16V4Z
1 2
C106 0.1U_0402_16V4Z
1 2
C104
1000P_0402_25V8J
1
2
C117 0.1U_0402_16V4Z
1 2
RP12
47_0804_8P4R_5%
18273645
C110 0.1U_0402_16V4Z
1 2
C111 0.1U_0402_16V4Z
12
JP5
TYCO_292527-4
CONN@
VREF1
VSS3
DQ05
DQ17
VSS9
DQS0#11
DQS013
VSS15
DQ217
DQ319
VSS21
DQ823
DQ925
VSS27
DQS1#29
DQS131
VSS33
DQ1035
DQ1137
VSS39
VSS41
DQ1643
DQ1745
VSS47
DQS2#49
DQS251
VSS53
DQ1855
DQ1957
VSS59
DQ2461
DQ2563
VSS65
DM367
NC69
VSS71
DQ2673
DQ2775
VSS77
CKE079
VDD81
NC83
BA285
VDD87
A1289
A991
A893
VDD95
A597
A399
A1101
VDD103
A10/AP105
BA0107
WE#109
VDD111
CAS#113
NC/S1#115
VDD117
NC/ODT1119
VSS121
DQ32123
DQ33125
VSS127
DQS4#129
DQS4131
VSS133
DQ34135
DQ35137
VSS139
DQ40141
DQ41143
VSS2
DQ44
DQ56
VSS8
DM010
VSS12
DQ614
DQ716
VSS18
DQ1220
DQ1322
VSS24
DM126
VSS28
CK030
CK0#32
VSS34
DQ1436
DQ1538
VSS40
VSS42
DQ2044
DQ2146
VSS48
NC50
DM252
VSS54
DQ2256
DQ2358
VSS60
DQ2862
DQ2964
VSS66
DQS3#68
DQS370
VSS72
DQ3074
DQ3176
VSS78
NC/CKE180
VDD82
NC/A1584
NC/A1486
VDD88
A1190
A792
A694
VDD96
A498
A2100
A0102
VDD104
BA1106
RAS#108
S0#110
VDD112
ODT0114
NC/A13116
VDD118
NC120
VSS122
DQ36124
DQ37126
VSS128
DM4130
VSS132
DQ38134
DQ39136
VSS138
DQ44140
DQ45142
VSS144
VSS145
DM5147
VSS149
DQ42151
DQ43153
VSS155
DQ48157
DQ49159
VSS161
NC,TEST163
VSS165
DQS6#167
DQS6169
VSS171
DQ50173
DQ51175
VSS177
DQ56179
DQ57181
VSS183
DM7185
VSS187
DQ58189
DQ59191
VSS193
SDA195
SCL197
VDDSPD199
DQS5#146
DQS5148
VSS150
DQ46152
DQ47154
VSS156
DQ52158
DQ53160
VSS162
CK1164
CK1#166
VSS168
DM6170
VSS172
DQ54174
DQ55176
VSS178
DQ60180
DQ61182
VSS184
DQS7#186
DQS7188
VSS190
DQ62192
DQ63194
VSS196
SAO198
SA1200
GND202
GND201
C115 0.1U_0402_16V4Z
1 2
RP13
47_0804_8P4R_5%
18273645
C109 0.1U_0402_16V4Z
12
RP9
47_0804_8P4R_5%
18273645
C118 0.1U_0402_16V4Z
12
C112 0.1U_0402_16V4Z
1 2
C116 0.1U_0402_16V4Z
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
H_CADIN7
H_CADIN15
H_CTLIN1H_CTLON1
H_CADON7
H_CADON15
PCIE_ITX_PRX_P5PCIE_ITX_PRX_N5
PCIE_ITX_PRX_P1PCIE_ITX_PRX_N1PCIE_ITX_PRX_P2PCIE_ITX_PRX_N2PCIE_ITX_PRX_P3PCIE_ITX_PRX_N3
PCIE_ITX_PRX_P0PCIE_ITX_PRX_N0
SB_TX2P_CSB_TX2N_CSB_TX3P_CSB_TX3N_C
SB_TX0P_CSB_TX0N_CSB_TX1P_C
H_CADIN[0..15]
H_CADIP[0..15]H_CADOP[0..15]
H_CADON[0..15]
SB_TX1N_C
H_CADIP5
H_CADIN9
H_CADIN11
H_CTLIP1
H_CTLIP0
H_CADIN2H_CADIP3
H_CADIN12
H_CADOP2
H_CADOP6
H_CADOP9
H_CADOP12
H_CADIN8
H_CADON4
H_CADIN5
H_CADIP8
H_CADIP11
H_CADIP14
H_CADOP0
H_CTLIN0
H_CADIN10
H_CADON1
H_CADOP13
H_CADIN1
H_CADIN3
H_CADIN4
H_CADIP10
H_CADIP13
H_CTLOP1
H_CADON5
H_CADON9
H_CADON13
H_CADIP0
H_CADIP7
H_CADON3H_CADIP4
H_CADIP15H_CADIN14
H_CTLOP0
H_CADIP2
H_CADOP1H_CADON0
H_CADON10
H_CADON14
H_CADIP1
H_CADIP6
H_CTLON0
H_CADON2
H_CADOP5
H_CADOP10
H_CADOP3
H_CADOP7
H_CADON8
H_CADOP11
H_CADIP9
H_CADIP12H_CADON11
H_CADOP14
H_CADIN6
H_CADOP4
H_CADIN0
H_CADIN13
H_CADON6
H_CADOP8
H_CADON12
H_CADOP15
PCIE_PTX_C_IRX_P5<26>PCIE_PTX_C_IRX_N5<26>
H_CLKIN0 <4>H_CLKIP0 <4>
H_CTLIN0 <4>H_CTLIP0 <4>
H_CLKON0<4>H_CLKOP0<4>
H_CLKOP1<4>H_CLKON1<4>
H_CTLOP0<4>H_CTLON0<4>
H_CLKIN1 <4>H_CLKIP1 <4>
H_CTLIN1 <4>H_CTLIP1 <4>H_CTLOP1<4>
H_CTLON1<4>
PCIE_ITX_C_PRX_P5 <26>PCIE_ITX_C_PRX_N5 <26>
PCIE_ITX_C_PRX_N1 <27>PCIE_ITX_C_PRX_P1 <27>
PCIE_ITX_C_PRX_P2 <26>PCIE_ITX_C_PRX_N2 <26>PCIE_ITX_C_PRX_P3 <25>PCIE_ITX_C_PRX_N3 <25>
PCIE_ITX_C_PRX_P0 <26>PCIE_ITX_C_PRX_N0 <26>
PCIE_PTX_C_IRX_P0<26>PCIE_PTX_C_IRX_N0<26>PCIE_PTX_C_IRX_P1<27>PCIE_PTX_C_IRX_N1<27>
PCIE_PTX_C_IRX_P3<25>PCIE_PTX_C_IRX_N3<25>
PCIE_PTX_C_IRX_P2<26>PCIE_PTX_C_IRX_N2<26>
H_CADIP[0..15] <4>
H_CADON[0..15]<4> H_CADIN[0..15] <4>
H_CADOP[0..15]<4>
SB_RX1P<19>SB_RX1N<19>
SB_RX0P<19>SB_RX0N<19>
SB_TX0P <19>
SB_TX1N <19>
SB_TX0N <19>SB_TX1P <19>
SB_RX3P<19>SB_RX3N<19>
SB_RX2P<19>SB_RX2N<19>
SB_TX2P <19>SB_TX2N <19>
SB_TX3N <19>SB_TX3P <19>
TMDS_B_CLK <18>TMDS_B_CLK# <18>
TMDS_B_DATA0 <18>TMDS_B_DATA0# <18>
TMDS_B_DATA1 <18>TMDS_B_DATA1# <18>
TMDS_B_DATA2 <18>TMDS_B_DATA2# <18>
+1.1VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
RS880-HT/PCIE
Custom
10 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
NEED CHECK R68 & R69 WITH AMD
0718 Place within 1"layout 1:2
0718 Place within 1"layout 1:2
LAN10/100
WLAN
New Card
CardReader
DP0GFX_TX0,TX1,TX2 and TX3
RS780M Display Port Support (muxed on GFX)
DP1GFX_TX4,TX5,TX6 and TX7
AUX0 and HPD0
AUX1 and HPD1
TV Tuner
9/20 SA00001ZG00(A11) S IC 216-0674001-00/RS780M FCBGA528P 0FH
C164 0.1U_0402_16V7K 1 2
C162 0.1U_0402_16V7K 1 2
C167 0.1U_0402_16V7K 1 2
PART 1 OF 6
HY
PE
R T
RA
NS
PO
RT
CP
U I/F
U3A
RS880M_FCBGA528
HT_RXCAD15PU19
HT_RXCAD15NU18
HT_RXCAD14PU20
HT_RXCAD14NU21
HT_RXCAD13PV21
HT_RXCAD13NV20
HT_RXCAD12PW21
HT_RXCAD12NW20
HT_RXCAD11PY22
HT_RXCAD11NY23
HT_RXCAD10PAA24
HT_RXCAD10NAA25
HT_RXCAD9PAB25
HT_RXCAD9NAB24
HT_RXCAD8PAC24
HT_RXCAD8NAC25
HT_RXCAD7PN24
HT_RXCAD7NN25
HT_RXCAD6PP25
HT_RXCAD6NP24
HT_RXCAD5PP22
HT_RXCAD5NP23
HT_RXCAD4PT25
HT_RXCAD4NT24
HT_RXCAD3PU24
HT_RXCAD3NU25
HT_RXCAD2PV25
HT_RXCAD2NV24
HT_RXCAD1PV22
HT_RXCAD1NV23
HT_RXCAD0PY25
HT_RXCAD0NY24
HT_RXCLK1PAB23
HT_RXCLK1NAA22
HT_RXCLK0PT22
HT_RXCLK0NT23
HT_RXCTL0PM22
HT_RXCTL0NM23
HT_RXCTL1PR21
HT_RXCTL1NR20
HT_RXCALPC23
HT_RXCALNA24
HT_TXCAD15PP18
HT_TXCAD15NM18
HT_TXCAD14PM21
HT_TXCAD14NP21
HT_TXCAD13PM19
HT_TXCAD13NL18
HT_TXCAD12PL19
HT_TXCAD12NJ19
HT_TXCAD11PJ18
HT_TXCAD11NK17
HT_TXCAD10PJ20
HT_TXCAD10NJ21
HT_TXCAD9PG20
HT_TXCAD9NH21
HT_TXCAD8PF21
HT_TXCAD8NG21
HT_TXCAD7PK23
HT_TXCAD7NK22
HT_TXCAD6PK24
HT_TXCAD6NK25
HT_TXCAD5PJ25
HT_TXCAD5NJ24
HT_TXCAD4PH23
HT_TXCAD4NH22
HT_TXCAD3PF23
HT_TXCAD3NF22
HT_TXCAD2PF24
HT_TXCAD2NF25
HT_TXCAD1PE24
HT_TXCAD1NE25
HT_TXCAD0PD24
HT_TXCAD0ND25
HT_TXCLK1PL21
HT_TXCLK1NL20
HT_TXCLK0PH24
HT_TXCLK0NH25
HT_TXCTL0PM24
HT_TXCTL0NM25
HT_TXCTL1PP19
HT_TXCTL1NR18
HT_TXCALPB24
HT_TXCALNB25
C165 0.1U_0402_16V7K 1 2
C160 0.1U_0402_16V7K 1 2
C168 0.1U_0402_16V7K 1 2
C154 0.1U_0402_16V7K 1 2
C159 0.1U_0402_16V7K 1 2
R57 301_0402_1%1 2
C169 0.1U_0402_16V7K 1 2
C152 0.1U_0402_16V7K 1 2
R58 301_0402_1%1 2
PART 2 OF 6
PC
IE I/F
G
FX
PCIE I/F GPP
PCIE I/F SB
U3B
RS880M_FCBGA528
SB_TX3PAD5
SB_TX3NAE5
GPP_TX2PAA2
GPP_TX2NAA1
GPP_TX3PY1
GPP_TX3NY2
SB_RX3PW5
SB_RX3NY5
GPP_RX2PAD1
GPP_RX2NAD2
GPP_RX3PV5
GPP_RX3NW6
SB_TX0PAD7
SB_TX0NAE7
SB_TX1PAE6
SB_TX1NAD6
SB_RX0PAA8
SB_RX0NY8
SB_RX1PAA7
SB_RX1NY7
PCE_CALRP(PCE_BCALRP)AC8
PCE_CALRN(PCE_BCALRN)AB8
SB_TX2NAC6
SB_RX2PAA5
SB_RX2NAA6
SB_TX2PAB6
GPP_RX0PAE3
GPP_RX0NAD4
GPP_RX1PAE2
GPP_RX1NAD3
GPP_TX0PAC1
GPP_TX0NAC2
GPP_TX1PAB4
GPP_TX1NAB3
GFX_RX0PD4
GFX_RX0NC4
GFX_RX1PA3
GFX_RX1NB3
GFX_RX2PC2
GFX_RX2NC1
GFX_RX3PE5
GFX_RX3NF5
GFX_RX4PG5
GFX_RX4NG6
GFX_RX5PH5
GFX_RX5NH6
GFX_RX6PJ6
GFX_RX6NJ5
GFX_RX7PJ7
GFX_RX7NJ8
GFX_RX8PL5
GFX_RX8NL6
GFX_RX9PM8
GFX_RX9NL8
GFX_RX10PP7
GFX_RX10NM7
GFX_RX11PP5
GFX_RX11NM5
GFX_RX12PR8
GFX_RX12NP8
GFX_RX13PR6
GFX_RX13NR5
GFX_RX14PP4
GFX_RX14NP3
GFX_RX15PT4
GFX_RX15NT3
GFX_TX0PA5
GFX_TX0NB5
GFX_TX1PA4
GFX_TX1NB4
GFX_TX2PC3
GFX_TX2NB2
GFX_TX3PD1
GFX_TX3ND2
GFX_TX4PE2
GFX_TX4NE1
GFX_TX5PF4
GFX_TX5NF3
GFX_TX6PF1
GFX_TX6NF2
GFX_TX7PH4
GFX_TX7NH3
GFX_TX8PH1
GFX_TX8NH2
GFX_TX9PJ2
GFX_TX9NJ1
GFX_TX10PK4
GFX_TX10NK3
GFX_TX11PK1
GFX_TX11NK2
GFX_TX12PM4
GFX_TX12NM3
GFX_TX13PM1
GFX_TX13NM2
GFX_TX14PN2
GFX_TX14NN1
GFX_TX15PP1
GFX_TX15NP2
GPP_TX4PY4
GPP_TX4NY3
GPP_TX5PV1
GPP_TX5NV2
GPP_RX4PU5
GPP_RX4NU6
GPP_RX5PU8
GPP_RX5NU7
C155 0.1U_0402_16V7K 1 2
C161 0.1U_0402_16V7K 1 2
C163 0.1U_0402_16V7K 1 2
C156 0.1U_0402_16V7K 1 2C157 0.1U_0402_16V7K 1 2
C166 0.1U_0402_16V7K 1 2
R55 1.27K_0402_1% 1 2
C158 0.1U_0402_16V7K 1 2
C153 0.1U_0402_16V7K 1 2
R56 2K_0402_1% 1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+VDDA18HTPLL
+NB_HTPVDD
+AVDD2
NB_THERMAL_DCNB_THERMAL_DA
TV_LUMA
NB_RESET#
+AVDD1
RED
BLUE
CRT_VSYNC
GREEN
CRT_HSYNC
NB_PWRGD
NB_ALLOW_LDTSTOPNB_LDTSTOP#
+VDDLT18
TV_COMPS
TV_CRMA
+AVDDQ
+VDDLTP18
RED
GREEN
BLUE
+NB_PLLVDD
+VDDA18PCIEPLL
NB_LDTSTOP#
NB_ALLOW_LDTSTOP
NB_PWM
ENBKL
UMA_CRT_CLK<16>UMA_CRT_DAT<16>
HDMIDAT_UMA<18>
NB_PWRGD<20>
CRT_HSYNC<14,16>CRT_VSYNC<14,16>
UMA_ENVDD <17>
NBGFX_CLK<15>NBGFX_CLK#<15>
CLK_SBLINK_BCLK<15>CLK_SBLINK_BCLK#<15>
HPD <18>
CLK_NBHT<15>CLK_NBHT#<15>
PLT_RST#<14,19,25,26,27,32,33>
RED<16>
GREEN<16>
BLUE<16>
AUX_CAL<14>
RS780_DFT_GPIO_0<14> SUS_STAT# <20>
LVDS_A2+ <17>
LVDS_A0+ <17>
LVDS_A1+ <17>
LVDS_ACLK- <17>
HDMICLK_UMA<18>
LVDS_ACLK+ <17>
LVDS_A2- <17>
LVDS_A0- <17>
LVDS_A1- <17>
LCD_DDC_DAT<17>LCD_DDC_CLK<17>
NB_OSC_14.318M<15>
LDT_STOP#<6,19>
CPU_LDT_REQ#<6,19>
SUS_STAT_R# <14>
ENBKL <33>NB_PWM <17>
+3VS
+3VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.8VS
+1.1VS
+1.1VS
+1.8VS
+1.8VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
RS880 VEDIO/CLK GEN
Custom
11 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Strap pin
AVDD=100mA
Strap pin
PA_RS780A4placement close to NB ball
NB temp to SB
Strap pin
L 0.08A/10mil/1vias
R
R73
R1072
R1085
R1086
Veri-Bright Non Veri-Bright
@
@
@
@
Ripely 2.0 support Veri-Bright function
R714.7K_0402_5%
1 2
T48 PAD
R64 150_0402_1%@1 2
L10
BLM18PG121SN1D_0603
1 2
C179
2.2U_0603_6.3V4Z
1
2
R371 300_0402_5%
1 2
T46 PAD
T49PAD
L4
0_0603_5%
R65 715_0402_1%
1 2
L6
BLM18PG121SN1D_0603
1 2
R730_0402_5%1 2
C1802.2U_0603_6.3V4Z
1
2
R1072 100K_0402_5%1 2
L11
BLM18PG121SN1D_0603
1 2
C1752.2U_0603_6.3V4Z
1
2
L5
BLM18PG121SN1D_06031 2
R66 0_0402_5%
1 2
R724.7K_0402_5%
1 2
T50PAD
C11200.1U_0402_16V4Z
1
2
R77 0_0402_5%
1 2
C1722.2U_0603_6.3V4Z
1
2
C1712.2U_0603_6.3V4Z
1
2
L2
BLM18PG121SN1D_0603
1 2
T47 PAD
C178
2.2U_0603_6.3V4Z
1
2L3
BLM18PG121SN1D_06031 2
R67
0_0402_5%
1 2
R63 150_0402_1%@1 2
PART 3 OF 6
PM
CL
OC
Ks
PL
L P
WR
MIS.
CR
T/T
VO
UT
LV
TM
U3C
RS880M_FCBGA528
VDDA18HTPLLH17
SYSRESETbD8
POWERGOODA10
LDTSTOPbC10
ALLOW_LDTSTOPC12
REFCLK_P/OSCIN(OSCIN)E11
PLLVDD(NC)A12
HPD(NC)D10
DDC_CLK0/AUX0P(NC)A8
DDC_DATA0/AUX0N(NC)B8
THERMALDIODE_PAE8
THERMALDIODE_NAD8
I2C_CLKB9
STRP_DATAB10
GFX_REFCLKPT2
GFX_REFCLKNT1
GPP_REFCLKPU1
GPP_REFCLKNU2
PLLVDD18(NC)D14
PLLVSS(NC)B12
TXOUT_L0P(NC)A22
TXOUT_L0N(NC)B22
TXOUT_L1P(NC)A21
TXOUT_L1N(NC)B21
TXOUT_L2P(NC)B20
TXOUT_L2N(DBG_GPIO0)A20
TXOUT_L3P(NC)A19
TXOUT_U0P(NC)B18
TXOUT_L3N(DBG_GPIO2)B19
TXOUT_U0N(NC)A18
TXOUT_U1P(PCIE_RESET_GPIO3)A17
TXOUT_U1N(PCIE_RESET_GPIO2)B17
TXOUT_U2P(NC)D20
TXOUT_U2N(NC)D21
TXOUT_U3P(PCIE_RESET_GPIO5)D18
TXOUT_U3N(NC)D19
TXCLK_LP(DBG_GPIO1)B16
TXCLK_LN(DBG_GPIO3)A16
TXCLK_UP(PCIE_RESET_GPIO4)D16
TXCLK_UN(PCIE_RESET_GPIO1)D17
VDDLTP18(NC)A13
VSSLTP18(NC)B13
C_Pr(DFT_GPIO5)E17
Y(DFT_GPIO2)F17
COMP_Pb(DFT_GPIO4)F15
RED(DFT_GPIO0)G18
TMDS_HPD(NC)D9
I2C_DATAA9
TESTMODED13
HT_REFCLKNC24
HT_REFCLKPC25
SUS_STAT#(PWM_GPIO5)D12
GREEN(DFT_GPIO1)E18
BLUE(DFT_GPIO3)E19
DAC_VSYNC(PWM_GPIO6)B11
DAC_HSYNC(PWM_GPIO4)A11
DAC_RSET(PWM_GPIO1)G14
AVDD1(NC)F12
AVDD2(NC)E12
REDb(NC)G17
GREENb(NC)F18
AVDDDI(NC)F14
AVSSDI(NC)G15
AVDDQ(NC)H15
AVSSQ(NC)H14
VDDLT18_2(NC)B15
VDDLT33_1(NC)A14
VDDLT33_2(NC)B14
VSSLT1(VSS)C14
VSSLT2(VSS)D15
VDDLT18_1(NC)A15
VSSLT3(VSS)C16
VSSLT4(VSS)C18
VSSLT5(VSS)C20
LVDS_DIGON(PCE_TCALRP)E9
LVDS_BLON(PCE_RCALRP)F7
LVDS_ENA_BL(PWM_GPIO2)G12
VSSLT6(VSS)E20
VDDA18PCIEPLL1D7
VDDA18PCIEPLL2E7
BLUEb(NC)F19
AUX_CAL(NC)C8
GPPSB_REFCLKP(SB_REFCLKP)V4
GPPSB_REFCLKN(SB_REFCLKN)V3
DDC_DATA1/AUX1N(NC)A7
DDC_CLK1/AUX1P(NC)B7
DAC_SCL(PCE_RCALRN)F8
DAC_SDA(PCE_TCALRN)E8
REFCLK_N(PWM_GPIO3)F11
VSSLT7(VSS)C22
RSVDG11
R1086 100K_0402_5%@1 2
L7
BLM18PG121SN1D_0603
1 2
C176
2.2U_0603_6.3V4Z
1
2
R801.8K_0402_5%
1 2
R1085 0_0402_5%@ 1 2
C1730.1U_0402_16V4Z
1
2
C1744.7U_0805_10V4Z
1
2
R88 10K_0402_5%
12
R62 150_0402_1%@1 2
L9
BLM18PG121SN1D_0603
1 2
C1702.2U_0603_6.3V4Z
1
2
R68
0_0402_5%
1 2
R69 0_0402_5% 1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
MEM_DQS_P0
MEM_DQS_P1MEM_DQS_N0
MEM_A9
MEM_A2MEM_A12
MEM_DQ10
MEM_DQS_P0
+MEM_VREF
MEM_DQS_N0
MEM_ODT
MEM_DQS_P1
MEM_DM1
MEM_DQS_N1
MEM_DQ14MEM_A2
MEM_DQ7
MEM_A8
MEM_DQ12
MEM_A1
+NB_IOPLLVDD+1.8V_IOPLLVDD
MEM_A3
+MEM_VREF
MEM_A0
MEM_DQ4
MEM_DQ2MEM_DQ5
MEM_DQ0
MEM_DQ6
MEM_DQ11
MEM_DQ1
MEM_A11
MEM_BA0MEM_BA1
MEM_CKE
MEM_WE#MEM_CS#
MEM_A4
MEM_DQS_N1MEM_RAS#MEM_CAS#
MEM_BA2
MEM_DM1
MEM_CLKPMEM_CLKN
MEM_ODT
MEM_DM0
MEM_A10
MEM_DQ15
+MEM_VREF1
MEM_A11
MEM_A8MEM_A9
MEM_CAS#
MEM_CS#
MEM_CLKN
MEM_CKE
MEM_RAS#
MEM_CLKP
MEM_WE#
MEM_DM0
MEM_BA0
MEM_A7
MEM_DQ13
+MEM_VREF1
MEM_A0
MEM_A10
MEM_BA2
MEM_A3
MEM_DQ8
MEM_BA1
MEM_A6
+VDDL
MEM_DQ9MEM_A1
MEM_A6MEM_A7
MEM_A4MEM_A5
MEM_DQ3
MEM_DQ2
MEM_DQ0MEM_DQ1
MEM_DQ3
MEM_DQ10
MEM_DQ7
MEM_DQ11
MEM_DQ8
MEM_DQ5MEM_DQ6
MEM_DQ9
MEM_DQ15
MEM_DQ13MEM_DQ14
MEM_DQ4
MEM_DQ12
MEM_A12
MEM_A5
MEM_COMP_P
MEM_COMP_N
+1.8VS
+1.8VS
+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ+1.8V_MEM_VDDQ
+1.1VS
+1.8V_MEM_VDDQ
+1.8V_MEM_VDDQ
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
RS880 Side-Port DDR2 SDRAM
Custom
12 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Side Port disable,VREF need connect to +1.8VS for DDR2
Layout Note: 50 mil for VSSDL
MEM_COMP_P and MEM_COMP_N tracewidth >=10mils and 10mils spacing fromother Signals in X,Y,Z directions
220 ohm @ 100MHz,2A
9/20 SA000012G20 S IC D2 32M16 HY5PS121621CFP-25 FBGA 84P
02/15 Remove L96.02/15 Change L12 and L13 from bead to 0 ohm resistor.
Support 8M x 16bit x 8 bank side port
SBD_MEM/DVO_I/F
PAR 4 OF 6
U3D
RS880M_FCBGA528
MEM_A0(NC)AB12
MEM_A1(NC)AE16
MEM_A2(NC)V11
MEM_A3(NC)AE15
MEM_A4(NC)AA12
MEM_A5(NC)AB16
MEM_A6(NC)AB14
MEM_A7(NC)AD14
MEM_A8(NC)AD13
MEM_A9(NC)AD15
MEM_A10(NC)AC16
MEM_A11(NC)AE13
MEM_A12(NC)AC14
MEM_A13(NC)Y14
MEM_BA0(NC)AD16
MEM_BA1(NC)AE17
MEM_BA2(NC)AD17
MEM_RASb(NC)W12
MEM_CASb(NC)Y12
MEM_WEb(NC)AD18
MEM_CSb(NC)AB13
MEM_CKE(NC)AB18
MEM_ODT(NC)V14
MEM_CKP(NC)V15
MEM_CKN(NC)W14
MEM_DM0(NC)W17
MEM_DM1/DVO_D8(NC)AE19
MEM_DQS0P/DVO_IDCKP(NC)Y17
MEM_DQS0N/DVO_IDCKN(NC)W18
MEM_DQS1P(NC)AD20
MEM_DQS1N(NC)AE21
MEM_DQ0/DVO_VSYNC(NC)AA18
MEM_DQ1/DVO_HSYNC(NC)AA20
MEM_DQ2/DVO_DE(NC)AA19
MEM_DQ3/DVO_D0(NC)Y19
MEM_DQ4(NC)V17
MEM_DQ5/DVO_D1(NC)AA17
MEM_DQ6/DVO_D2(NC)AA15
MEM_DQ7/DVO_D4(NC)Y15
MEM_DQ8/DVO_D3(NC)AC20
MEM_DQ9/DVO_D5(NC)AD19
MEM_DQ10/DVO_D6(NC)AE22
MEM_DQ11/DVO_D7(NC)AC18
MEM_DQ12(NC)AB20
MEM_DQ13/DVO_D9(NC)AD22
MEM_DQ14/DVO_D10(NC)AC22
MEM_DQ15/DVO_D11(NC)AD21
MEM_COMPP(NC)AE12
MEM_COMPN(NC)AD12
MEM_VREF(NC)AE18
IOPLLVDD18(NC)AE23
IOPLLVSS(NC)AD23
IOPLLVDD(NC)AE24
C2
02
0.1
U_
04
02
_1
6V
4Z
1
2
R9
7
1K
_0
40
2_
1%
12
C184
1U_0603_10V6K
1
2
C6
07
1U
_0
40
2_
6.3
V4
Z
1
2
C1820.1U_0402_16V4Z
1
2
C1
95
0.1
U_
04
02
_1
6V
4Z
1
2
R9
9
1K
_0
40
2_
1%
12
L15
0_0805_5%1 2
R92 40.2_0402_1%12
R9
6
1K
_0
40
2_
1%
12
C1
96
0.1
U_
04
02
_1
6V
4Z
1
2
C1812.2U_0603_6.3V4Z
1
2
C203
22
U_
08
05
_6
.3V
6M
1
2C2
01
0.1
U_
04
02
_1
6V
4Z
1
2C6
08
1U
_0
40
2_
6.3
V4
Z
1
2
R93 40.2_0402_1%12
L12
0_0603_5%
1 2
R9
8
1K
_0
40
2_
1%
12
U61
HY5PS561621AFP-25_FBGA84
VREFJ2
LDMF3
UDMB3
DQ14B1
DQ13D9
DQ12D1
DQ11D3
DQ10D7
DQ9C2
DQ8C8
DQ7F9
DQ6F1
DQ5H9
DQ4H1
DQ3H3
DQ2H7
DQ1G2
DQ0G8
BA1L3
BA0L2
A11P7
A10/APM2
A9P3
A8P8
A7P2
A6N7
A5N3
A4N8
A3N2
A0M8
A1M3
A2M7
RASK7
CKEK2
ODTK9
CSL8
CASL7
CKJ8
CKK8
WEK3
VDDQG9
VDDQA9
VDDQC1
VDDQC3
VDDQC7
VDDQC9
VDDQE9
VDDQG1
VSSQA7
VSSQB2
VSSQB8
VSSQD2
VSSQD8
VSSQE7
VSSQF2
VSSQF8
VSSQH2
VSSQH8
VSSA3
VSSE3
VSSJ3
VSSN1
VSSP9
UDQSA8
UDQSB7
LDQSE8
LDQSF7
VDDQG3
VDDQG7
VDDA1
VDDE1
VDDJ9
VDDM9
VDDR1
A12R2
DQ15B9
VDDLJ1
VSSDLJ7
NCR8
NCA2
NCL1
NCR3
NCR7
NCE2
C2
00
0.1
U_
04
02
_1
6V
4Z
1
2C1
99
0.1
U_
04
02
_1
6V
4Z
1
2
C1832.2U_0603_6.3V4Z
1
2
L13
0_0603_5%1 2
R91
100_0402_1%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+VDDA11PCIE
+VDDHTRX
+VDDHT
+VDDA18PCIE
+VREF1.35V
+1.8V_VDD_SP
+VDDHTTX
VLDT_EN#<36>
+1.1VS
+1.8VS
+1.1VS +NB_VDDC
+1.8VS
+3VS
+1.8VS
+1.2V_HT
+1.1VS
+3VS
+1.8VS
+1.35VS
+1.8VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
RS880 PWR/GND
Custom
13 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
2A
2A
2A
2A
VDDA_12=2.5A
VDD_CORE=5A
L Just for RS780M A11 version boot issue
L 0.6A/50mil/4vias
L 0.45A/40mil/3vias
L 0.5A/50mil/4vias
L 0.25A/30mil/2vias
L 0.7A/60mil/4vias
L 7A/280mil/16vias
L 0.15A/30mil/2vias
C2
47
0.1
U_
04
02
_1
6V
4Z
1
2C239
0.1U_0402_16V4Z
1
2
C238
0.1U_0402_16V4Z
1
2
C1067
10U_0805_10V4Z@
1
2
C216
0.1U_0402_16V4Z
1
2
G
D
S
Q1632N7002_SOT23-3@
2
13
C2154.7U_0805_10V4Z
1
2
C2
42
0.1
U_
04
02
_1
6V
4Z
1
2
L22
0_0805_5%
12 C2
44
0.1
U_
04
02
_1
6V
4Z
1
2
L16
0_0805_5%
12
C248 0.1U_0402_16V4Z12
C2170.1U_0402_16V4Z
1
2
PART 5/6
PO
WE
R
U3E
RS880M_FCBGA528
VDDHT_1J17
VDDHT_2K16
VDDHT_3L16
VDDHT_4M16
VDDHT_5P16
VDDHT_6R16
VDDHT_7T16
VDDHTTX_1AE25
VDDHTTX_2AD24
VDDHTTX_3AC23
VDDHTTX_4AB22
VDDHTTX_5AA21
VDDHTTX_6Y20
VDDHTTX_7W19
VDDHTTX_8V18
VDDHTRX_1H18
VDDHTRX_2G19
VDDHTRX_3F20
VDDHTRX_4E21
VDDHTRX_5D22
VDD18_1F9
VDD18_2G9
VDD18_MEM1(NC)AE11
VDD18_MEM2(NC)AD11
VDDA18PCIE_1J10
VDDA18PCIE_2P10
VDDA18PCIE_3K10
VDDA18PCIE_10Y9
VDDA18PCIE_11AA9
VDDA18PCIE_12AB9
VDDA18PCIE_13AD9
VDDA18PCIE_14AE9
VDDA18PCIE_6W9
VDDA18PCIE_7H9
VDDPCIE_1A6
VDDPCIE_2B6
VDDPCIE_3C6
VDDPCIE_4D6
VDDPCIE_5E6
VDDPCIE_6F6
VDDPCIE_7G7
VDDPCIE_8H8
VDDPCIE_9J9
VDDA18PCIE_4M10
VDDA18PCIE_5L10
VDDC_1K12
VDDC_2J14
VDDC_3U16
VDDPCIE_11M9
VDDC_4J11
VDDC_5K15
VDDPCIE_10K9
VDDC_6M12
VDDC_7L14
VDDC_8L11
VDDC_9M13
VDDC_10M15
VDDC_11N12
VDDC_12N14
VDDC_13P11
VDDC_14P13
VDDC_15P14
VDDC_16R12
VDDC_17R15
VDDC_18T11
VDDC_19T15
VDDC_20U12
VDDC_21T14
VDD33_1(NC)H11
VDD33_2(NC)H12
VDD_MEM1(NC)AE10
VDD_MEM2(NC)AA11
VDD_MEM3(NC)Y11
VDD_MEM4(NC)AD10
VDD_MEM6(NC)AC10
VDD_MEM5(NC)AB10
VDDA18PCIE_8T10
VDDC_22J16
VDDPCIE_12L9
VDDA18PCIE_9R10
VDDPCIE_13P9
VDDPCIE_14R9
VDDPCIE_15T9
VDDPCIE_16V9
VDDPCIE_17U9
VDDA18PCIE_15U10
VDDHTRX_6B23
VDDHTRX_7A23
VDDHTTX_9U17
VDDHTTX_10T17
VDDHTTX_11R17
VDDHTTX_12P17
VDDHTTX_13M17
C598 0.1U_0402_16V4Z12
+C234
330U_D2E_2.5VM_R15
1
2
C228
0.1U_0402_16V4Z
1
2
C218
0.1U_0402_16V4Z
1
2
C597 0.1U_0402_16V4Z12
C1064
10U_0805_10V4Z@
1
2
C2
31
0.1
U_
04
02
_1
6V
4Z
1
2
C2500.1U_0402_16V4Z
1 2
C2094.7U_0805_10V4Z
1
2
C223 0.1U_0402_16V4Z 12
C237
0.1U_0402_16V4Z
1
2
C2
33
10
U_
08
05
_1
0V
4Z
1
2
C222 1U_0402_6.3V4Z
1 2
C236
0.1U_0402_16V4Z
1
2
R1051 0_0603_5%1 2
R1017 0_0402_5%@1 2
C2
30
0.1
U_
04
02
_1
6V
4Z
1
2
R1016
3K_0402_5%@
12
L18
0_0805_5%
12
L17
FBMA-L11-201209-221LMA30T_0805
1 2
C2511U_0402_6.3V4Z
1
2
U64
G2992F1U_SO8@
VOUT4
NC5
GND2
VREF3
VIN1
VCNTL6
NC7
NC8
TP9
C246
4.7U_0805_10V4Z
1
2
C599 0.1U_0402_16V4Z12
C2
41
0.1
U_
04
02
_1
6V
4Z
1
2
C229
0.1U_0402_16V4Z
1
2
C214
0.1U_0402_16V4Z 1
2
C2080.1U_0402_16V4Z
1
2
C224 0.1U_0402_16V4Z 12
PJP604
PAD-OPEN 4x4m
1 2
C225
4.7U_0805_10V4Z
1
2
PART 6/6
GR
OU
ND
U3F
RS880M_FCBGA528
VSSAHT1A25
VSSAHT2D23
VSSAHT3E22
VSSAHT4G22
VSSAHT5G24
VSSAHT6G25
VSSAHT7H19
VSSAHT8J22
VSSAHT9L17
VSSAHT10L22
VSSAHT11L24
VSSAHT12L25
VSSAHT13M20
VSSAHT14N22
VSSAHT15P20
VSSAHT16R19
VSSAHT17R22
VSSAHT18R24
VSSAHT19R25
VSSAHT21U22
VSSAHT22V19
VSSAHT23W22
VSSAHT24W24
VSSAHT25W25
VSSAHT26Y21
VSSAHT27AD25
VSS2D11
VSS3G8
VSS4E14
VSS5E15
VSS7J12
VSS8K14
VSS9M11
VSS10L15
VSS11L12
VSS12M14
VSS13N13
VSS14P12
VSS15P15
VSS16R11
VSS17R14
VSS18T12
VSS19U14
VSS20U11
VSS21U15
VSS22V12
VSS23W11
VSS24W15
VSS25AC12
VSS26AA14
VSS27Y18
VSS28AB11
VSS29AB15
VSS30AB17
VSS31AB19
VSS32AE20
VSSAPCIE1A2
VSSAPCIE2B1
VSSAPCIE3D3
VSSAPCIE4D5
VSSAPCIE5E4
VSSAPCIE6G1
VSSAPCIE7G2
VSSAPCIE8G4
VSSAPCIE9H7
VSSAPCIE10J4
VSSAPCIE11R7
VSSAPCIE12L1
VSSAPCIE13L2
VSSAPCIE14L4
VSSAPCIE15L7
VSS34K11
VSSAPCIE16M6
VSSAPCIE17N4
VSSAPCIE18P6
VSSAPCIE19R1
VSSAPCIE20R2
VSSAPCIE21R4
VSSAPCIE22V7
VSSAPCIE23U4
VSSAPCIE24V8
VSSAPCIE25V6
VSSAPCIE26W1
VSSAPCIE27W2
VSSAPCIE28W4
VSSAPCIE29W7
VSSAPCIE30W8
VSSAPCIE31Y6
VSSAPCIE32AA4
VSSAPCIE33AB5
VSSAPCIE34AB1
VSSAPCIE35AB7
VSSAPCIE36AC3
VSSAPCIE37AC4
VSSAPCIE38AE1
VSSAPCIE39AE4
VSSAPCIE40AB2
VSS1AE14
VSSAHT20H20
VSS33AB21
VSS6J15
C252
1U_0402_6.3V4Z
1
2
C249 4.7U_0805_10V4Z12
R10151K_0402_1%
@
12
C2060.1U_0402_16V4Z
1
2
L19
0_0805_5%
12
C2354.7U_0805_10V4Z
1
2
C212 10U_0805_10V4Z
C2
32
0.1
U_
04
02
_1
6V
4Z
1
2
C2
40
0.1
U_
04
02
_1
6V
4Z
1
2
C227
0.1U_0402_16V4Z
1
2
C2530.1U_0402_16V4Z
1 2
C219 1U_0402_6.3V4Z
1 2
C10680.1U_0402_16V7K@
1
2
C220 1U_0402_6.3V4Z
1 2
C1066
0.1U_0402_16V7K@
1
2
C221 1U_0402_6.3V4Z
1 2
C211 10U_0805_10V4Z
C226
0.1U_0402_16V4Z
1
2
C210
0.1U_0402_16V4Z
1
2
C2
43
0.1
U_
04
02
_1
6V
4Z
1
2
C1065
1U_0603_10V6K@
1
2
C207
0.1U_0402_16V4Z
1
2
C2
45
10
U_
08
05
_1
0V
4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SUS_STAT_R#<11> PLT_RST# <11,19,25,26,27,32,33>
RS780_DFT_GPIO_0<11>
CRT_HSYNC<11,16>
CRT_VSYNC<11,16>
AUX_CAL<11>
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
RS880 STRAPS
Custom
14 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
RS740/RS780: Enables Side port memory ( RS780 use HSYNC#)1. Disable (RS740/RS780) 0 : Enable (RS740/RS780)
RX780: Enables the Test Debug Bus using PCIE bus1 : Disable ( Can still be enabled using nbcfg register access )0 : Enable
DFT_GPIO0: STRAP_DEBUG_BUS_PCIE_ENABLEb
Enables the Test Debug Bus using GPIO.1 : Disable (RS780) Enable (RX780)0 : Enable (RS780) Disable (RX780)PIN: RX780:NB_TV_C; RS740: RS740_DFT_GPIO5; RS780: VSYNC#
DFT_GPIO5:STRAP_DEBUG_BUS_GPIO_ENABLEb
Selects Loading of STRAPS from EPROM1 : Bypass the loading of EEPROM straps and use Hardware Default Values0 : I2C Master can load strap values from EEPROM if connected, or usedefault values if not connectedRS740/RX780: DFT_GPIO1 RS780:SUS_STAT
DFT_GPIO1: LOAD_EEPROM_STRAPS
RS780 use HSYNC to enable SIDE PORT (internal pull high)
RS780 DFT_GPIO1
RX780 DFT_GPIO1 mux at GREEN(Ball E18) and change pull low form 150 to 3K.
RS780 DFT_GPIO5 mux at CRT_VSYNC pull low to 3K
R102 1K_0402_5%@12
R107 3K_0402_5%12
R101 1K_0402_5%12
D4 CH751H-40PT_SOD323-2@
2 1
R105 1K_0402_5%@12
R104 150_0402_1%@1 2
R1064 3K_0402_5%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CLKREQ_MCARD2#
CLK
_X
TA
L_
OU
TC
LK
_X
TA
L_
IN
CLKREQ_NCARD#CLKREQ_MCARD2#
CL
K_
48
M_
US
B_
R
CLK_XTAL_IN
CLK_XTAL_OUT
NB
_O
SC
_1
4.3
18
M_
RS
EL_S
AT
A27M
_S
EL
SEL_SATA
27M_SEL
CLK_CPU_BCLK_R
CLK_CPU_BCLK#_R
CLKREQ_NCARD#
CLKREQ_MCARD1#
CLKREQ_MCARD1#
CLKREQ_LAN#
CLKREQ_LAN#
CLKREQ4
CLKREQ4
CLK_48M_USB
NB_OSC_14.318M
CLK_14M_SIO
CLK_PCIE_MCARD0# <27>CLK_PCIE_MCARD0 <27>
NB_OSC_14.318M <11>
CLK_PCIE_MCARD2<26>CLK_PCIE_MCARD2#<26>
CLK_PCIE_MCARD1#<26>CLK_PCIE_MCARD1<26>
CLK_CPU_BCLK# <6>
CLK_CPU_BCLK <6>
NBGFX_CLK <11>NBGFX_CLK# <11>
CLK_PCIE_NCARD <26>CLK_PCIE_NCARD# <26>
CLKREQ_NCARD# <26>CLKREQ_MCARD2# <26>
SMB_CK_CLK0<8,9,20,30>SMB_CK_DAT0<8,9,20,30>
CLK_NBHT# <11>CLK_NBHT <11>
CLK_48M_USB <20>
CLK_PCIE_LAN <25>CLK_PCIE_LAN# <25>
CLK_SBLINK_BCLK#<11>CLK_SBLINK_BCLK<11> CLK_SBSRC_BCLK# <19>
CLK_SBSRC_BCLK <19>
CLKREQ_MCARD1# <26>
CLKREQ_LAN# <25>
CLK_14M_SB <19>
+3VS_CLK
+VDDCLK_IO
+3VS_CLK
+3
VS
_C
LK
+V
DD
CL
K_
IO
+3VS_CLK
+3VS_CLK
+3VS_CLK
+3VS_CLK
+VDDCLK_IO+1.2V_HT
+3VS_CLK
+3VS_CLK
+3VS_CLK
+3VS_CLK
+3
VS
_C
LK
+3
VS
_C
LK
+3
VS
_C
LK
+VDDCLK_IO
+VDDCLK_IO
+VDDCLK_IO
+3VS_CLK
+3VS_CLK
+3VS
+3VS_CLK
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
Clock generator
Custom
15 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
100M DIFF(IN/OUT)*
HT_REFCLKP
RX780 RS780
NB CLOCK INPUT TABLE
100M DIFF100M DIFF
100M DIFF100M DIFF
14M SE (1.8V) 14M SE (1.1V)
NB CLOCKS
NC vref
HT_REFCLKN
REFCLK_P
REFCLK_N
GFX_REFCLK 100M DIFF
Card Reader
SEL_SATA
* defaultconfigure as normal SRC(SRC_6) output
1
*0
configure as SATA output
MiniCard_2
CPU
MiniCard_1
GLAN
New Card
configure as single-ended 66MHz output1
*0 configure as differential 100MHz output
NB
NB GFX
configure as 27M and 27M_SS output
NB_OSC_14.318M
1 *
0 configure as SRC_7 output* default
RS780
1.8V 75R/100RRX780
1.1V 200R/100R
OSC_14M_NB
27M_SEL
PA_RS7X0A1
* default
Routing the trace at least 10mil
SB LINK SB SRC
Use voltage divider resistor R379 & R380 to pull low
PA_RS7X0A1
For ICS need to pull high.
For SLG is NC
EMI Caps for single end clock.
01/23 14.318MHz For SB710 reference
C446
0.1U_0402_16V4Z
1
2
C451
1U_0402_6.3V4Z
@1
2
C461
0.1U_0402_16V4Z
1
2
C447
0.1U_0402_16V4Z
1
2
Y2
14.31818MHZ_20P_6X1430004201
12
C453
0.1U_0402_16V4Z
1
2
R324 8.2K_0402_5%
1 2
R325 8.2K_0402_5%
1 2
R326 8.2K_0402_5%
1 2
C450
0.1U_0402_16V4Z
1
2
SLG8SP626VTR_QFN72_10x10
U10
VDD_CPU54
VDD_CPU_I/O53
VSS_CPU52
CLKREQ_1#51
CLKREQ_2#50
VDD_A49
VS
S_
SR
C1
9
SR
C_
1#
20
SR
C_
12
1
SR
C_
0#
22
SR
C_
02
3
CL
KR
EQ
_0
#2
4
AT
IGC
LK
_2
#2
5
AT
IGC
LK
_2
26
VS
S_
AT
IG2
7
VD
D_
AT
IG_
IO2
8
VD
D_
AT
IG2
9
AT
IGC
LK
_1
#3
0
AT
IGC
LK
_1
31
AT
IGC
LK
_0
#3
2
VS
S_
SB
_S
RC
36
SB
_S
RC
_1
35
SB
_S
RC
_1
#3
4A
TIG
CL
K_
03
3
VSS_A48
VSS_SATA47
SRC_6/SATA46
SRC_6#/SATA#45
VDD_SATA44
CLKREQ_3#43
CLKREQ_4#42
SB_SRC_SLOW#41
SB_SRC_040
SB_SRC_0#39
VDD_SB_SRC38
VDD_SB_SRC_IO37
RE
F_
1/S
EL
_S
AT
A6
4
RE
F_
2/S
EL
_2
76
3
VD
D_
RE
F6
2
VD
D_
HT
T6
1
HT
T_
0/6
6M
_0
60
HT
T_
0#
/66
M_
15
9
VS
S_
HT
T5
8
PD
#5
7
CP
U_
K8
_0
56
CP
U_
K8
_0
#5
5
SCL1
SDA2
VDD_DOT3
SRC_7#/27M4
SRC_7/27M_SS5
VSS_DOT6
SRC_5#7
SRC_58
SRC_4#9
SRC_410
VSS_SRC11
VDD_SRC_IO12
SRC_3#13
SRC_314
SRC_2#15
SRC_216
VDD_SRC17
VDD_SRC_IO18
RE
F_
0/S
EL
_H
TT
66
65
VS
S_
RE
F6
6X
TA
L_
IN6
7X
TA
L_
OU
T6
8V
DD
_4
86
94
8M
Hz_
17
04
8M
Hz_
07
1V
SS
_4
87
2
GN
D7
3
C465
22P_0402_50V8J
1
2
R379 158_0402_1% 1 2
C460
0.1U_0402_16V4Z
1
2
R372 10K_0402_5%
1 2
R186261_0402_1%@
12
R1106110_0402_5%
C464
22P_0402_50V8J
1
2
C455
0.1U_0402_16V4Z
1
2
R946 0_0402_1%
1 2
R1798.2K_0402_5%
@
12
R1045 8.2K_0402_5%@1 2
C107512P_0402_50V8J
1
2
R168
0_0805_5%
1 2 C448
0.1U_0402_16V4Z
1
2
R1105 75_0402_1%@
1 2
R174 8.2K_0402_5%
1 2
C45210U_0805_10V4Z
1
2
C458
0.1U_0402_16V4Z
1
2
R945 0_0402_1%
1 2
C449
0.1U_0402_16V4Z
1
2
R38090.9_0402_1%
1 2
R1808.2K_0402_5%
12
C457
0.1U_0402_16V4Z
1
2
C459
0.1U_0402_16V4Z
1
2
C445
0.1U_0402_16V4Z
1
2
R170 33_0402_5% 1 2
C1076
12P_0402_50V8J
1
2
R181
8.2K_0402_5%
12
C1123
1U_0402_6.3V4Z
1 2
R167
0_0805_5%
1 2
C11060.1U_0603_25V7K
1
2
C107412P_0402_50V8J
1
2
R1039 8.2K_0402_5%
1 2
C444
10U_0805_10V4Z
1
2C454
0.1U_0402_16V4Z
1
2
C456
0.1U_0402_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
GREEN_L
D_DDCCLK
D_DDCDATA
HS YNC
VSYNC
BLUE_L
GREEN
RED
BLUE
RED_L
D_HSYNC
D_DDCCLK
VSYNC
HS YNC
D_VSYNC
D_DDCDATA
D_HSYNC <35>
D_VSYNC <35>
RED_L <35>
GREEN_L <35>
BLUE_L <35>
RED<11>
GREEN<11>
BLUE<11>
UMA_CRT_CLK<11>
UMA_CRT_DAT<11> D_DDCDATA <35>
D_DDCCLK <35>
CRT_HSYNC<11,14>
CRT_VSYNC<11,14>
+3VS
+CRT_VCC+CRT_VCC
+CRT_VCC+5VS
+CRT_VCC
+R_CRT_VCC
+3VS
+CRT_VCC
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
CRT Connector
Custom
16 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
CRT CONNECTOR
v0.2 ADD
v0.2 ADD
F2
1A_6VDC_MINISMDC110
21
C4750.1U_0402_16V4Z
1
2
U13SN74AHCT1G125GW_SOT353-5
A2
Y4O
E#
1G
3P
5
JCRT
SUYIN_070546FR015S263ZRCONN@
RGND6
ID011
Red1
GGND7
SDA12
Green2
BGND8
Hsync13
Blue3
+5V9
Vsync14
res4
SGND10
SCL15
GND5
GND16
GND17
Q10A2N7002DW-7-F_SOT363-6
61
2
C4770.1U_0402_16V4Z
@1 2
R211
75
_0
40
2_
1%
12
L49
BLM15AG121SN1D_0402
1 2
L48
BLM15AG121SN1D_0402
1 2
C858
6P
_0
40
2_
50
V8
K
1
2
R214
75
_0
40
2_
1%
12
D35
DAN217_SC59
@
2 31
C469
6P
_0
40
2_
50
V8
K
1
2
D37
DAN217_SC59
@
2 31
L47
BLM15AG121SN1D_0402
1 2
R100
6.8K_0402_5%
C857
470P_0402_50V8J
@
1
2
D36
RB491D_SOT23
2 1
U14SN74AHCT1G125GW_SOT353-5
A2
Y4O
E#
1G
3P
5
R237
4.7K_0402_5%
12
C470
10
P_
04
02
_5
0V
8J
@
1
2
C11070.1U_0603_25V7K
1
2
C856
470P_0402_50V8J
@
1
2
C859
6P
_0
40
2_
50
V8
K
1
2
R1022 0_0402_5%@1 2
R240 0_0603_5%
1 2
C476
6P
_0
40
2_
50
V8
K
1
2
Q10B2N7002DW-7-F_SOT363-6
3
5
4
R241 0_0603_5%
1 2
C474
10
P_
04
02
_5
0V
8J
@
1
2
D34
DAN217_SC59
@
2 31
R217
75
_0
40
2_
1%
12
R2384.7K_0402_5%
12
R218
6.8K_0402_5%
C471
6P
_0
40
2_
50
V8
K
1
2
C472
6P
_0
40
2_
50
V8
K
1
2
C4730.1U_0402_16V4Z
1 2
R1023 0_0402_5%@1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
LVDS_A1+LVDS_A1-
BKOFF#
LVDS_A2+
LCD_DDC_DAT
DAC_BRIG
LVDS_A0+LVDS_A0-
DMIC_CLKDMIC_DAT
LVDS_A2-
LCD_DDC_DATLCD_DDC_CLK
LCD_DDC_CLK
BKOFF#
LVDS_ACLK-LVDS_ACLK+
USB20_P5
USB20_N5
LVDS_A1+LVDS_A1-
LVDS_A2+
LVDS_A0+LVDS_A0-
LVDS_A2-
LVDS_ACLK- LVDS_ACLK+USB20_P5USB20_N5
INV_PWM
INV_PWM
DAC_BRIG <33>BKOFF# <33>
DMIC_DAT <28>DMIC_CLK <28>
LCD_DDC_DAT <11>LCD_DDC_CLK <11>
LVDS_A2+ <11>LVDS_A2- <11>
LVDS_A1+ <11>LVDS_A1- <11>
LVDS_ACLK+ <11>LVDS_ACLK- <11>LVDS_A0+ <11>LVDS_A0- <11>
UMA_ENVDD<11>
CAM_SHDN# <21>
USB20_P5<20>USB20_N5<20>
NB_PWM<11>
EC_PWM<33>
+3VS
+3VS
INVPWR_B++LCDVDD
+USB_CAM
+LCDVDD
+LCDVDD
+5VALW
+5VS
B+
+USB_CAM
+5VALW +USB_CAM
+3VS
+5VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
LCD CONN. / WebCam
Custom
17 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
LVDS CONN
80mil
USB_VCCA is +3.9V, R892:100K;
R891:215KKohm
G916 Vref=1.25V when U54 install
G916-390T1UF
9/20 SP02000EA00/SP02000BW00
L Close to JLVDS
80mil
L C718 install when U54 isRT9193-39GB
Ripely 2.0 Support Veri-Bright function
PJP4PAD-OPEN 2x2m
21
R1084 0_0402_5%1 2
C8
67
68
0P
_0
40
2_
50
V7
K
@
12
C4
83
68
0P
_0
40
2_
50
V7
K
@
1
2
L44
FBMA-L11-201209-221LMA30T_0805
1 2
R2754.7K_0402_5% 1 2
C1108680P_0402_50V7K
1
2
R491100_0805_5%
1 2
R892
100K_0402_1%@
12
R2241M_0402_5%
12
R1078 0_0402_5%@ 1 2
D22
PRTR5V0U2X_SOT143-4@
GND1
IO12
IO23
VIN4
C1056 10P_0402_50V8J@1 2
C719
10U_0805_10V4Z1
2
U54
RT9193-39GB_SOT23-5
VIN1
GND2
EN3
VOUT5
BP4
C720
10U_0805_10V4Z1
2
C1058 10P_0402_50V8J@1 2
C1057 10P_0402_50V8J@1 2
R2762.2K_0402_5%
12
G
D
S
Q43
SI2301BDS-T1-E3_SOT23-3
2
13
C480
680P_0402_50V7K
12
JLVDS
ACES_88242-4001
CONN@
11
33
55
77
99
1111
1313
1515
1717
1919
2121
2323
2525
2727
2929
3131
3333
3535
3737
3939
22
44
66
88
1010
1212
1414
1616
1818
2020
2222
2424
2626
2828
3030
3232
3434
3636
3838
4040
GND41
GND42
Q45B2N7002DW-7-F_SOT363-6
3
5
4
R891
215K_0402_1%@
12
C1059 10P_0402_50V8J@1 2
R222
100K_0402_5%1 2
C718
0.1U_0402_16V4Z
1
2
C8
66
68
0P
_0
40
2_
50
V7
K
@1
2
C487
4.7U_0805_10V4Z
R1014
0_0402_5%
@
1 2
C863
1000P_0402_50V7K1
2
R225220_0402_5%
12
R2744.7K_0402_5% 1 2
C4910.1U_0402_16V4Z
1
2
Q45A
2N7002DW-7-F_SOT363-6
61
2
C479680P_0402_50V7K
1
2
C481
680P_0402_50V7K
12
C4
82
68
0P
_0
40
2_
50
V7
K
@
1
2
PJP6PAD-OPEN 2x2m
21
R4834.7K_0402_5%@1 2
R1013
0_0402_5%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
HDMI_R_D0-
HDMI_CLK-
HDMI_TX0+
HDMI_TX0-
HDMI_R_D0+
HDMI_TX1-
HDMI_R_D2-
HDMI_R_D2+HDMI_TX2+
HDMI_TX2-
HDMI_R_D1+
HDMI_R_D1-
HDMI_TX1+
HDMI_SDATA
HDMI_SCLK
HDMI_TX0-HDMI_TX0+
HDMI_TX1-HDMI_TX1+
HDMI_TX2-HDMI_TX2+
HDMI_HPD
HDMI_CLK+HDMI_CLK-
HDMI_TX0+HDMI_TX0-
HDMI_TX1+HDMI_TX1-
HDMI_TX2+HDMI_TX2-
HDMI_CLK-
HDMI_R_CK-
HDMI_R_CK+
HDMI_R_D2-HDMI_R_D2+
HDMI_R_D1+HDMI_R_D1-HDMI_R_D0+HDMI_R_D0-HDMI_R_CK+HDMI_R_CK-
HDMI_SCLKHDMI_SDATA
HDMI_HPDHDMI_CLK+
HDMI_CLK+
HDMICLK_UMA<11>
HDMIDAT_UMA<11>
HPD <11>
TMDS_B_CLK<10>TMDS_B_CLK#<10>
TMDS_B_DATA0<10>TMDS_B_DATA0#<10>
TMDS_B_DATA1<10>TMDS_B_DATA1#<10>
TMDS_B_DATA2<10>TMDS_B_DATA2#<10>
+HDMI_5V_OUT+3VS
+5VS +HDMI_5V_OUT
+HDMI_5V_OUT
+3VS
+HDMI_5V_OUT
+5VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
HDMI
Custom
18 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
MP:Update D10 to meet HDMI.
L Change PCB Footprint from SW_WCM2012F2S_4P to KING_WCM-2012-900T_4P
HDMI Connector
03/07 Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.
1/19 Use one mos to instead of two dule MOS design
v0.2 ADD
v0.2 ADD
C804 0.1U_0402_16V7K1 2
R1018
0_0402_5%
@
1 2
R2106.8K_0402_5%
Q134B2N7002DW-7-F_SOT363-6
3
5
4
G
D
S
Q173
2N7002_SOT23-3
2
13
R307715_0402_1%
12
R2094.7K_0402_5%
12
R115 0_0402_5%@1 2
L88
WCM-2012-900T_4P
11
44
33
22
R120 0_0402_5%@1 2
L86
WCM-2012-900T_4P
11
44
33
22
R118 0_0402_5%@1 2
R173715_0402_1%
12
C468
0.1U_0402_16V4Z
1
2
R113 0_0402_5%@1 2
U39SN74AHCT1G125GW_SOT353-5
A2
Y4O
E#
1G
3P
5
R6152.2K_0402_5%
12
R2366.8K_0402_5%
R119 0_0402_5%@1 2
R139715_0402_1%
12
C852 0.1U_0402_16V7K1 2
R117 0_0402_5%@1 2
D10
RB491D_SOT23
2 1
R112 0_0402_5%@1 2
C655 0.1U_0402_16V7K1 2
L87
WCM-2012-900T_4P
11
44
33
22
R315715_0402_1%
12
R1104100K_0402_5%
12
Q134A2N7002DW-7-F_SOT363-6
61
2
R141715_0402_1%
12
C507 0.1U_0402_16V7K1 2
C827 0.1U_0402_16V7K1 2
C850
0.1U_0402_16V4Z
1
2 R1019
0_0402_5%
@
1 2
JHDMI
SUYIN_100042MR019S153ZLCONN@
D2+1
GND2
D2-3
D1+4
GND5
D1-6
D0+7
GND8
D0-9
CK+10
GND11
CK-12
CEC13
Reserved14
SCL15
SDA16
DDC/CEC_GND17
+5V18
HP_DET19
GND20
GND21
GND22
GND23
R628100K_0402_5%
12
C508 0.1U_0402_16V7K1 2
C853 0.1U_0402_16V7K1 2
C675 0.1U_0402_16V7K1 2
R176
4.7K_0402_5%
12
R297715_0402_1%
12
R304715_0402_1%
12
C851
0.1U_0402_16V4Z
1
2
R172715_0402_1%
12
L85
WCM-2012-900T_4P
11
44
33
22
R116 0_0402_5%@1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CLK_PCI_SIO_R PCI_CLK3
CPU_LDT_REQ#
PLT_RST#NB_RST#_R
SB_RX0P_CSB_RX0N_CSB_RX1P_CSB_RX1N_C
CPU_LDT_REQ#H_PROCHOT#
NB_RST#_R
SB_32KHI
SB_32KHO
NB_RST#_R
+SB_PCIEVDD
PCI_PIRQH#
SB_RX2P_CSB_RX2N_CSB_RX3P_CSB_RX3N_C
CLK_PCI_EC_RLPCCLK1
H_PROCHOT#
SB_32KHI
SB_32KHO
PCI_AD23PCI_AD24PCI_AD25PCI_AD26PCI_AD27PCI_AD28
H_PWRGD
CLK_PCI_EC
LPCCLK1 CLK_PCI_SIO
CLK_PCI_SIO2
CLK_PCI_SIO
CLK_PCI_EC
H_PWRGD_SB
PCI_CLK3 <23>
PCI_CLK5 <23>
PLT_RST# <11,14,25,26,27,32,33>
PCI_CLK4 <23>
PCICLK2 <23>SB_RX0P<10>SB_RX0N<10>SB_RX1P<10>SB_RX1N<10>
SB_TX1P<10>SB_TX1N<10>
SB_TX0P<10>SB_TX0N<10>
SB_TX2P<10>SB_TX2N<10>SB_TX3P<10>SB_TX3N<10>
SB_RX2P<10>SB_RX2N<10>SB_RX3P<10>SB_RX3N<10>
RTC_CLK <23>
LPC_FRAME# <32,33>
LPC_AD1 <32,33>LPC_AD2 <32,33>
LPC_AD0 <32,33>
LPC_AD3 <32,33>
LDT_STOP#<6,11>
CPU_LDT_REQ#<6,11>H_PROCHOT#<6>
SIRQ <32,33>
CLK_SBSRC_BCLK<15>CLK_SBSRC_BCLK#<15>
LDT_RST#<6>
ACCEL_INT <30>
PCI_AD23 <23>
PCI_SERR# <33>
PCI_AD24 <23>PCI_AD25 <23>PCI_AD26 <23>PCI_AD27 <23>PCI_AD28 <23>
H_PWRGD_CPU<6>
H_PWRGD<43>
LPC_DRQ# <32>
CLK_PCI_EC <23,33>LPCCLK1 <23>
CLK_PCI_SIO <32>
H_PWRGD<43>
CLK_14M_SB<15>
+RTCVCC+SB_VBAT
+1.8VS
+3VALW
+RTCBATT
+3VL
+3VS
+PCIE_VDDR
+1.2V_HT
+SB_VBAT +RTCVCC_R
+RTCBATT_R
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
SB710-PCIE/PCI/ACPI/LPC/RTC
Custom
19 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
W=20mils
EC & Debug
STRAP PIN
STRAP PIN
Check AMD need pull low or not
W=20mils
W=20mils
Close to SB
Close to SB
9/20 SA00001S510 S IC 218S7EALA11FG SB700 BGA 528P SB 0FH
9/20 SP020008T00
01/23 14.318MHz for SB710 reference
R1107 0_0402_5%
1 2
R305 562_0402_1% 12
R311
0_0402_5%
1 2
C497 0.1U_0402_16V7K 1 2
T15PAD
U16
NC7SZ08P5X_NL_SC70-5@
B2
A1
Y4
P5
G3
C643
18P_0402_50V8J
1 2
C496 0.1U_0402_16V7K 1 2
L53
BLM18PG121SN1D_0603 1 2
C506
0.1U_0402_16V4Z@
12
C510
1U_0402_6.3V4Z
1
2
C50410U_0805_10V4Z
1
2
R308 33_0402_5%
1 2
C1086 12P_0402_50V8J
1 2
R301 0_0402_5%
1 2
C492 0.1U_0402_16V7K 1 2
R1079
0_0402_5%
1 2
C494 0.1U_0402_16V7K 1 2
R876
1K_0402_5%
1 2
C495 0.1U_0402_16V7K 1 2
C498 0.1U_0402_16V7K 1 2
Y3
32.768KHZ_12.5PF_Q13MC14610050_10PPM
OSC4
OSC1
NC3
NC2
PC
I E
XP
RE
SS
IN
TE
RF
AC
E
Part 1 of 5
SB700
PC
I IN
TE
RF
AC
E
LP
CR
TC
CP
U
RT
C X
TA
L
PC
I C
LK
S
CL
OC
K G
EN
ER
AT
OR
U15A
218-0660011 A14 SB7_FCBGA528
A_RST#N2
PCIE_RX2PR20
PCIE_RX2NR21
PCIE_RX3PR18
PCIE_TX3NT22
PCIE_TX3PT23
PCIE_TX2NU24
PCIE_TX2PU25
PCIE_RX1PU19
PCIE_RX1NV19
PCIE_RX0PU22
PCIE_RX0NU21
PCIE_TX1NV25
PCIE_TX1PV24
PCIE_TX0NV22
PCIE_TX0PV23
PCIE_RCLKP/NB_LNK_CLKPN25
PCIE_RCLKN/NB_LNK_CLKNN24
PCIE_CALRPT25
PCIE_CALRNT24
PCIE_PVDDP24
GPP_CLK1NL19
X1A3
X2B3
VBATB2
GPP_CLK0NJ18
GPP_CLK2PM19
ALLOW_LDTSTPF23
CPU_HT_CLKNM18
GPP_CLK2NM20
SLT_GFX_CLKPM23
CPU_HT_CLKPP17
LDT_RST#G24
PCICLK0P4
PCICLK1P3
PCICLK2P1
PCICLK3P2
PCIRST#N1
CBE0#W2
CBE1#U7
CBE2#AA7
CBE3#Y1
FRAME#AA6
DEVSEL#W5
IRDY#AA5
TRDY#Y5
PARU6
STOP#W6
PERR#W4
REQ0#AC3
REQ1#AD4
REQ2#AB7
REQ3#/GPIO70AE6
GNT0#AD2
GNT1#AE4
GNT2#AD5
GNT3#/GPIO72AC6
SERR#V7
CLKRUN#AD6
LAD0H24
LAD1H23
LAD2J25
LAD3J24
LFRAME#H25
LDRQ0#H22
SERIRQV15
PCICLK4T4
LPCCLK0G22
LPCCLK1E22
AD0U2
AD1P7
AD2V4
AD3T1
AD4V3
AD5U1
AD6V1
AD7V2
AD8T2
AD9W1
AD10T9
AD12R7
AD13R5
AD14U8
AD15U5
AD16Y7
AD17W8
AD18V9
AD19Y8
AD20AA8
AD21Y4
AD22Y3
AD23Y2
AD24AA2
AD25AB4
AD26AA1
AD27AB3
AD28AB2
AD29AC1
AD30AC2
AD31AD1
AD11R6
REQ4#/GPIO71AB6
GNT4#/GPIO73AE5
LDRQ1#/GNT5#/GPIO68AB8
GPP_CLK1PL20
RTCCLKC3
PCIE_RX3NR17
INTE#/GPIO33AD3
INTF#/GPIO34AC4
INTG#/GPIO35AE2
INTH#/GPIO36AE3
LOCK#V5
PCIE_PVSSP25
PCICLK5/GPIO41T3
BMREQ#/REQ5#/GPIO65AD7
NB_HT_CLKPM24
LDT_PGF22
LDT_STP#G25
GPP_CLK3NP22
INTRUDER_ALERT#C2
NB_DISP_CLKPK23
25M_48M_66M_OSCL18
GPP_CLK0PJ19
NB_HT_CLKNM25
SLT_GFX_CLKNM22
GPP_CLK3PN22
14M_X1J21
14M_X2J20
NB_DISP_CLKNK22
PROCHOT#F24
R316120_0402_5%
1 2
C652
18P_0402_50V8J
1 2
C5051U_0402_6.3V4Z
1
2
J1 JUMP_43X39@
11
22
R389
20M_0402_5%
12
R317120_0402_5%
1 2
R312 33_0402_5%
12
R1109 1K_0402_5%@12
C1087 12P_0402_50V8J
1 2
R302 33_0402_5%
1 2
R306 2.05K_0402_1% 12
R314 20M_0402_5%@
1 2
R967 0_0402_5%
12
T16PAD
R1108 0_0402_5%@12
R319 10K_0402_5%12
T18PAD
C509
0.1U_0402_16V4Z
1
2
C499 0.1U_0402_16V7K 1 2
C493 0.1U_0402_16V7K 1 2
T17PAD
R300 8.2K_0402_5%@1 2
R318 10K_0402_5%@12
D42
DAN202U_SC70
2
31 JBATT1
ACES_85205-02001CONN@
11
22
GND3
GND4
C1085 12P_0402_50V8J@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
NBPWRGD
USB20_N0USB20_P0
USB20_N1USB20_P1
USB20_P2USB20_N2
USB20_P3USB20_N3
USB20_N5USB20_P5
USB20_N6USB20_P6
USB20_P7USB20_N7
USB20_N11USB20_P11
USB20_P10USB20_N10
USB20_N8USB20_P8
SMB_CK_DAT1SMB_CK_CLK1
SUS_STAT#
H_THERMTRIP#
USB_RCOMP
SMB_CK_CLK0
SMB_CK_DAT0
SUS_STAT#
HDA_SDIN1HDA_SDIN0HDA_SDOUT
HDABITCLK
HDA_SYNC
HDARST#
SB_TEST2SB_TEST1SB_TEST0
SB_TEST2
SB_TEST1
SB_TEST0
SMB_CK_DAT0SMB_CK_CLK0
SMB_CK_CLK1
SMB_CK_DAT1
EC_RSMRST#
EXP_CPPE#
NBPWRGD
PCIE_WAKE#
PCIE_WAKE#
CR_CPPE#
SB_GPIO5
HDA_BITCLK_CODEC
HDA_BITCLK_MDC
HDA_SDOUT_MDC
HDA_SDOUT_CODEC
HDABITCLK
HDA_BITCLK
HDA_BITCLK
EC_RSMRST#
EC_LID_OUT#<33>
EC_SCI#<33>
USB20_N0 <31>USB20_P0 <31>
USB20_N1 <31>USB20_P1 <31>
USB20_P2 <31>USB20_N2 <31>
USB20_P3 <35>USB20_N3 <35>
USB20_N5 <17>USB20_P5 <17>
USB20_N6 <31>USB20_P6 <31>
USB20_P7 <31>USB20_N7 <31>
USB20_N11 <26>USB20_P11 <26>
USB20_P10 <26>USB20_N10 <26>
USB20_N8 <26>USB20_P8 <26>
HDARST#<23,33>
SMB_CK_DAT1<26>SMB_CK_CLK1<26>
EC_RSMRST#<33>
SMB_CK_DAT0<8,9,15,30>SMB_CK_CLK0<8,9,15,30>
H_THERMTRIP#<6>
SB_SPKR<28>
CLK_48M_USB <15>
SUS_STAT#<11>
HDA_SDIN0<28>HDA_SDIN1<34>
HDA_SDOUT_MDC<34>HDA_SDOUT_CODEC<28>
HDA_BITCLK_CODEC<28>HDA_BITCLK_MDC<34>
HDA_SYNC_MDC<34>HDA_SYNC_CODEC<28>
HDA_RST#_CODEC<28>HDA_RST#_MDC<34>
SLP_S3#<33>SLP_S5#<33>
PWRBTN_OUT#<33>SB_PWRGD<6,33,43>
KB_RST#<33>GATEA20<33>
EC_SMI#<33>
GPIO16 <23>GPIO17 <23>
EXP_CPPE#<26>
NB_PWRGD<11>
LAN_PCIE_WAKE#<25>
MINI_PCIE_WAKE#<26>
CR_CPPE#<27>
3/5V_OK<39,41>
+3VS
+3VALW
+3VALW
+3VS
+3VALW+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
SB710 USB/AC97
Custom
20 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Touch Screen (delete)
STRAP PIN
USB-0 Right side (S/W Debug Port)
USB-7 Fingerprint
USB-5 USB Camera
USB-10 MiniCard(TV or WWAN)
USB-4 Left side
STRAP PIN
USB-2 Left Side
USB-6 Bluetooth
SB700 has internal PD
USB-3 Dock
USB-1 Right side
USB-11 New Card
USB-8 MiniCard(WLAN)
USB-9 Card Reader (delete)
STRAP PIN
demo circuit LID use RI#
For SB700 A11 divider to 1.8V for RS & RX780
03/05 Add SSC circuit for HDA_BITCLK.
R81 0_0402_5%1 2
C1122
0.1U_0402_16V4Z
@1
2
R321 2.2K_0402_5%@1 2
R1081
10K_0402_5%
@
12R1082
10K_0402_5%
@
12
R32311.8K_0402_1%
1 2
U66
ASM3P623S00BF-08TR_TSSOP8
@
CLKOUT6
VDD7
NC2
CLKIN1
NC8
SS3
SSON5
GND4
C1089 82P_0402_50V8J
1 2
C1091 82P_0402_50V8J
1 2
R339 33_0402_5%
1 2
R337 33_0402_5%
1 2
R322 2.2K_0402_5%@1 2
R82 0_0402_5%
1 2
R54010K_0402_5%
12
R320 2.2K_0402_5%@1 2
R83
10K_0402_5%1 2
R331 2.2K_0402_5% 1 2
R340 33_0402_5%
1 2
US
B 2
.0
Part 4 of 5SB700
AC
PI
/ W
AK
E U
P E
VE
NT
S
GP
IO
HD
AU
DIO
US
B O
C
US
B 1
.1
US
B M
ISC
INT
EG
RA
TE
D u
C
INT
EG
RA
TE
D u
C
U15D
218-0660011 A14 SB7_FCBGA528
USBCLK/14M_25M_48M_OSCC8
USB_RCOMPG8
USB_OC6#/IR_TX1/GEVENT6#B9
USB_HSD5PC12
USB_HSD5ND12
USB_HSD4PB12
USB_HSD4NA12
USB_HSD3PG12
USB_HSD3NG14
USB_HSD2PH14
USB_HSD2NH15
USB_HSD1PA13
USB_HSD1NB13
USB_HSD0PB14
USB_HSD0NA14
USB_OC4#/IR_RX0/GPM4#A8
USB_OC3#/IR_RX1/GPM3#A9
USB_OC1#/GPM1#F8
USB_OC2#/GPM2#E5
USB_HSD7PG11
USB_HSD7NH12
USB_HSD6PE12
USB_HSD6NE14
USB_OC0#/GPM0#E4
DDR3_RST#/GEVENT7#G5
SATA_IS0#/GPIO10AE18
AZ_SDIN3/GPIO46M3
PCI_PME#/GEVENT4#E1
RI#/EXTEVNT0#E2
SLP_S3#F5
SLP_S5#G1
PWR_BTN#H2
PWR_GOODH1
SUS_STAT#K3
TEST1H4
TEST0H3
GA20IN/GEVENT0#Y15
KBRST#/GEVENT1#W15
SMBALERT#/THRMTRIP#/GEVENT2#J6
LPC_PME#/GEVENT3#K4
LPC_SMI#/EXTEVNT1#K24
S3_STATE/GEVENT5#F1
SYS_RESET#/GPM7#J2
WAKE#/GEVENT8#H6
RSMRST#D3
CLK_REQ3#/SATA_IS1#/GPIO6AD18
NB_PWRGDW14
SMARTVOLT1/SATA_IS2#/GPIO4AA19
SMARTVOLT2/SHUTDOWN#/GPIO5Y19
SPKR/GPIO2W21
SCL0/GPOC0#AA18
SDA0/GPOC1#W18
DDC1_SCL/GPIO9AA20
DDC1_SDA/GPIO8Y18
AZ_BITCLKM1
AZ_SDOUTM2
AZ_SYNCL6
AZ_RST#M4
USB_HSD9PA11
USB_HSD9NB11
USB_HSD8PC10
USB_HSD8ND10
LLB#/GPIO66C1
AZ_DOCK_RST#/GPM8#L5
SLP_S2/GPM9#H7
USB_OC5#/IR_TX0/GPM5#B8
BLINK/GPM6#F2
SCL1/GPOC2#K1
SDA1/GPOC3#K2
TEST2H5
CLK_REQ0#/SATA_IS3#/GPIO0W17
AZ_SDIN2/GPIO44L8
AZ_SDIN1/GPIO43J8
AZ_SDIN0/GPIO42J7
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39V17
CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40W20
USB_FSD13PE6
USB_FSD13NE7
USB_FSD12PF7
USB_FSD12NE8
USB_HSD11PH11
USB_HSD11NJ10
USB_HSD10PE11
USB_HSD10NF11
KSO_17B18
IMC_PWM0/IMC_GPIO10F21
SCL2/IMC_GPIO11D21
SDA2/IMC_GPIO12F19
SCL3_LV/IMC_GPIO13E20
SDA3_LV/IMC_GPIO14E21
IMC_PWM1/IMC_GPIO15E19
IMC_PWM2/IMC_GPO16D19
IMC_PWM3/IMC_GPO17E18
KSI_0G20
KSI_1G21
KSI_2D25
KSI_3D24
KSI_4C25
KSI_5C24
KSI_6B25
KSI_7C23
PS2_DATH19
PS2_CLKH20
SPI_CS2#/IMC_GPIO2H21
IDE_RST#/F_RST#/IMC_GPO3F25
PS2KB_DATD22
PS2KB_CLKE24
PS2M_DATE25
PS2M_CLKD23
KSO_16A18
KSO_0B24
KSO_1B23
KSO_2A23
KSO_3C22
KSO_4A22
KSO_5B22
KSO_6B21
KSO_7A21
KSO_8D20
KSO_9C20
KSO_10A20
KSO_11B20
KSO_12B19
KSO_13A19
KSO_14D18
KSO_15C18
R1080 0_0402_5%
1 2
R336 33_0402_5%
1 2
R329 1.2K_0402_5% 1 2
R108310K_0402_5%@
12
R333 33_0402_5%
1 2
R10520_0402_5%
12
C1088 82P_0402_50V8J
1 2
R3272.2K_0402_5%
12
R335 33_0402_5%
1 2
R338 33_0402_5%
1 2
R332 2.2K_0402_5% 1 2
T19PAD
R328 1.2K_0402_5% 1 2
C1090 82P_0402_50V8J
1 2
R994 0_0402_5%@12
R1053100_0402_5%@
12
R334 33_0402_5%
1 2
D58
CH751H-40PT_SOD323-2
21
R993 47_0402_5%
12
R388 4.7K_0402_5%
1 2
T41PAD
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+PLLVDD_SATA
+XTLVDD_SATA
LFB_ID1LFB_ID2
LFB_ID0
+SB_AVDD
LFB_ID2
THERMAL_DC
SATA_STX_DRX_P1SATA_STX_DRX_N1
SATA_STX_DRX_P0SATA_STX_DRX_N0
SATA_X2
SATA_X1
SATA_CAL
LFB_ID1
LFB_ID0
SATA_X2
SATA_X1
SATA_STX_DRX_P2SATA_STX_DRX_N2
SATA_STX_DRX_P3SATA_STX_DRX_N3
AC_IN_SB
SATA_TXP0<24>SATA_TXN0<24>
SATA_RXP0_C<24>SATA_RXN0_C<24>
SATA_LED#<34>
SATA_TXP1<24>SATA_TXN1<24>
SATA_RXP1_C<24>SATA_RXN1_C<24>
EC_THERM# <33>
CAM_SHDN# <17>BT_OFF <31>
SATA_TXP2<31>SATA_TXN2<31>
SATA_RXP2_C<31>SATA_RXN2_C<31>
WLOFF# <26>BT_COMBO_EN# <26>WWOFF# <26>
SATA_TXP3<24>SATA_TXN3<24>
SATA_RXP3_C<24>SATA_RXN3_C<24>
HDD_HALTLED# <34>SB_INT_FLASH_SEL
CR_WAKE# <27>
AC_IN <33,38>
+3VALW
+3VS
+1.2V_HT
+3VS
+3VALW
+3VALW
+3VALW
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
SB710 SATA/IDE/SPI
Custom
21 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
LFB_ID0 to LFB_ID2 got internal PU 10K to S5.
Hynix
Qimonda
Samsung
LFB_ID0LFB_ID1LFB_ID2
0 0 0
0 0 1
0 01
Local Frame Buffer Strapping ListCopy from Becks.
02/18 Add R1071 and D56 to connect to AC_IN.
R1071
150K_0402_5%
12
C51710P_0402_50V8J
12
C523
1U_0402_6.3V4Z
1
2
D56CH751H-40PT_SOD323-2
2 1
R1062 0_0402_5%
1 2
R342 1K_0402_1%
12
R344 1K_0402_5%1 2
C5262.2U_0603_6.3V4Z
1
2
L56
BLM18PG121SN1D_0603 12
AT
A 6
6/1
00
/13
3
Part 2 of 5
SB700
SA
TA
PW
RS
ER
IAL
AT
A
SP
I R
OM
HW
MO
NIT
OR
U15B
218-0660011 A14 SB7_FCBGA528
IDE_IORDYAA24
IDE_IRQAA25
IDE_A0Y22
IDE_A1AB23
IDE_A2Y23
IDE_DACK#AB24
IDE_DRQAD25
IDE_IOR#AC25
IDE_IOW#AC24
IDE_CS1#Y25
IDE_CS3#Y24
IDE_D0/GPIO15AD24
IDE_D1/GPIO16AD23
IDE_D2/GPIO17AE22
IDE_D3/GPIO18AC22
IDE_D4/GPIO19AD21
IDE_D5/GPIO20AE20
IDE_D6/GPIO21AB20
IDE_D7/GPIO22AD19
IDE_D8/GPIO23AE19
IDE_D9/GPIO24AC20
IDE_D10/GPIO25AD20
IDE_D11/GPIO26AE21
IDE_D12/GPIO27AB22
IDE_D13/GPIO28AD22
IDE_D14/GPIO29AE23
IDE_D15/GPIO30AC23
XTLVDD_SATAW12
PLLVDD_SATAAA11
SATA_TX2PAB12
SATA_TX2NAC12
SATA_RX2PAD12
SATA_RX2NAE12
SATA_TX3PAD13
SATA_TX3NAE13
SATA_RX3PAC14
SATA_RX3NAB14
SATA_TX0PAD9
SATA_TX0NAE9
SATA_RX0NAB10
SATA_RX0PAC10
SATA_TX1PAE10
SATA_TX1NAD10
SATA_RX1NAD11
SATA_RX1PAE11
SATA_CALV12
SATA_X1Y12
SATA_X2AA12
SATA_ACT#/GPIO67W11
SPI_DI/GPIO12G6
SPI_DO/GPIO11D2
SPI_CLK/GPIO47D1
SPI_HOLD#/GPIO31F4
SPI_CS1#/GPIO32F3
FANOUT1/GPIO48M5
FANOUT2/GPIO49M7
FANIN0/GPIO50P5
FANIN1/GPIO51P8
FANIN2/GPIO52R8
LAN_RST#/GPIO13U15
ROM_RST#/GPIO14J1
VIN0/GPIO53A4
VIN1/GPIO54B4
VIN2/GPIO55C4
VIN3/GPIO56D4
VIN4/GPIO57D5
VIN5/GPIO58D6
VIN6/GPIO59A7
VIN7/GPIO60B7
TEMPIN0/GPIO61B6
TEMPIN1/GPIO62A6
TEMPIN2/GPIO63A5
TEMPIN3/TALERT#/GPIO64B5
FANOUT0/GPIO3M8
AVDDF6
AVSSG7
TEMP_COMMC6
SATA_TX4PAE14
SATA_TX4NAD14
SATA_RX4NAD15
SATA_RX4PAE15
SATA_TX5PAB16
SATA_TX5NAC16
SATA_RX5NAE16
SATA_RX5PAD16
C5250.1U_0402_16V4Z
1
2
R367 10K_0402_5%1 2
L54
BLM18PG121SN1D_0603 12
C512 0.01U_0402_25V7K
1 2
R341
10M_0402_5%
12
C5221U_0402_6.3V4Z
1
2
C520 1000P_0402_50V7K
1 2
R1032
1K_0402_5%@1 2
C513 0.01U_0402_25V7K
1 2
C519 0.01U_0402_25V7K
1 2
L55
BLM18PG121SN1D_0603 12
Y4
25MHz_20pF_6X25000017
12
C515 0.01U_0402_25V7K
1 2
R343 10K_0402_5%
1 2
R345 10K_0402_5%1 2
C521 1000P_0402_50V7K
1 2
R10331K_0402_5%@
1 2
C5241U_0402_6.3V4Z
1
2
C518 0.01U_0402_25V7K
1 2
C514 0.01U_0402_25V7K
1 2
C51610P_0402_50V8J
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
+AVDDCK_1.2V
+1.2V_CKVDD
+AVDDCK_3.3V
+V5_VREF
+S5_3V
+AVDDCK_3.3V
+AVDDCK_1.2V
+AVDDC
+S5_1.2V
+1.2V_SB_CORE
+1.2_USB
+3.3V_SB_IDE
+3VS
+1.2V_HT
+1.2V_HT
+3VALW
+3VS
+3VS
+5VS
+1.2V_HT
+1.2V_HT
+PCIE_VDDR
+1.2V_SATA
+3VALW
+AVDD_USB
+1.2VALW
+1.2VALW
+1.2V_HT
+1.2VALW
+3VALW
+3VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
SB710 PWR/GND
Custom
22 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
L 0.45A/40mil/3vias ?
L 0.45A/30mil/3vias
L 0.8A/50mil/4vias
L <1.25A/50mil/4vias
L <1.25A/50mil/4vias?
L 0.6A/50mil/4vias
L 0.3A/30mil/2vias
L 0.1A/30mil/2vias ?
L C567,C568 change to 1U_0402 when SI-2
L69
0_0805_5%12
C544 1U_0402_6.3V4Z@1 2
C5621U_0402_6.3V4Z
12
C5791U_0603_10V4Z
1
2
C560 0.1U_0402_16V4Z
1 2
C580 1U_0402_6.3V4Z
1 2
C547 1U_0402_6.3V4Z@1 2
L63
0_0805_5%12
C539 1U_0402_6.3V4Z
1 2
C582 0.1U_0402_16V4Z
1 2
R592 0_0805_5%@1 2
C581 1U_0402_6.3V4Z
1 2
C535 1U_0402_6.3V4Z
1 2
C55622U_0805_6.3V6M
1 2
SB700
GR
OU
ND
Part 5 of 5
U15E
218-0660011 A14 SB7_FCBGA528
VSS_4D7
VSS_2A25
VSS_21M13
VSS_10K16
VSS_11L4
VSS_1A2
VSS_17L16
VSS_8K9
VSS_9K11
VSS_46AB1
VSS_13L10
VSS_14L11
VSS_15L12
VSS_16L14
VSS_18M6
VSS_19M10
VSS_20M11
VSS_22M15
VSS_23N4
VSS_26P6
VSS_27P9
VSS_28P10
VSS_29P11
VSS_32R1
VSS_33R2
VSS_34R4
VSS_36R10
VSS_37R12
VSS_3B1
VSS_35R9
VSS_30P13
AVSS_SATA_15AB13
AVSS_SATA_18AC8
AVSS_SATA_5V11
AVSS_SATA_11Y17
AVSS_SATA_19AD8
VSS_31P15
VSS_24N12
AVSS_SATA_14AB11
AVSS_SATA_2U10
AVSS_SATA_3U11
AVSS_SATA_1T10
AVSS_SATA_17AB17
AVSS_SATA_4U12
AVSS_SATA_12AA9
AVSS_SATA_6V14
AVSS_SATA_10Y14
AVSS_SATA_7W9
AVSS_SATA_8Y9
AVSS_SATA_16AB15
AVSS_SATA_20AE8
AVSS_SATA_13AB9
AVSS_USB_5D9
AVSS_USB_8D14
AVSS_USB_4D8
AVSS_USB_3C14
AVSS_USB_6D11
AVSS_USB_7D13
AVSS_USB_2B15
AVSS_USB_21K10
AVSS_USB_10E15
AVSS_USB_20J15
AVSS_USB_22K12
AVSS_USB_11F12
AVSS_USB_12F14
AVSS_USB_23K14
AVSS_USB_16J9
AVSS_USB_15H17
AVSS_USB_19J14
AVSS_USB_14H9
AVSS_USB_1A15
AVSS_USB_24K15
VSS_12L7
AVSS_USB_17J11
AVSS_USB_18J12
VSS_7H8
VSS_25N14
VSS_6G19
AVSS_USB_13G9
AVSS_USB_9D15
AVSSCKL17
PCIE_CK_VSS_3J22
PCIE_CK_VSS_14U20
PCIE_CK_VSS_13U18
PCIE_CK_VSS_12T17
PCIE_CK_VSS_18W19
PCIE_CK_VSS_6M17
PCIE_CK_VSS_11R19
PCIE_CK_VSS_8P16
PCIE_CK_VSS_7M21
PCIE_CK_VSS_17V21
PCIE_CK_VSS_16V20
PCIE_CK_VSS_15V18
VSS_50AE24
PCIE_CK_VSS_21W25
PCIE_CK_VSS_19W22
PCIE_CK_VSS_20W24
AVSSCF9
PCIE_CK_VSS_2J17
PCIE_CK_VSS_1H18
PCIE_CK_VSS_4K25
VSS_5F20
PCIE_CK_VSS_5M16
PCIE_CK_VSS_9P23
PCIE_CK_VSS_10R16
VSS_49AE1
VSS_44V6
VSS_45Y21
VSS_42U4
VSS_48AB25
VSS_47AB19
VSS_41T14
VSS_43U14
VSS_38R14
VSS_39T11
VSS_40T12
AVSS_SATA_9Y11
C5630.1U_0402_16V4Z
12
C576 10U_0805_10V4Z
1 2
C5381U_0402_6.3V4Z
12
C5270.1U_0402_16V4Z
12
L64 0_0603_5%
R120_0603_5%@
1 2
Part 3 of 5
SB700
POWER
PC
I/G
PIO
I/O
CO
RE
S0
3.3
V_
S5
I/O
CO
RE
S5
A-L
INK
I/O
SA
TA
I/O
US
B I
/O PL
LC
LK
GE
N I
/O
IDE
/FL
SH
I/O
U15C
218-0660011 A14 SB7_FCBGA528
VDDQ_2M9
VDDQ_6U17
VDDQ_3T15
VDDQ_11AB5
VDDQ_1L9
VDDQ_4U9
VDDQ_5U16
VDDQ_12AB21
VDDQ_10AA4
VDDQ_7V8
VDDQ_8W7
VDDQ_9Y6
S5_3.3V_1A17
S5_3.3V_2A24
S5_3.3V_3B17
S5_3.3V_4J4
S5_3.3V_5J5
S5_1.2V_2G4
S5_1.2V_1G2
USB_PHY_1.2V_1A10
USB_PHY_1.2V_2B10
V5_VREFAE7
AVDDCK_3.3VJ16
AVDDCK_1.2VK17
AVDDCE9
AVDDTX_0A16
AVDDTX_1B16
AVDDTX_2C16
AVDDTX_3D16
AVDDTX_5E17
AVDDTX_4D17
AVDDRX_2F18
AVDDRX_0F15
AVDDRX_5G18
AVDDRX_4G17
PCIE_VDDR_4P21
PCIE_VDDR_3P20
PCIE_VDDR_7R25
PCIE_VDDR_2P19
PCIE_VDDR_5R22
PCIE_VDDR_1P18
PCIE_VDDR_6R24
AVDD_SATA_1AA14
AVDD_SATA_4AB18
AVDD_SATA_2AA15
AVDD_SATA_3AA17
AVDD_SATA_5AC18
AVDD_SATA_6AD17
AVDD_SATA_7AE17
VDD_1L15
VDD_2M12
VDD_3M14
VDD_4N13
VDD_5P12
VDD_6P14
VDD_7R11
VDD_9T16
VDD_8R15
AVDDRX_1F17
AVDDRX_3G15
VDD33_18_2AA21
VDD33_18_4AE25
VDD33_18_3AA22
VDD33_18_1Y20
CKVDD_1.2V_2L22
CKVDD_1.2V_1L21
CKVDD_1.2V_4L25
CKVDD_1.2V_3L24
S5_3.3V_7L2
S5_3.3V_6L1
C550 10U_0805_10V4Z
1 2
L61
0_0805_5%12
C57310U_0805_10V4Z
1 2
C5741U_0402_6.3V4Z
12
C5650.1U_0402_16V4Z
12
C5880.1U_0402_16V4Z 12
C552 4.7U_0805_10V4Z
12
C52910U_0805_6.3V6M
1 2
L66
0_0805_5%12
L67
0_0805_5%12
C5900.1U_0402_16V4Z 12
C5860.1U_0402_16V4Z 12
C5341U_0402_6.3V4Z
12
L60
0_0805_5%12
C548 0.1U_0402_16V4Z 12
C533 1U_0402_6.3V4Z
1 2
C568 1U_0805_16V7K
1 2
C558 1U_0402_6.3V4Z
1 2
C542 0.1U_0402_16V4Z
1 2
R3461K_0402_5%
12D14
CH751H-40PT_SOD323-2
21
C5611U_0402_6.3V4Z
12
C549 1U_0402_6.3V4Z
1 2
C5852.2U_0603_6.3V4Z
12
C5691U_0402_6.3V4Z
12
C571 0.1U_0402_16V4Z
1 2
C528 22U_0805_6.3V6M
12
C5591U_0402_6.3V4Z
12
R564 0_0805_5%1 2
C5751U_0402_6.3V4Z
12
C5780.1U_0402_16V4Z
1
2
C584 0.1U_0402_16V4Z
1 2
C5700.1U_0402_16V4Z
12
C566 22U_0805_6.3V6M
12
L65 0_0603_5%
C555 1U_0402_6.3V4Z
1 2
C583 0.1U_0402_16V4Z
1 2
C546 1U_0402_6.3V4Z
1 2
C5371U_0402_6.3V4Z
12
C543 22U_0805_6.3V6M@12
C567 1U_0805_16V7K
1 2
C557 0.1U_0402_16V4Z
1 2
C545 1U_0402_6.3V4Z
1 2
C554 1U_0402_6.3V4Z
1 2
C531 1U_0402_6.3V4Z
1 2
C536 1U_0402_6.3V4Z@1 2
C530 1U_0402_6.3V4Z
1 2
C551 0.1U_0402_16V4Z 12
L68
0_0805_5%12
C572 0.1U_0402_16V4Z
1 2
C5640.1U_0402_16V4Z
12
C5892.2U_0603_6.3V4Z
12
C5872.2U_0603_6.3V4Z
12
C553 1U_0402_6.3V4Z
1 2
C5321U_0402_6.3V4Z
12
C541 0.1U_0402_16V4Z
1 2
R593 0_0805_5%1 2
C577 10U_0805_10V4Z
1 2
C5400.1U_0402_16V4Z
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PCI_AD28<19>PCI_AD27<19>PCI_AD26<19>PCI_AD25<19>PCI_AD24<19>PCI_AD23<19>
PCICLK2<19>PCI_CLK3<19>
PCI_CLK4<19>PCI_CLK5<19>
CLK_PCI_EC<19,33>LPCCLK1<19>RTC_CLK<19>HDARST#<20,33>
GPIO17<20>GPIO16<20>
+3VS +3VS +3VS +3VS +3VALW +3VALW +3VALW +3VALW +3VALW +3VALW
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
SB700 STRAPS
Custom
23 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Internal pull up
RESERVED
DEBUG STRAPS
PCI_AD25 PCI_AD24
USE EEPROMPCIE STRAPS
USE DEFAULTPCIE STRAPS
DEFAULT
BYPASSACPIBCLK
USE ACPIBCLK
DEFAULT
USE IDEPLL
USELONGRESET
USESHORTRESET
USE PCIPLL
DEFAULT
BYPASS IDEPLL
PULLHIGH
DEFAULT
BYPASSPCI PLL
PCI_AD27 PCI_AD26
PULLLOW
DEFAULT
PCI_AD28
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]
PCI_AD23
LPC_CLK0
ENABLE PCIMEM BOOT
EXT. RTC (PD on X1,apply32KHz toRTC_CLK)DEFAULT
GP17
NOTE: SB700 HAS INTERNAL 15K PULL UP RESISTOR FOR RTC_CLK
DISABLE PCIMEM BOOT
PULLLOW
PULLHIGH
REQUIRED STRAPS
INTERNALRTC
DEFAULT
RTC_CLKLPC_CLK1
CLKGENENABLED
DEFAULT
CLKGENDISABLED
AZ_RST_CD#
ECENABLED
ECDISABLED
DEFAULT
GP16PCI_CLK2
BOOTFAILTIMERENABLED
DEFAULT
BOOTFAILTIMERDISABLED
PCI_CLK3
RESERVED
DEFAULT
IGNOREDEBUGSTRAPS
USEDEBUGSTRAPS
PCI_CLK4 PCI_CLK5
RESERVED
L,H = LPC ROM (Default)
H,H = Reserved
H,L = SPI ROM
L,L = FWH ROM
R3
49
10
K_
04
02
_5
%
@
12
R3
58
10
K_
04
02
_5
%
12
R3
47
10
K_
04
02
_5
%
@
12
R3
74
2.2
K_
04
02
_5
%
@
12
R3
48
10
K_
04
02
_5
%
@
12
R3
64
10
K_
04
02
_5
%
12
R3
76
2.2
K_
04
02
_5
%
@
12
R3
53
10
K_
04
02
_5
%
@
12
R3
65
2.2
K_
04
02
_5
%
12
R3
78
2.2
K_
04
02
_5
%
@
12
R3
51
10
K_
04
02
_5
%
@
12
R3
61
10
K_
04
02
_5
%
12
R356
2.2K_0402_5%
12
R3
57
10
K_
04
02
_5
%
12
R3
62
10
K_
04
02
_5
%
12
R3
73
2.2
K_
04
02
_5
%
@
12
R3
60
10
K_
04
02
_5
%
@
12
R3
77
2.2
K_
04
02
_5
%
@
12
R3
59
10
K_
04
02
_5
%
@
12
R3
63
2.2
K_
04
02
_5
%
@
12
R3
75
2.2
K_
04
02
_5
%
@
12
R3
55
10
K_
04
02
_5
%
@
12
R3
54
10
K_
04
02
_5
%
@
12
R3
66
2.2
K_
04
02
_5
%
@
12
R3
52
10
K_
04
02
_5
%
@
12
R3
50
10
K_
04
02
_5
%
@
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SATA_RXP1 SATA_RXP1_C
SATA_TXP1SATA_TXN1
SATA_RXN1 SATA_RXN1_C
SATA_RXP0_CSATA_RXP0SATA_RXN0 SATA_RXN0_C
SATA_TXP0SATA_TXN0
SATA_TXP3SATA_TXN3
SATA_RXP3_CSATA_RXN3 SATA_RXN3_CSATA_RXP3
SATA_RXP1_C <21>
SATA_TXP1 <21>SATA_TXN1 <21>
SATA_RXN1_C <21>
SATA_RXN0_C <21>SATA_RXP0_C <21>
SATA_TXN0 <21>SATA_TXP0 <21>
SATA_TXP3 <21>SATA_TXN3 <21>
SATA_RXN3_C <21>SATA_RXP3_C <21>
+5VS
+5VS
+5VS
+3VS +3VS_HDD1
+5VS
+5VS
+3VS_HDD1
+5VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
HDD/CDROM
Custom
24 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
CD-ROM Connector
Placea caps. near ODD CONN.
Multi-Bay Connector-option
Place close to Multi-BayConnector-option JP10
HDD Connector
Pleace near HD CONN (JP23)
Pleace near HD CONN (JP23)
Max 3A
Near CONN side.
Near CONN side.
Near CONN side.
C591
0.1U_0402_16V4Z
1
2
C5
95
0.1
U_
04
02
_1
6V
4Z
1
2
R1009
0_0805_5%
@
1 2
R970 0_0402_5%
1 2
JP10
TYCO_2023087-3
CONN@
GND1
VCC54
VCC52
TX-5
TX+3
VCC56
GND7
VCC38
RX-9
VCC310
RX+11
VCC312
GND13
GND14
GND15
GND16
GND17
GND18
C603
0.1U_0402_16V4Z
PA@
1
2
C1
03
21
0U
_0
80
5_
10
V4
Z
@
1
2
C594
0.1U_0402_16V4Z
1
2
C6110.01U_0402_16V7K
12
C6
14
1U
_0
60
3_
10
V4
Z
1
2
C6050.01U_0402_16V7K
12
+C600
150U_Y_6.3VM@
1
2
C6060.01U_0402_16V7K
12
C601
10U_0805_10V4Z
PA@
1
2
C6
13
0.1
U_
04
02
_1
6V
4Z
1
2
C1
03
50
.1U
_0
40
2_
16
V4
Z
@
1
2
C1033
0.1U_0402_16V4Z
@
1
2
C602
0.1U_0402_16V4Z
PA@
1
2
C6
15
10
U_
08
05
_1
0V
4Z
1
2
C61610U_0805_10V4Z
1
2
JP9
SUYIN_127072FR022G523_RVCONN@
GND1
A+2
A-3
GND4
B-5
B+6
GND7
V338
V339
V3310
GND11
GND12
GND13
V514
V515
V516
GND17
Reserved18
GND19
V1220
V1221
V1222
C6120.01U_0402_16V7K
12
C1034
0.1U_0402_16V4Z
@
1
2
JP11
SUYIN_127382FR013G509ZRCONN@
GND1
A+2
A-3
GND4
B-5
B+6
GND7
DP8
V59
V510
MD11
GND12
GND13
C5960.01U_0402_16V7K
12
C604
0.1U_0402_16V4Z
PA@ 1
2
C5
93
10
U_
08
05
_1
0V
4Z
1
2
C5920.01U_0402_16V7K
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
LAN_SK_LAN_LINK#
LAN_MDI0+LAN_MDI0-
LANGND
RJ45_MIDI1-
RJ45_MIDI0+
LAN_ACTIVITY#
RJ45_MIDI1+
RJ45_MIDI0-
LAN_CT0
RJ45_MIDI0+RJ45_MIDI0-
LAN_MDI1+
LAN_X1 LAN_X2
RJ45_CT0
LAN_MDI1-
RJ45_CT1
RJ45_MIDI1-RJ45_MIDI1+
LAN_CT1
VCTRL12
LAN_CSLAN_SK_LAN_LINK#LAN_DI
LAN_ACTIVITY#
VCTRL12
LAN_MDI1+LAN_MDI1-
LAN_MDI0-LAN_MDI0+
ISOLATEB
LAN_X2LAN_X1
ISOLATEB
PCIE_PTX_IRX_P3
PCIE_PTX_IRX_N3
LAN_DI
LAN_CS
RJ45_GNDRJ45_CT0_CRJ45_CT1_C
LAN_ACTIVITY#LAN_SK_LAN_LINK#
RJ45_MIDI0+ <35>RJ45_MIDI0- <35>
RJ45_MIDI1- <35>RJ45_MIDI1+ <35>
PCIE_ITX_C_PRX_P3<10>
PCIE_ITX_C_PRX_N3<10>
CLK_PCIE_LAN#<15>CLK_PCIE_LAN<15>
CLKREQ_LAN#<15>
PLT_RST#<11,14,19,26,27,32,33>
LAN_PCIE_WAKE#<20>
PCIE_PTX_C_IRX_P3<10>
PCIE_PTX_C_IRX_N3<10>
LAN_POWER_OFF<33>
+3V_LAN
+3V_LAN
+3V_LAN
+LAN_VDD12
+LAN_VDD12
+EVDD12
+EVDD12+LAN_VDD12
+3VS
+LAN_VDD12
+3V_LAN
+3V_LAN
+3VALW
+3V_LAN
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
RTL8111C/8102E 10/100/1000 LAN
Custom
25 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
LAN Conn.
9/20 DC234001G00
Close to Pin48
Close to Pin1,37,29
Close to Pin45
Close to Pin10,13,30,36
Close to Pin19
Place Close to Chip
40 mils
C1084 0.01U_0603_100V7-M
1 2
R395 300_0402_5%12
R1057 0_0402_5%1 2
C621
0.1U_0402_16V4Z1
2
JRJ45
FOX_JM36113-P1122-7FCONN@
PR1-2
PR1+1
PR2+3
PR3+4
PR3-5
PR2-6
PR4+7
PR4-8
Green LED-12
Green LED+11
Yellow LED-14
Yellow LED+13
SHLD115
SHLD116
DETECT PIN19
DETCET PIN210
G
DS
Q144SI2301BDS-T1-E3_SOT23-3
2
13
C631
0.1U_0402_16V4Z1
2C628
0.1U_0402_16V4Z1
2
C1081
1U_0402_6.3V4Z1
2
C6320.1U_0402_16V4Z
1
2
R1059 2.49K_0402_1%1 2
C620
0.1U_0402_16V4Z1
2
R1067 0_0805_5%@1 2
C647 0.01U_0402_16V7K
1 2
R1056
100K_0402_5%
@
12
R39475_0402_1%
1 2
C658
1000P_1206_2KV7K
1
2
C1083 0.01U_0603_100V7-M
1 2
C63310U_0805_10V4Z@
1
2
R391 300_0402_5%12
C65768P_0402_50V8K
@
1
2
C662
4.7U_0805_10V4Z
1
2
R1055 3.6K_0402_5%1 2
Y5
25MHz_20pF_6X25000017
12
C1082
0.1U_0402_16V4Z1
2
R106115K_0402_5%
C488 0.1U_0402_16V7K 12
R10601K_0402_1%
12 C1080
0.1U_0402_16V4Z
1
2
C65668P_0402_50V8K@
1
2
C485 0.1U_0402_16V7K 12
C648 0.01U_0402_16V7K
1 2
C622
0.1U_0402_16V4Z1
2
R39675_0402_1%
1 2
C654
27P_0402_50V8J
1
2
C1077
0.1U_0402_16V4Z
@
1
2
C630
0.1U_0402_16V4Z1
2
C661
0.1U_0402_16V4Z
1
2
C653
27P_0402_50V8J
1
2
R1058 10K_0402_5%12
C629
0.1U_0402_16V4Z1
2
D55
PACDN042Y3R_SOT23-3
@
231
U19
NS681680
RD+1
RD-2
CT3
CT6
TD+7
TD-8
TX-9
TX+10
CT11
CT14
RX-15
RX+16
NC4
NC5
NC13
NC12
RTL8102EL
U44
RTL8103EL-GR_LQFP48_7X7
AVDD331
MDIP02
MDIN03
NC4
MDIP15
MDIN16
GND7
NC8
NC9
DVDD1210
NC11
NC12
RSET46
VCTRL12A48
GND47
CKXTAL242
CKXTAL141
NC40
NC44
LED038
VDD3337
NC43
DVDD1213
GND14
HSIP15
HSIN16
REFCLK_P17
REFCLK_M18
VDDTX19
HSOP20
HSON21
GNDTX22
NC23
NC24
LED1/EESK35
LED2/EEDI/AUX34
LED3/EEDO33
EECS32
DVDD1236
GND31
DVDD1230
VDD3329
ISOLATEB28
PERSTB27
LANWAKEB26
CLKREQB25
NC39
VCTRL12D45
C1079
10U_0805_10V4Z@
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SMB_CK_DAT1SMB_CK_CLK1
MINI_PCIE_WAKE#
CLKREQ_NCARD#
PERST#
EXP_CPPE#
EXP_CPPE#
PERST#
PLT_RST#
PLT_RST#
SMB_CK_CLK1SMB_CK_DAT1
WW_LED#
UIM_RST
UIM_PWR
UIM_CLKUIM_DATA
UIM_VPP
WW_OFF#
WL_LED#
PLT_RST#
SMB_CK_DAT1SMB_CK_CLK1
CH_DATACH_CLK
MINI_PCIE_WAKE#
WL_OFF#
EXP_CPPE#
CH_CLK
UIM_PWRUIM_DATA
UIM_RST
UIM_PWRUIM_DATA
UIM_VPP
WW_OFF#
WL_OFF#
UIM_CLK UIMCLK
SMB_CK_CLK1<20>SMB_CK_DAT1<20>
CLK_PCIE_NCARD<15>
USB20_P11<20>USB20_N11<20>
PCIE_ITX_C_PRX_N0<10>PCIE_ITX_C_PRX_P0<10>
PCIE_PTX_C_IRX_P0<10>PCIE_PTX_C_IRX_N0<10>
CLK_PCIE_NCARD#<15>
CLKREQ_NCARD#<15>
PLT_RST#<11,14,19,25,27,32,33>
SUSP#<28,33,36,38,41>
SYSON<33,36,40>
USB20_N10 <20>USB20_P10 <20>
CLKREQ_MCARD1#<15>
CLK_PCIE_MCARD1<15>CLK_PCIE_MCARD1#<15>
PCIE_PTX_C_IRX_P5<10>PCIE_PTX_C_IRX_N5<10>
PCIE_ITX_C_PRX_P5<10>PCIE_ITX_C_PRX_N5<10>
MINI_PCIE_WAKE#<20>
WW_LED# <34>
WL_LED# <34>
USB20_P8 <20>USB20_N8 <20>
CLKREQ_MCARD2#<15>
CH_DATA<31>CH_CLK<31>
CLK_PCIE_MCARD2<15>CLK_PCIE_MCARD2#<15>
PCIE_PTX_C_IRX_P2<10>PCIE_PTX_C_IRX_N2<10>
PCIE_ITX_C_PRX_N2<10>PCIE_ITX_C_PRX_P2<10>
EXP_CPPE#<20>
BT_COMBO_EN#<21>
WWAN_POWER_OFF<33>
WWOFF# <21>
WLOFF# <21>
+3VS_PEC
+1.5VS_PEC
+3V_PEC
+3VS_PEC
+3V_PEC
+1.5VS_PEC
+3VS_MINI +1.5VS_MINI+3VALW_WWAN+3VS_MINI+3VALW +3VS +1.5VS
+1.5VS_PEC
+3V_PEC
+3VS_PEC
+3VALW
+1.5VS
+3VS
+3VALW_WWAN
+3VS_MINI
+1.5VS_MINI
+3VS_MINI
+3VALW_WLAN
+3VS_WLAN
+1.5VS_WLAN
+3VS_WLAN+3VALW
+3VS +1.5VS+3VS_WLAN +1.5VS_WLAN +3VALW_WLAN
+3VS_WLAN
+3VS_MINI
+3VS_MINI+3VALW
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
WLAN/TV tuner/Express Card
Custom
26 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Express Card Power Switch
Mini Card Slot 1---TV tuner / WWAN / Robson
New Card
Near to Express Card slot.USE TI TPS2231MRGPR
9/20 SP02000B000
9/20 SP01000HS00/SP01000LX00
9/20 STANDOFF (H=7.5 mm) ES000000D00
9/20 SP02000IQ00
Mini Card Slot 2---WLAN
9/20 STANDOFF (H=7.5 mm) ES000000D00
9/20 SP01000HS00/SP01000LX00
Max 2.7A
Max 1.3A
Max 0.65A
Max 0.3A Max 0.3A
Max 0.5A
Max 1A Max 0.5A
Max 0.275A
R4060_0805_5%1 2
L78
0_1206_5%
PA@
1 2C665
0.1U_0402_16V4Z
1
2
R47 0_0603_5%1 2
C7840.1U_0402_16V7K@
1
2
JP6
ACES_88266-07001
CONN@
11
22
33
44
55
66
77
G18
G29
C782
0.1U_0402_16V4Z
PA@ 1
2
C677
0.1U_0402_16V4Z
RP@1
2
C787
4.7U_0805_10V4Z
PA@ 1
2
R421
33_0402_5% 1 2
C1071
4.7U_0805_10V4Z
PA@1
2
C669
0.1U_0402_16V4Z
1
2
R540_0402_5%
RP@
1 2
C670
4.7U_0805_10V4Z
1
2 C781
0.01U_0402_16V7K
PA@ 1
2
R1043 0_0603_5%@
1 2
C109439P_0402_50V8J
PA@1
2
R48
4.7K_0402_5%
12
R1042 0_0603_5%
1 2
C683
0.1U_0402_16V4Z
RP@1
2
JEXP
SANTA_130801-5_LTCONN@
GND1
USB_D-2
USB_D+3
CPUSB#4
RSV5
RSV6
SMB_CLK7
SMB_DATA8
+1.5V9
+1.5V10
WAKE#11
+3.3VAUX12
PERST#13
+3.3V14
+3.3V15
CLKREQ#16
CPPE#17
REFCLK-18
REFCLK+19
GND20
PERn021
PERp022
GND23
PETn024
PETp025
GND26
GND27
GND28
C671
0.1U_0402_16V4Z
PA@1
2
C1070
0.1U_0402_16V4Z
PA@1
2
R972 0_0603_5%@
12
U21
R5538D001-TR-F_QFN20_4X4~D
RP@
3.3Vin2
3.3Vin4
3.3Vout3
3.3Vout5
SYSRST#6
SHDN#20
STBY#1
PERST#8
OC#19
RCLKEN18
AUX_IN17
AUX_OUT15
CPPE#10
CPUSB#9
NC16
GND7
1.5Vin12
1.5Vin14
1.5Vout11
1.5Vout13
THERMAL_PAD21
C783
4.7U_0805_10V4Z
PA@ 1
2
C786
0.1U_0402_16V4Z
PA@ 1
2
C109339P_0402_50V8J
PA@1
2
L79
0_0805_5%
PA@
12
C684
0.1U_0402_16V4Z
RP@1
2
JP14
FOX_AS0B226-S99N-7FCONN@
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
4141
4242
4343
4444
4545
4646
4747
4848
4949
5050
5151
5252
11
22
G1
53
G2
54
G3
55
G3
56
R971 0_0603_5%PA@
12C666
4.7U_0805_10V4Z
1
2
C667
0.1U_0402_16V4Z
1
2
C6790.1U_0402_16V4Z
RP@
12
C685
4.7U_0805_10V4Z
RP@1
2
C6800.1U_0402_16V4Z
RP@
12
C785
0.01U_0402_16V7K
PA@ 1
2
D59CH751H-40PT_SOD323-2
2 1
C109239P_0402_50V8J
PA@
1
2
R1087 0_0603_5%@
1 2
C109539P_0402_50V8J
PA@
1
2
R49
0_0402_5%
1 2
G
D S
Q167
SI2301BDS-T1-E3_SOT23-3
@
2
1 3
C73839P_0402_50V8J
PA@
1
2
D60CH751H-40PT_SOD323-2
2 1
R401 0_0603_5%PA@
1 2
C682
4.7U_0805_10V4Z
RP@1
2
C109639P_0402_50V8J
PA@1
2
C6810.1U_0402_16V4Z
RP@
12
JP13
FOX_AS0B226-S99N-7FCONN@
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
3939
4040
4141
4242
4343
4444
4545
4646
4747
4848
4949
5050
5151
5252
11
22
G1
53
G2
54
G3
55
G3
56
R1037
10K_0402_5%@
1 2
C678
4.7U_0805_10V4Z
RP@1
2
R4070_0805_5%
12
C668
0.01U_0402_16V7K
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
XD_CD#
APREXT
PCIE_PTX_IRX_P1PCIE_PTX_IRX_N1
XDCD0#_SDCD#XDCD1#_MSCD#
XD_RB#XD_ALE
XD_SD_D6XD_SD_D7XD_RE#
XD_SD_D4XD_SD_D5
XD_CLEXDWP#_SDWP#
SDCMD_MSBS_XDWE#XD_SD_MS_D3
XD_SD_MS_D0XD_SD_MS_D1XD_SD_MS_D2
XDCD0#_SDCD#
XDCD1#_MSCD#
XD_RB#
XDWP#_SDWP#
XD_RE#
XD_CLE
CPPE#
SDCMD_MSBS_XDWE#
SDCMD_MSBS_XDWE#
MSCLK
XDCD1#_MSCD#
XD_SD_MS_D0SDCLK
XD_SD_MS_D3XD_SD_MS_D2XD_SD_MS_D1
XD_SD_MS_D0
XD_SD_MS_D3XD_SD_MS_D2XD_SD_MS_D1
XD_ALE
XD_CLE
XDWP#_SDWP#
XDCE#
XD_RB#
SDCMD_MSBS_XDWE#
XD_CD#
XD_RE#XDWP#_SDWP#
XD_SD_D6XD_SD_D7
XD_SD_D4XD_SD_D5
XD_SD_MS_D2XD_SD_MS_D1XD_SD_MS_D0
XD_SD_MS_D3
XDCD0#_SDCD#
XD_SD_D6
XD_SD_D4XD_SD_D5
XD_SD_D7
SDCLK
XDCE#
SDCLKMSCLK
SDCLK_MSCLK_XDCE#
MSCLK XDCE#
CPPE#
XDCD0#_SDCD#
XD_ALE
CR_LED#
PCIE_ITX_C_PRX_P1<10>PCIE_ITX_C_PRX_N1<10>
PCIE_PTX_C_IRX_P1<10>PCIE_PTX_C_IRX_N1<10>
PLT_RST#<11,14,19,25,26,32,33>
CLK_PCIE_MCARD0#<15>CLK_PCIE_MCARD0<15>
CR_CPPE#<20>
CR_WAKE#<21>
+VCC_4IN1+VCC_OUT
+1.8VS_OUT
+3VS_CR
+1.8VS_OUT
+VCC_OUT
+3VS_CR
+VCC_4IN1
+3VS_CR
+1.8VS
+3VS+3VS_CR
+5VS_LED
+3VS
+VCC_OUT +VCC_4IN1
+VCC_4IN1 +VCC_4IN1
+3VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
PCI-E I/F Card Reader-JM385
Custom
27 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Card Reader Connector
Use 0805 type and over 20 mils trace width on both side
8mA sink current
White LED: VF=3V, IF = 10mA, Res = 200 ohm
use for PWR_EN#
Power Circuit
Strap pin for JMicro
25mA
45mA
58mA
1mA
D3 Normal 30mA Deepest 3mA
Ripple 100mV
Ripple 100mV
Ripple 250mV
Ripple 250mV
place near pin 5 and
pin 10.
20mil
12mil
40mil
L Place R413,C902 close to JREAD.20; R412,C901close to JREAD.26; R411,C900 close to JREAD.37
L At least 20mils
L Place R455~R457 close to U23.42
R411100_0402_5%
@
12
R369
0_0402_5%
1 2
U22
G5250C2T1U_SOT23-5@
IN3
EN4
OUT1
OUT5
GND2
R413100_0402_5%
@
12
C6950.1U_0402_16V4Z12
JMB385
U23
JMB385-LGEZ0A_LQFP48_7X7
XRSTN1
XTEST2
APCLKN3
APCLKP4
APVDD5
APGND6
APREXT7
APRXP8
APRXN9
APV1810
APTXN11
APTXP12
SEEDAT13
SEECLK14
CR1_CD1N15
CR1_CD0N16
CR1_PCTLN17
DV1818
DV3319
DV3320
CR1_LEDN21
MDIO1422
MDIO1323
GND24
MDIO1225
MDIO1126
MDIO1027
MDIO928
MDIO829
TAV3330
GND31
GND32
GND33
NC34
NC35
NC36
DV1837
PCIES_EN38
PCIES39
MDIO740
MDIO641
MDIO542
MDIO443
DV3344
MDIO345
MDIO246
MDIO147
MDIO048
R45 10K_0402_5%
12
R106910K_0402_5%
12
R123
150K_0402_5%
@
12
R455 22_0402_5%12
R124
10K_0402_5%
12
C6900.1U_0402_16V4Z
1
2
C896
1U_0603_10V4Z
@
1
2
T45PAD
D40
DAN202U_SC70
2
31
7 IN 1 CONN
JREAD
TAITW_R015-B10-LMCONN@
XD-WP33
XD-D47
MS-DATA324
MS-DATA017
SD-DAT230
SD-DAT014
SD-CMD25
MS-DATA115
XD-D65
SD-DAT329
SD-DAT112
XD-ALE35
XD-D032
SD_CLK20
XD-D29
MS-INS22
MS-DATA219
MS-SCLK26
XD-RE38
MS-BS13
XD-D56
XD-D74
XD-D110
XD-CE37
XD-R/B39
XD-D38
XD-WE34
MS-VCC28
7IN1 GND11
XD-CLE36
7IN1 GND31
SD-VCC21
XD-VCC3
XD-CD40
SD-CD-SW1
SD-WP-SW2
7IN1 GND41
7IN1 GND42
SD-DAT427
SD-DAT523
SD-DAT618
SD-DAT716
R1070
0_0402_5%
1 2
R412100_0402_5%
@
12
R10210_0603_5%
12
R121 4.7K_0402_5%
12
R370
470_0402_5%
12
C696270P_0402_50V7K
1
2
R86200K_0402_5%
12
C6940.1U_0402_16V4Z
1
2
C892
10U_0805_10V4Z
@1
2
C692
0.1U_0402_16V4Z
1
2
G
D
S
Q53
2N7002_SOT23-3
@
2
13
R106 10K_0402_5%
12
D5
HT-F196BP5_WHITE
21
C6860.1U_0402_16V4Z
1
2
R454
4.7K_0402_5%
@
12
C693 0.1U_0402_16V7K1 2
R457 22_0402_5%12
C895
0.1U_0402_16V4Z@
1
2
R40510K_0402_5%
12
R12210K_0402_5% @12
C893
0.1U_0402_16V4Z
1
2
R3830_0805_5%1 2
C688
0.1U_0402_16V4Z
1
2
R111 4.7K_0402_5%
12
C68910U_0805_10V4Z
1
2
C687
1U_0402_6.3V4Z
1
2
C900100P_0402_25V8K
@
1
2
R1020
0_0603_5%@
12
C902100P_0402_25V8K
@
1
2
C691
0.1U_0402_16V4Z
1
2
C697 0.1U_0402_16V7K1 2
R456 22_0402_5%12
R1148.2K_0402_5%
12
C901100P_0402_25V8K
@
1
2
G
D S
Q54
2N7002_SOT23-3
2
1 3
R40910K_0402_5%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
HDA_BITCLK_CODEC
EAPD_CODEC
MIC_EXTR
MIC_EXTL
MIC_INR
MIC_INL
LINE_OUT_L
LINE_OUT_R
VREFOUT_B
SENSE
HP_OUTL
HP_OUTR
DOCK_MICR
DOCK_MICL
HDA_SYNC_CODEC
HDA_RST#_CODEC
MONO_INR
SENSEB#
VC_REFA
HDA_BITCLK_CODEC
HDA_SDOUT_CODEC
SPDIF_OUT
SUSP#<26,33,36,38,41>
GNDA <29>
EAPD_CODEC <33>
DMIC_DAT <17>
HP_OUTR <29>
INTMIC_DET# <29>
LINE_OUT_L <29>
LINE_OUT_R <29>
VREFOUT_B <29>
EXTMIC_DET# <29>
HP_OUTL <29>
MIC_EXT_L <29>
MIC_EXT_R <29>
MIC_IN_L <29>
MIC_IN_R <29>
DOCK_MIC_L <35>
DOCK_MIC_R <35>
HDA_BITCLK_CODEC<20>
HDA_SDOUT_CODEC<20>
HDA_SDIN0<20>
HDA_SYNC_CODEC<20>
HDA_RST#_CODEC<20>
SB_SPKR<20>
SENSE_B#<35>
DMIC_CLK<17>JACK_DET# <29,35>
EC_BEEP<33>
SPDIF_OUT <35>
+5VALW +VDDA_CODEC
+3VS_HDA
+3VS
+3VDD_CODEC +VDDA_CODEC
+3VDD_CODEC
+VDDA_CODEC_R
+3VS_HDA
+VDDA_CODEC_R
+VDDA_CODEC_R
+VDDA_CODEC_R+3VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
Audio Codec-IDT9271B7
Custom
28 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
CODEC POWER
W=40Mil
300mA(4.75V(4.56~4.94V))
Use an 80mil toconnection or placea 1206 resistor underCODEC with doublevias.
GNDAGND
DOCK MIC
HP Jack & Dock
Internal SPKR.
Internal MIC
Jack MIC
F
H
39.2K
5.11K
SENSE A
10K
Port
D
G
A
20K
C
Resistor
B
10K
5.11K
39.2K E
PortResistor
20K
SENSE B
T21PADC745
33P_0402_50V8K@
1
2
C749
0.1U_0402_16V4Z
@
1 2
R198
0_1206_5%1 2
U32
G9191-475T1U_SOT23-5
IN1
GND2
SHDN3
OUT5
BYP4
R523 10K_0402_5%1 2
C984 0.022U_0603_25V7KPRM@
1 2
C986 1U_0603_10V6KRP@1 2
R23022_0402_5%RP@
1 2
C913 1U_0603_10V4Z12
C985 1U_0603_10V6KRP@1 2
R1006
0_0402_5%
@
1 2
C982 1U_0603_10V6K 1 2
R195
0_0805_5%
@
1 2
C979
0.1U_0402_16V4Z
RP@1
2
R422 0_0603_5%PR@1 2
C983 0.022U_0603_25V7KPRM@
1 2
R522 33_0402_5% 1 2
R978
BLM18BD601SN1D_06031 2
C956 0.1U_0402_16V4Z1 2
C733
0.1U_0402_16V4Z
1
2
R563 47K_0402_5%@1 2
C1046
0.1U_0402_16V4Z
1
2
R570 10K_0402_1%1 2
C728 0.1U_0402_16V4Z1 2
R910 39.2K_0402_1%RP@ 1 2
R52547_0402_5%@
12
C74410U_0805_10V4Z
1 2
C9550.1U_0402_16V4Z
1 2
R524 47K_0402_5%1 2
C729
2.2U_0805_16V4Z
1
2
C981 1U_0603_10V6K 1 2
C730
0.1U_0402_16V4Z
1
2
R885
BLM18BD601SN1D_06031 2
C734
1U_0603_10V4Z
1
2
C746
0.1U_0402_16V4Z
@
1 2
C731
1U_0603_10V4Z
1
2
R569 20K_0402_1%1 2
U27
92HD71B7X5NLGXA1X8_QFN48_7X7
DVDD_CORE1
BITCLK6
VOL_DN/DMIC_1/GPIO 24
SDO5
VOL_UP/DMIC_0/GPIO 12
DVDD_IO3
SDI_CODEC8
DVSS**7
PCBEEP12
RESET#11
SYNC10
DVDD_CORE*9
SENSE_A13
PORTE_L14
PORTE_R15
PORTF_L16
PORTF_R17
NC18
NC19
NC20
PORTB_L21
PORTB_R22
PORTC_L23
PORTC_R24
PORTD_R36
PORTD_L35
SENSE_B / NC34
CAP233
MONO_OUT32
VREFOUT-E / GPIO 431
GPIO 330
VREFOUT-C29
VREFOUT-B28
VREFFILT27
AVSS1*26
AVDD1*25
SPDIF OUT048
EAPD/ SPDIF OUT 0 or 1 / GPIO 047
DMIC_CLK46
SPDIF OUT1 / GPIO 745
GPIO 644
GPIO 543
AVSS2**42
PORTA_R41
NC / OTP40
PORTA_L39
AVDD2**38
NC37
R979
0_0603_5%
1 2
R548 5.1K_0402_1%1 2
R9110_0603_5%
RM@
12
C748
0.1U_0402_16V4Z
@
1 2
C732
0.1U_0402_16V4Z
1
2
R571 39.2K_0402_1%
1 2
R982 5.1K_0402_1%1 2
C747
0.1U_0402_16V4Z
@
1 2
C951 0.1U_0402_16V4Z1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
HP_OUT_RHP_OUT_L
EXTMIC_DET#HP_DET#
CIR_IN
MIC_EXT_RMIC_EXT_L
MIC_EXT_L
MIC_EXT_R
HP_OUT_L
HP_OUT_R
SPKL-
SPKL+
SPKR-
EC_MUTE#
SPKR+
SPKL+SPKL-SPKR+SPKR-
MIC_IN_R
MIC_IN_RMIC_IN_L
MIC_IN_L
HP_DET#
DOCK_LOUT_C_R
DOCK_LOUT_C_L
DOCK_LOUT_CR_R
DOCK_LOUT_CR_LDOCK_LOUT_L
DOCK_LOUT_R
GNDA_DOCK_1GNDA_DOCK
GNDA_DOCK_2
MIC_IN_R<28>MIC_IN_L<28>
INTMIC_DET#<28>
ANA_MIC_DET<33>
EXTMIC_DET#<28>
CIR_IN<33,35>
MIC_EXT_L<28>
MIC_EXT_R<28>
VREFOUT_B<28>
JACK_DET#<28,35>
HP_OUTR<28>
HP_OUTL<28>
LINE_OUT_L<28>
LINE_OUT_R<28>
EC_MUTE#<33>
DOCK_LOUT_C_L <35>
DOCK_LOUT_C_R <35>
GNDA_DOCK_1 <35>
GNDA_DOCK_2 <35>
+3VS
+VDDA_CODEC
+5VL
+VDDA_CODEC
B+
+3VALW
+5VS+5VAMP
+5VS
+3VALW
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
AMP & Audio Jack
Custom
29 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
SPEAKER
INTMIC IN
Audio/B & CIR
EXTMIC IN
HP OUT For M/B
Keep 10 mil width
15.6dB
GAIN0 GAIN1 Av(inv)
0 6dB
15.6dB
21.6dB
0
1
0
1
1
9/20 SP02000H700/SP02000H900
Close to CODEC U27
Close to CODEC U27
0 1 10dB
9/20 SP02000H800
HP OUT For Docking
R909
0_0402_5%
12
JP20
E&T_3806-F04N-02RCONN@
11
22
33
44
GND15
GND26
C760
100P_0402_50V8J
1
2
R97310K_0402_5%
RP@
12
R908
4.7K_0402_5%
12
R969
60.4_0603_1%
RP@
1 2
C1041 0.022U_0603_25V7K 1 2 C7431U_0603_10V4Z
PRM@
1 2
C1054 47P_0402_50V8J1 2
D61PSOT24C_SOT23-3
PRM@
231
R968
60.4_0603_1%
RP@
1 2
R1003
100K_0402_5%
12
+
C776 150U_Y_6.3VMRP@
1 2
C1051
0.1U_0402_16V4Z
1
2
+
C773 150U_Y_6.3VM
1 2
R97410K_0402_5%
RP@
12
Q145A
2N7002DW-7-F_SOT363-6
RP@
61
2
C742
1U_0603_10V4Z
1 2
R1001100K_0402_5%
12
C76610U_0805_10V4Z
1
2
C761
100P_0402_50V8J
1
2
R125
0_0402_5%
@
12
G
D
S
Q1512N7002_SOT23-3
PR@ 2
13
Q148A
2N7002DW-7-F_SOT363-6RP@
61
2
R906
1K_0402_5% PRM@12
R975330K_0402_5%
RP@
12
R1005
0_0402_5%
12
+
C774 150U_Y_6.3VM
1 2
R977 0_0603_5%RP@
1 2
G
D
S Q1612N7002_SOT23-3
RP@2
13
R4140_0402_5%
RM@
12
C1040 0.022U_0603_25V7K 1 2
R1002
0_0402_5%
12
R955 10K_0402_5%PRM@12
JP43
ACES_87213-1400GCONN@
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
C1052 47P_0402_50V8J1 2
R1004100K_0402_5%@
12
C762
100P_0402_50V8J
1
2
R907
4.7K_0402_5%
12
C1049 0.022U_0603_25V7K 1 2
C1050 0.022U_0603_25V7K 1 2
JP42
ACES_88231-04001
CONN@
11
22
33
44
GND15
GND26
Q145B
2N7002DW-7-F_SOT363-6
RP@
3
5
4
C763
100P_0402_50V8J
1
2
Q147A
2N7002DW-7-F_SOT363-6RP@
6 1
2
R905
4.7K_0402_5%PR@
12
+
C775 150U_Y_6.3VMRP@
1 2
G
D
S
Q160
2N7002_SOT23-3
PR@ 2
13
C767
0.1U_0402_16V4Z
1
2
C1055 47P_0402_50V8J1 2
R103
10K_0402_5%
PA@
12
U28
TPA6017A2_TSSOP20
GN
D4
1G
ND
31
1G
ND
21
3G
ND
12
0
VD
D1
6
PV
DD
11
5
RIN-17
BYPASS10
NC12
LOUT-8
LOUT+4
ROUT-14
ROUT+18
RIN+7
LIN-5
LIN+9
GAIN02
GAIN13
PV
DD
26
SHUTDOWN19
TH
ER
MA
L P
AD
21
Q148B
2N7002DW-7-F_SOT363-6RP@3
5
4
R1000100K_0402_5%@
12
R951
100K_0402_5%PR@
12
R9044.7K_0402_5%
PRM@
12
R126
0_0402_5%12
Q147B
2N7002DW-7-F_SOT363-6RP@
3
5
4
C1053 47P_0402_50V8J1 2
R594
0_1206_5%1 2
C10441U_0805_50V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SMB_CK_CLK0
SMB_CK_DAT0
ACCEL_INT <19>
HDD_HALTLED <34>
SMB_CK_DAT0 <8,9,15,20>
SMB_CK_CLK0 <8,9,15,20>
+3VS_ACL_IO
+3VS_ACL
+3VS_ACL+3VS +3VS_ACL_IO
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
Accelerometer
Custom
30 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
ACCELEROMETER
0011101b
L Must be placed in the center of the system.
VDDIO absolute manrating is VDD+0.1
D44
CH751H-40PT_SOD323-2
RP@
2 1
R999 10K_0402_5%
RP@
12
C1030
0.1U_0402_16V4Z
RP@1
2
C1031
10U_0805_6.3V6M
RP@1
2
U63
LIS302DLTR_LGA14_3x5
RP@
SC
L / S
PC
14
GND2
Reserved3
GND4
GND5
CS
7
Vdd_IO1
Vdd6
SDA / SDI / SDO13
SDO12
Reserved11
GND10
INT 29
INT 18
R9980_0402_5%
RP@
1 2
R9970_0402_5%
RP@
1 2
R959 0_0603_5%RP@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
USB20_P6
USB20_N6
USB_EN#
SATA_RXP2SATA_RXN2
SATA_TXP2SATA_TXN2
USB_EN#
USB_EN#
USB20_N7USB20_P7
USB20_N2_R
USB20_P2_R
SATA_TXP2
SATA_TXN2
USB20_N2_RUSB20_P2_R
BT_LED
USB20_P6USB20_N6
USB20_N7
+3VS_FB
+3VS_FB
USB20_P7
BT_LED
USB20_P6USB20_N6
SATA_TXP2<21>SATA_TXN2<21>
SATA_RXN2_C<21>SATA_RXP2_C<21>
USB_EN#<33>
USB20_N0<20>USB20_P0<20>
USB20_N1<20>USB20_P1<20>
USB20_P7<20>USB20_N7<20>
BT_OFF<21>
USB20_P2<20>
USB20_N2<20>
BT_LED <34>
CH_DATA <26>CH_CLK <26>
USB20_N6 <20>USB20_P6 <20>
+3VAUX_BT+3VS
+3VAUX_BT
+USB_VCCA+5VALW+USB_VCCA
+5VALW
+3VS+3VALW
+USB_VCCA
+USB_VCCA
+3VAUX_BT
+5VALW
+3VAUX_BT
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
USB, BT, eSATA,FPR
Custom
31 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
BT Connector
Check BT power consumption < 1A
W=100mils
Left side USB CONNECTOR Right side USB 0&1 Board Conn
9/20 SP02000DX00
9/20 SP02000HC00/SP02000HB00
9/20 SP01000B000
Finger printer
Max 0.5AMax 2.5A
USB
ESATA
JESAT
TYCO_1759576-1CONN@
VBUS1
D-2
D+3
GND4
GND5
A+6
A-7
GND8
B-9
B+10
GND11
GND12
GND13
GND14
GND15
L51
WCM-2012-900T_4P
11
44
33
22
JP47
ACES_87213-1000G
CONN@
11
22
33
44
55
66
77
88
99
1010
GND111
GND212
U40
TPS2061IDGN_MSOP8~N
GND1
IN2
OC#5
OUT6
OUT8
IN3
EN#4
OUT7
+
C7
89
15
0U
_D
_6
.3V
M
1
2
C7
91
10
00
P_
04
02
_5
0V
7K
1
2
C7
90
0.1
U_
04
02
_1
6V
4Z
1
2
C801
4.7U_0805_10V4Z
1
2
C8320.1U_0402_16V4Z
1
2
C792 1000P_0402_50V7K
1 2
C1
12
10
.1U
_0
40
2_
16
V4
Z
1
2
C788
4.7U_0805_10V4Z
1
2
C799
0.01U_0402_16V7K
1
2
C800
0.1U_0402_16V4Z
1
2
R520
10K_0402_5%
1 2
D12
PRTR5V0U2X_SOT143-4@
GND1
IO12
IO23
VIN4
R519
100K_0402_5%
12
C1109820P_0402_25V7K
1
2
C802 0.1U_0402_16V4Z1 2
R517 1K_0402_5%@ 1 2
D11
PRTR5V0U2X_SOT143-4@
GND1
IO12
IO23
VIN4
G
DS
Q24 SI2301BDS-T1-E3_SOT23-3
2
13
JP55
JST_SM06B-XSRK-ETB(HF)
CONN@
11
22
33
44
55
66
GND7
GND8
C798
1U_0603_10V4Z
1
2
JP39
ACES_85201-06051CONN@
GND7
GND8
11
22
33
44
55
66
R581
0_0603_5%1 2
JP32
ACES 87213-0800G
CONN@
11
22
33
44
55
66
77
88
GND19
GND210
C793 1000P_0402_50V7K
1 2
D16
PRTR5V0U2X_SOT143-4@
GND1
IO12
IO23
VIN4
D21
PRTR5V0U2X_SOT143-4
@
GND1
IO12
IO23
VIN4
G
DS
Q31 SI2301BDS-T1-E3_SOT23-3@
2
13
R518 1K_0402_5%@ 1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
SPI_CS# INT_SPI_CS#
SPI_CLK_R
EC_SO_SPI_SI_R EC_SI_SPI_SO_R
LPC_AD2
CLK_PCI_SIO
PLT_RST#
LPC_DRQ#
LPC_AD1
LPC_FRAME#
SIRQ
LPC_AD0
LPC_AD3
EC_SI_SPI_SO <33>
SMB_EC_CK1<6,33,34,37>SMB_EC_DA1<6,33,34,37>
SPI_CLK<33>
EC_SO_SPI_SI<33>
SPI_CS#<33>
LPC_FRAME#<19,33>
LPC_AD0 <19,33>
PLT_RST# <11,14,19,25,26,27,33>
LPC_AD2 <19,33>
SIRQ<19,33>
LPC_AD3<19,33>
LPC_AD1<19,33>
CLK_PCI_SIO <19>
LPC_DRQ# <19>
+3VL
+3VALW
+3VAL
+3VALW
+3VL
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
BIOS ROM/Debug Tool
Custom
32 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
SPI Flash (16Mb*1)20mils
LPC Debug Port
9/20 ??????
L Need add back R221 if no ext BIOS design U30 install.
Ripely 2.0 will support 16Mb SPI ROM
SA00001IT00
H31
DEBUG_PAD@
1
2
3
4
56
7
8
9
10
R23222_0402_5%
@
12
U29
WIESON G6179 8P SPI
CONN@
S1
VCC8
Q2
HOLD7
VSS4
D5
C6
W3
C48622P_0402_50V8J@
1
2
R996 0_0402_5%1 2
R227 0_0402_5%
1 2
R221 0_0402_5%1 2
U31
AT24C16AN-10SI-2.7_SO8@
A01
A12
SDA5
SCL6
VCC8
A23
GND4
WP7
R995 0_0402_5%@1 2
C803
0.1U_0402_16V4Z
1
2
R521100K_0402_5%
12
C484
0.1U_0402_16V4Z
1
2
R223 0_0402_5%
12
R526100K_0402_5%
12
&U29
SA00001IT00
45@
R229 0_0402_5%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
LID_SW#
ON/OFF#
KSO8
KSO12
KSI7
KSO13
KSO4
KSO14
FSTCHG
KSO5
KSO0KSO1
KSO6
KSO9
KSO7
KSO2KSO3
BATT_OVP
KSO11KSO10
SYSONSMB_EC_CK2SMB_EC_DA2
SB_PWRGD
ECRST#
ACOFF
SLP_S3#
TP_CLK
TP_DATA
ON/OFFBTN_LED#
SLP_S5#
E51_RXD
PWRBTN_OUT#
TP_BTN#
E51_TXD
KSI6
KSI1
KSI5
KSI2
KSO15
KSI4
BKOFF#
EC_RSMRST#
SMB_EC_CK1SMB_EC_DA1
SUSP#
TP_LED#
NMI_DBG#
BAT_LED#
EC_SMI#
LPC_LFRAME#
LID_SW#
IREF
KSO17
SIRQ
GATEA20
LPC_AD2
KSO16
LPC_AD1
LPC_AD3
KB_RST#
LPC_AD0
EC
AG
ND
ECAGND
EC_PWM
TP_CLK
PLT_RST#
TP_DATA
CLK_PCI_EC
FAN_PWM
EC_SCI#
BATT_TEMP
CR Y2
KSI3
KSI0
CR Y1
EC_BEEP
KSI5
KSO11
KSO0
KSO1KSI0
KSI7
KSO13
KSO2
KSI2
KSO4
KSO8
KSO15KSO10
KSO3
KSO5
KSI4
KSO7
KSO14
KSI3
KSO6
KSO12
KSI6
KSI1
KSO9
KSI5
KSO11
KSO0
KSO1KSI0
KSI7
KSO13
KSO2
KSI2
KSO4
KSO8
KSO15KSO10
KSO3
KSO5
KSI4
KSO7
KSO14
KSI3
KSO6
KSO12
KSI6
KSI1
KSO9
VR_ONAC_IN_EC
SUSP# SYSON
SMB_EC_CK2
SMB_EC_DA2
SMB_EC_DA1
SMB_EC_CK1
DOCK_VOL_UP#
DOCK_VOL_DWN#
TP_BTN#
H_THERMTRIP#_EC
CIR_IN
LAN_POWER_OFF E51_RXD
WL_BLUE_BTN
WL_BLUE_BTN
E51_TXD
ESB_DAT
EC_CLKEC_DAT
EC_CLK
EC_DAT
EC_CLKEC_DAT
ESB_CLK
NB_OTP
PLT_RST#<11,14,19,25,26,27,32>ANA_MIC_DET <29>
CONA#<35>
LPC_AD1<19,32>
CIR_IN <29,35>
LPC_FRAME#<19,32>SIRQ<19,32>
LPC_AD2<19,32>
LPC_AD0<19,32>
LPC_AD3<19,32>
CLK_PCI_EC<19,23>
SMB_EC_CK1<6,32,34,37>
EC_SCI#<20>
SMB_EC_DA1<6,32,34,37>
EC_SO_SPI_SI <32>
SMB_EC_CK2<6>SMB_EC_DA2<6>
EC_SI_SPI_SO <32>
SPI_CS# <32>SPI_CLK <32>
BATT_OVP <37>BATT_TEMP <37>
DAC_BRIG <17>
SYSON <26,36,40>
FAN_PWM <4>
EC_RSMRST# <20>
EC_ON <36,39>
BAT_LED# <34>
LID_SW#<34>
ADP_I <38>
VR_ON <43>
GATEA20<20>KB_RST#<20>
EC_THERM# <21>
ON/OFFBTN_LED# <34>
EC_LID_OUT# <20>
SLP_S3#<20>SLP_S5#<20>EC_SMI#<20>
TP_CLK <34>TP_DATA <34>
ON/OFF#<34>
SB_PWRGD <6,20,43>BKOFF# <17>
EAPD_CODEC <28>DIM_LED<36>
TP_BTN# <34>
MUTE_LED <35>
ACOFF <38>
I2C_INT <34>
DOCK_VOL_DWN# <35>DOCK_VOL_UP# <35>
USB_EN# <31>EC_MUTE# <29>
STD_ADP <38>
ENBKL <11>
AC_SET <38>
VLDT_EN<36>
TP_LED# <34>
FSTCHG <38>
ADP_ID <37>
PCI_SERR# <19>
HDARST#<20,23>
IREF <38>
CAPS_LED# <34>
EC_BEEP <28>
WL_BLUE_LED# <34>
AC_IN <21,38>
NUM_LED#<34>DOCK_SLP_BTN#<35>
PWRBTN_OUT# <20>
VCTRL <38>
VGATE <43>
SUSP# <26,28,36,38,41>
H_THERMTRIP#_EC<6>
LAN_POWER_OFF<25>
WL_BLUE_BTN<34>
VFIX_EN <43>
AC_LED# <37>ESB_DAT<34>ESB_CLK<34>
EC_PWM <17>
WWAN_POWER_OFF <26>
NB_OTP <37>
+EC_AVCC
+3VL_EC
+3VL_EC
+EC_AVCC
+3VL_EC
+5V_TP
+3VL_EC+3VL
+3VL_EC
+3VL_EC
+3VS
+3VL+3VS
+3VS
+5VS_LED
+5VL
+3VL +3VL_EC
+3VL
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
EC KB926/KB conn
Custom
33 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
KB Back Light Conn
For EMI
EC DEBUG port
Need 4.7uf for 926 C version
9/20 SP01000KC00/SP010009O10
9/20 SP01000FF00/SP01000G300
Keyboard Connector
L TP_LED#=L, T/P disableTP_LED#=float (GPO), T/P enable
02/15 Remove JP34 and reserve R1068 for EC debug.
02/22 Add R1076, C1104 and R1077 for EMI request.
L Please close to EC.
1/19 Change EC P/N to D3 version
R5314.7K_0402_5%
12
C807
1000P_0402_50V7K
1
2
R547
0_0402_5%
1 2
C822 100P_0402_25V8K@ 1 2
C758 100P_0402_25V8K@ 1 2
C884 100P_0402_25V8K@ 1 2
C609 100P_0402_25V8K@ 1 2
C756 100P_0402_25V8K@ 1 2
C876 100P_0402_25V8K@ 1 2
C875 100P_0402_25V8K@ 1 2
C885 100P_0402_25V8K@ 1 2
C826 100P_0402_25V8K@ 1 2
JP48
ACES_85201-04051
CONN@
11
22
33
44
G15
G26
R527
0_0805_5%1 2
C887 100P_0402_25V8K@ 1 2
C886 100P_0402_25V8K@ 1 2
R51310K_0402_5%
1 2
C878 100P_0402_25V8K@ 1 2
C888 100P_0402_25V8K@ 1 2
C8110.1U_0402_16V4Z
12
C809
1000P_0402_50V7K
1
2
LPC & MISC
Int. K/B Matrix
SM Bus
GPIO
GPIO
AD Input
PWM Output
DA Output
PS2 Interface
SPI Device Interface
SPI Flash ROM
GPO
GPI
U33
KB926QFC0_LQFP128_14X14
GA20/GPIO001
KBRST#/GPIO012
SERIRQ#3
LFRAME#4
LAD35
PM_SLP_S3#/GPIO046
LAD27
LAD18
VC
C9
LAD010
GN
D1
1
PCICLK12
PCIRST#/GPIO0513
PM_SLP_S5#/GPIO0714
EC_SMI#/GPIO0815
LID_SW#/GPIO0A16
SUSP#/GPIO0B17
PBTN_OUT#/GPIO0C18
EC_PME#/GPIO0D19
SCI#/GPIO0E20
INVT_PWM/PWM1/GPIO0F21
VC
C2
2
BEEP#/PWM2/GPIO1023
GN
D2
4EC_THERM#/GPIO11
25
FANPWM1/GPIO1226
ACOFF/FANPWM2/GPIO1327
FAN_SPEED1/FANFB1/GPIO1428
FANFB2/GPIO1529
EC_TX/GPIO1630
EC_RX/GPIO1731
ON_OFF/GPIO1832
VC
C3
3
PWR_LED#/GPIO1934
GN
D3
5
NUMLED#/GPIO1A36
ECRST#37
CLKRUN#/GPIO1D38
KSO0/GPIO2039
KSO1/GPIO2140
KSO2/GPIO2241
KSO3/GPIO2342
KSO4/GPIO2443
KSO5/GPIO2544
KSO6/GPIO2645
KSO7/GPIO2746
KSO8/GPIO2847
KSO9/GPIO2948
KSO10/GPIO2A49
KSO11/GPIO2B50
KSO12/GPIO2C51
KSO13/GPIO2D52
KSO14/GPIO2E53
KSO15/GPIO2F54
KSI0/GPIO3055
KSI1/GPIO3156
KSI2/GPIO3257
KSI3/GPIO3358
KSI4/GPIO3459
KSI5/GPIO3560
KSI6/GPIO3661
KSI7/GPIO3762
BATT_TEMP/AD0/GPIO3863
BATT_OVP/AD1/GPIO3964
ADP_I/AD2/GPIO3A65
AD3/GPIO3B66
AV
CC
67
DAC_BRIG/DA0/GPIO3C68
AG
ND
69
EN_DFAN1/DA1/GPIO3D70
IREF/DA2/GPIO3E71
DA3/GPIO3F72
CIR_RX/GPIO4073
CIR_RLC_TX/GPIO4174
AD4/GPIO4275
SELIO2#/AD5/GPIO4376
SCL1/GPIO4477
SDA1/GPIO4578
SCL2/GPIO4679
SDA2/GPIO4780
KSO16/GPIO4881
KSO17/GPIO4982
PSCLK1/GPIO4A83
PSDAT1/GPIO4B84
PSCLK2/GPIO4C85
PSDAT2/GPIO4D86
TP_CLK/PSCLK3/GPIO4E87
TP_DATA/PSDAT3/GPIO4F88
FSTCHG/SELIO#/GPIO5089
BATT_CHGI_LED#/GPIO5290
CAPS_LED#/GPIO5391
BATT_LOW_LED#/GPIO5492
SUSP_LED#/GPIO5593
GN
D9
4
SYSON/GPIO5695
VC
C9
6
SDICS#/GPXOA0097
SDICLK/GPXOA0198
SDIDO/GPXOA0299
EC_RSMRST#/GPXO03100
EC_LID_OUT#/GPXO04101
EC_ON/GPXO05102
EC_SWI#/GPXO06103
ICH_PWROK/GPXO06104
BKOFF#/GPXO08105
WL_OFF#/GPXO09106
GPXO10107
GPXO11108
SDIDI/GPXID0109
PM_SLP_S4#/GPXID1110
VC
C1
11
ENBKL/GPXID2112
GN
D1
13
GPXID3114
GPXID4115
GPXID5116
GPXID6117
GPXID7118
SPIDI/RD#119
SPIDO/WR#120
VR_ON/XCLK32K/GPIO57121
XCLK1122
XCLK0123
V18R124
VC
C1
25
SPICLK/GPIO58126
AC_IN/GPIO59127
SPICS#128
R46 10K_0402_5%
1 2
C823 100P_0402_25V8K@ 1 2
C757 100P_0402_25V8K@ 1 2
D54CH751H-40PT_SOD323-2
2 1
R536100K_0402_5%
12
R5284.7K_0402_5%
12
C824 100P_0402_25V8K@ 1 2
L800_0603_5%
12
R1077 0_0402_5% 1 2
R1050
10K_0402_5%1 2
R58910K_0402_5%
12
R542 0_0402_5%
RP@
1 2
C814 4.7U_0805_10V4Z
12
R539100K_0402_5%
12
C769 100P_0402_25V8K@ 1 2
C816 0.1U_0402_16V4Z
1 2
R53347K_0402_5%
1 2
C759 100P_0402_25V8K@ 1 2
C768 100P_0402_25V8K@ 1 2
C808
0.1U_0402_16V4Z
1
2
C806
0.1U_0402_16V4Z
1
2
C1073100P_0402_50V8J
1 2
+ C110522U_A_4VM
@
1
2
R541 10K_0402_5%
12
C213 100P_0402_25V8K@ 1 2
R1076 0_0402_5%
1 2
C81315P_0402_50V8J
1 2
R53510K_0402_5%
1 2
R530
33_0402_5%@1 2
C764 100P_0402_25V8K@ 1 2
R5324.7K_0402_5%
12
R1068
0_0603_5%
@
1 2
C805
0.1U_0402_16V4Z
1
2
R1044 100K_0402_5%1 2
Y7
32.768KHZ_12.5PF_Q13MC30610003
OUT4
IN1
NC3
NC2
C81515P_0402_50V8J
1 2
R544
0_0402_5%
1 2
R53810K_0402_5%
12
L81
0_0603_5%
1 2
R5294.7K_0402_5%
12
C754 100P_0402_25V8K@ 1 2
C8120.01U_0402_16V7K
1 2
C110433P_0402_50V8K
@
1
2
R516
150_0603_1%
12
R1040150K_0402_5%
12
R54520M_0402_5%
@
12
R514 4.7K_0402_5%
1 2
JP33
ACES_85201-24051
CONN@
11
22
33
44
55
66
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
GND125
GND226
R1063 10K_0402_5%
12
R5434.7K_0402_5%
12
C877 100P_0402_25V8K@ 1 2
C810
15P_0402_50V8J@
1 2
C825 100P_0402_25V8K@ 1 2
R53410K_0402_5%
1 2
R59010K_0402_5%
12
R515 4.7K_0402_5%12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
TP_DATATP_CLK
TP_DATATP_CLK
ON/OFFBTN_LED#
HDA_SDIN1_MDC
ON/OFFBTN_LED#ON/OFF#
TP_BTN#
TP_LED#
WL/WW_LED#
WL_BLUE_LED#
WL_BLUE_LED#
ESB_CLK1EC_CK1
ESB_DAT1
+3VL_R
EC_DA1
ON/OFFBTN_LED#ON/OFF#
EC_CK1EC_DA1
I2C_INT
ESB_CLK1
ESB_DAT1
I2C_INT
TP_CLK <33>TP_DATA <33>
LID_SW#<33>
ON/OFF#<33>
ON/OFFBTN_LED#<33>
HDD_HALTLED <30>
CAPS_LED#<33>
HDA_BITCLK_MDC <20>
HDA_SYNC_MDC<20>HDA_SDIN1<20>
HDA_SDOUT_MDC<20>
HDA_RST#_MDC<20>
SYSON#<35,36,42>
TP_BTN# <33>
TP_LED# <33>
BAT_LED#<33>
WL_LED# <26>
WW_LED# <26>
BT_LED <31>
WL_BLUE_LED#<33>
SATA_LED#<21>
HDD_HALTLED# <21>
SMB_EC_CK1<6,32,33,37>
NUM_LED#<33>
ESB_CLK<33>
I2C_INT<33>ESB_DAT<33>
WL_BLUE_BTN<33>
SMB_EC_DA1<6,32,33,37>
+5V_TP
+3VL
+5VS_LED
+5VALW_LED
+5VS_LED
+3VS
+3VS
+3VS
+5VALW_LED
+5VALW +5V_TP
+3VALW
+5VS_LED
+5VS
+5VALW_LED
+3VS
+3VS
+5VS
+3VS
+3VL_CAP
+5VS_LED
+5VALW_LED
+3VL
+3VL_CAP+3VL
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
TP,MDC,ON/OFF,S/W,LED,Reed
Custom
34 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
9/20
SP01000KC00/SP01E000900
M/B TO TP/B
Reed switch BOARD.
9/20 SP01000J100
HDD/G-Sensor LED
CAPS LOCK LED
WHITEPOWER LED
WHITE
MDC 1.5 Conn.
ON/OFF Button Connector
9/20 STANDOFF (H= 5.0 mm) ES000000800
Battery Charge LED
White LED: VF=3V, IF = 10mA, Res = 200 ohmAmber LED: VF=1.8V, IF = 8mA, Res = 390 ohm
TP ON/OFF
TouchPAD ON/OFF LED
T/P Enable (TP_LED#=L)-> WhiteT/P Disable (TP_LED#=X)-> Amber
WLAN and BT LED inform pin to KBCWHITE
Max 0.5A
Max 0.5A
9/20 SP01000H400
SWITCH BOARD.
ENE::::ESBCY S:::: MB_EC
02/22 Reserve for EMI request.
L Please close to JP36
11/11 Del reserved LDO for ENE cap board
C777
10P_0402_50V8J@
1
2
Q7A
2N7002DW-7-F_SOT363-6
61
2
R20
10K_0402_5%
12
C1103
33P_0402_50V8K
@
12
R554
0_0603_5%RP@
12
C11000.1U_0402_16V4Z
1
2
R989
47K_0402_5%
1 2
R1025
100K_0402_5%
12
G
D
S
Q552N7002_SOT23-3 2
13
R555
0_0603_5%RM@
12
G
DS
Q85SI2301BDS-T1-E3_SOT23-3@
2
13
R1041
10K_0402_5%@12
SW1SMT1-05-A_4P
3
2
1
4
5 6
R985
10K_0402_5%
@
12
R984200_0402_5%
12
JP36
ACES_85201-1005NCONN@
11
22
33
44
55
66
77
88
99
1010
GND11
GND12
JP1
ACES_85201-04051CONN@
11
22
33
44
G15
G26
R49610_0402_5%@
12
R1048 47_0402_5%RP@1 2
D31PSOT24C_SOT23-3
231
JP40
ACES_85201-04051
CONN@
11
22
33
44
G15
G26
R1046 0_0402_5%RP@1 2
WHITE
YELLOW
D19
HT-297UY5/BP5_YELLOW-WHITE
PRM@
21
43
D57CH751H-40PT_SOD323-2
2 1
C821100P_0402_50V8J@
1
2
R1065 0_0402_5%RM@1 2
R988
200_0402_5%RP@
12
D6
HT-F196BP5_WHITE
21
D8
HT-F196BP5_WHITE
21
R552
470_0402_5%
1 2
WHITE
YELLOW
D18
HT-297UY5/BP5_YELLOW-WHITE
21
43
G
D
S
Q156
2N7002_SOT23-3@
2
13
C820100P_0402_50V8J
@
1
2
R558 10K_0402_5%RM@12
PJP605PAD-OPEN 2x2m
@
21
R1008 0_0402_5%PA@1 2
R550200_0402_5%1 2
R1074
0_0402_5%
RP@
12
R987
200_0402_5%
12
R1047 0_0402_5%RP@
1 2
JP37
ACES_85201-04051
CONN@
11
22
33
44
G15
G26
R103810K_0402_5%@
12
C8190.1U_0402_16V4Z
1
2
C1
09
84
.7U
_0
60
3_
6.3
V6
K
1
2
WHITE
YELLOW
D17
HT-297UY5/BP5_YELLOW-WHITE
PA@
21
43
C1
11
90
.1U
_0
40
2_
16
V4
ZR
P@
1
2
R549200_0402_5%1 2
C110110P_0402_50V8J
1
2
R983200_0402_5%
12
C2
54
0.0
47
U_
04
02
_1
6V
7K
RP
@
R1049 47_0402_5%RP@1 2
C7804.7U_0805_10V4Z@
1
2
JP25
ACES_88020-12101CONN@
11
33
55
77
99
1111
22
44
66
88
1010
1212
GN
D1
3
GN
D1
4
GN
D1
5
GN
D1
6
GN
D1
7
GN
D1
8
C2
55
0.0
47
U_
04
02
_1
6V
7K
RP
@
Q7B
2N7002DW-7-F_SOT363-6
3
5
4
R1007 0_0402_5% 1 2
C1102
33P_0402_50V8J
RP@
12
C2
57
0.1
U_
04
02
_1
6V
4Z
1
2
R49533_0402_5%1 2
R1066 0_0402_5%RM@1 2
D7
HT-F196BP5_WHITE
21
R235 0_0603_5%
1 2
R1035 0_0402_5%RM@1 2
R420_0402_5%RP@1 2
C779
0.1U_0402_16V4Z
1
2
G
D
SQ1532N7002_SOT23-3
2
13
R1034 0_0402_5%RM@1 2
R1075
47_0402_5%
@
12
C778
1000P_0402_50V7K
1
2 C2560.1U_0402_16V4Z
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
JACK_DET#DOCK_SLP_BTN#MUTELEDDOCK_PWR_ONCIR_IN
TV_LUMA_LTV_CRMA_LTV_COMPS_L
AUDIO_IGNDDOCK_PRESENT
DOCK_MIC_L_CDOCK_MIC_R_CDOCK_LOUT_C_LDOCK_LOUT_C_RAUDIO_OGND
R_VOL_DWN# DOCK_VOL_DWN#R_VOL_UP# DOCK_VOL_UP#
+V_BATTERY
DOCK_PWR_ON
DOCK_PRESENT
SPDIFO_L
DOCK_MIC_L_C
DOCK_MIC_R_CDOCK_MIC_R_R
DOCK_MIC_L_C
DOCK_MIC_L_R
R_VOL_UP# R_VOL_DWN#
DOCK_LOUT_C_LDOCK_LOUT_C_R
SPDIFO_L
RJ45_MIDI1-
RJ45_MIDI0-
D_DDCDATA
D_HSYNC
USB20_N3
RJ45_MIDI1+
RJ45_MIDI0+
D_DDCCLK
D_VSYNC
USB20_P3
AUDIO_IGND
AUDIO_IGND
AUDIO_OGND
AUDIO_IGND
GNDA_DOCKA
GNDA_DOCK_1
GNDA_DOCKA
GNDA_DOCK_2
CONA# <33>
DOCK_VOL_DWN# <33>
JACK_DET# <28,29>DOCK_SLP_BTN# <33>
DOCK_LOUT_C_R <29>DOCK_LOUT_C_L <29>
DOCK_VOL_UP# <33>
CIR_IN <29,33>
MUTE_LED <33>
SYSON#<34,36,42>
DOCK_MIC_R<28>
DOCK_MIC_L<28>
SENSE_B# <28>
SPDIF_OUT <28>
USB20_P3<20>
RJ45_MIDI1-<25>
RJ45_MIDI0-<25>
GREEN_L<16>
D_DDCDATA<16>
D_HSYNC<16>
USB20_N3<20>
RJ45_MIDI1+<25>
RJ45_MIDI0+<25>
BLUE_L<16>
RED_L<16>
D_DDCCLK<16>
D_VSYNC<16>
GNDA_DOCK_1<29>
GNDA_DOCK_2<29>
+3VL_EC
B+
+3VALW
+5VS
+3VS
+DOCKVIN
+1.5VS
+DOCKVIN
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
DOCK CONN
Custom
35 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
DOCK_PWR_ON Spec0V = Notebook S4/S5, Dock off2.5V = Notebook S3, Dock on4V = Notebook S0, Dock on
Atlas/ Saturn Dock
Need 600 Ohm 500 mAMIC_Dock
SPDIF
Close to CODEC U27
L R976/Q149/R646 be option with R992/C945
03/03 Change JDOCK Footprint
01/23 Change NMOS type to solve Saturn docking issue
H43H_4P2@
1
R591 1K_0402_5%RP@1 2
H51H_6P0X5P0N@
1
H32H_2P8@
1
R586 1K_0402_5%
RP@
1 2
D43
DAN202U_SC70
RP@
2
31
H42H_2P8@
1
R647
220_0402_5%
RP@
1 2
H54H_3P3X0P6N@
1
C943
220P_0402_50V7K
RP@1
2
G
D
S
Q182N7002_SOT23-3
RP@
2
13
R568 200_0402_5%RP@ 1 2
R914
10K_0402_5%
RP@
12
R912
10K_0402_5%
RP@
1 2
R943 10K_0402_5%RP@
12
C8431000P_0402_50V7K
RP@1
2
R91510K_0402_5%
RP@
12
L93FCM1608KF-601T02_2P
RP@
1 2
C942
220P_0402_50V7K
RP@1
2
C
B
E
Q16PMBT3904_SOT23RP@
1
2
3
JDOCK
FOX_QL1122L-H212AR-9FCONN@
CRT_Green40
TV composite33
CRT_Blue34
TV ground31
Vsync26
CIR input29
USB-28
USB+22
PWR_ON27
Digital gnd24
MDI0-6
MDI3-18
Mute_LED25
DDC_Clock30
DDC_DATA36
Digital gnd39
TV chroma35
TV Luma37
CRT_Red38
Hsync32
MDI3+20
MD2I-14
MDI2+16
MDI1-10
MDI1+12
Sleep Botton23
Jack Detect21
VOL_up19
VOL_down17
MDI0+8
Battery out2
Battery out4
SPDIF15
Audio Output gnd13
Left headphone9
Right headphone11
Mic_Right7
Dock_present1
Mic gnd3
Mic_Left5
GND41
GND42
GND43
GND44
GND45
GND46
H36H_2P8@
1
G
D
S
Q33
2N7002_SOT23-3
RP@
2
13
C8441000P_0402_50V7K
RP@1
2
H35H_2P8@
1
H57H_2P8@
1
C921220P_0402_50V7K
RP@
1
2
R415
0_0402_5%
RP@
12
R588
10K_0402_5%
RP@
12
R573
110_0402_5%RP@
12
H41H_2P8@
1
H48H_3P3@
1
R127
0_0402_5%
12H33
H_2P8@
1
R942 10K_0402_5%RP@
12
H53H_3P3X0P6N@
1
R976
33_0402_5%@
12
H55H_5P6N@
1
R585 1K_0402_5%RP@
1 2
C8311000P_0402_50V7K
RP@1
2
L94FCM1608KF-601T02_2P
RP@
1 2
R9801.21K_0402_1%RP@
12
E
B
C
Q149
MMBT3904_NL_SOT23-3@2
31
H46H_4P2@
1
R646
0_0402_5%@1 2
C922220P_0402_50V7KRP@
1
2
R9441.21K_0402_1%RP@
12
T51PAD
H56H_2P5N@
1
R913
47K_0402_5%
RP@
12
T53PAD
PJP5
PAD-OPEN 2x2m
21
H39H_2P8@
1
T52PAD
H34H_2P8@
1
H37H_2P8@
1
C978
1U_0603_10V6K
RP@1
2
R572 22_0402_5%RP@
1 2
C944
220P_0402_50V7K
RP@ 1
2
H40H_2P8@
1
G
D
S
Q100
2N7002_SOT23-3RP@
2
13
C945
0.1U_0402_16V7K
RP@
1 2R565
10K_0402_5%
RP@
12
R5662K_0402_5%
RP@
12
R417 0_0603_5%RP@
1 2
R128
0_0402_5%
@
12
R418 0_0603_5%RP@1 2
R992
0_0603_5%RP@1 2
H52H_1P5N@
1
H47H_3P3@
1
H44H_4P2@
1
G
D
SQ36
2N7002_SOT23-3
RP@
2
13
R567 200_0402_5%RP@ 1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
RUNON
VLDT_EN#
EC_ON#
SUSPSYSON#
VLDT_EN# SYSON#
VLDT_EN
VLDT_EN#
SUSP SUSP
SYSON
SYSON#
SUSP
SUSP
RUNON
SUSP
SUSP
EC_ON#
DIM_LED#
DIM_LED
DIM_LED#
SUSP
1.8VS_ENABLE
SYSON#<34,35,42> SUSP <42>
EC_ON<33,39>
SUSP# <26,28,33,38,41>SYSON<26,33,40> VLDT_EN<33>
DIM_LED<33>
VLDT_EN#<13>
+5VL
B+
+1.2VALW +1.2V_HT
+5VALW +5VS
+5VL+5VL
+5VS
+3VS
+1.8VS
+0.9V
+5VL
+1.8VS+1.8V
+1.2V_HT +1.8V +1.2VALW
B+
+3VALW +3VS
+1.5VS +1.1VS
+5VALW
+5VALW_LED
+5VS
+5VS_LED
B+
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 0.3
DC/DC Circuits
Custom
36 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
+1.2VALW TO +1.2V_HT
+5VALW TO +5VS
+1.8V TO +1.8VS
Discharge circuit
Change to +3VL(same as EC) to avoid leakage
+3VALW TO +3VS
DIM LED
G
D
S
Q402N7002_SOT23-3
2
13
CF1
1
C846
1U_0402_6.3V4Z
1
2
G
D
S
Q52
2N7002_SOT23-3
2
13
C11120.1U_0603_25V7K
1
2
FM1
1
R596
100K_0402_5%
12
C848
1U_0402_6.3V4Z
1
2
G
D
S
Q37
2N7002_SOT23-3
2
13
C839
1U_0402_6.3V4Z
1
2
R292
470_0805_5%
12
R420 0_0603_5%1 2
Q4IRF8113PBF_SO8
365
78
2
4
1
G
D
S
Q48
2N7002_SOT23-3
2
13
C840
4.7U_0805_10V4Z
1
2
R280
470_0805_5%
12
C11110.1U_0603_25V7K
1
2
R597
100K_0402_5%
12
G
D
S
Q46
2N7002_SOT23-3
2
13
FM3
1
C835
4.7U_0805_10V4Z
1
2
C11160.1U_0603_25V7K
1
2
G
D
S
Q41
2N7002_SOT23-3
2
13
C833
1U_0402_6.3V4Z
1
2
C837
0.01U_0402_25V7K
1
2
PJP8
PAD-OPEN 2x2m
21
G
D
S
Q12
2N7002_SOT23-3
2
13
R294
470_0805_5%
12
R137
750K_0402_5%
12
G
D
S Q132N7002_SOT23-3
2
13
C11140.1U_0603_25V7K
1
2
R368
470_0805_5%@12
G
DS
Q166 SI2301BDS-T1-E3_SOT23-3@
2
13
C849
0.01U_0402_25V7K
1
2
R58710K_0402_5%
@
12
C862
4.7U_0805_10V4Z
1
2
C8360.1U_0402_16V4Z
@1
2
C11130.1U_0603_25V7K
1
2
C11150.1U_0603_25V7K
1
2
Q14
SI4800BDY_SO8
S1
S2
S3
G4
D8
D7
D6
D5
C838
4.7U_0805_10V4Z
1
2
R284
470_0805_5%
12
Q11IRF8113PBF_SO8
365
78
2
4
1
C8474.7U_0805_10V4Z
1
2
R288
470_0805_5%
12
R293
470_0805_5%
12
G
D
S
Q442N7002_SOT23-3
2
13
G
D
S
Q172N7002_SOT23-3
2
13
G
D
S
Q42
2N7002_SOT23-3@
2
13
C11100.1U_0603_25V7K
1
2
G
DS
Q32 SI2301BDS-T1-E3_SOT23-3@
2
13
Q35
SI4800BDY_SO8
S1
S2
S3
G4
D8
D7
D6
D5
G
D
S
Q39
2N7002_SOT23-3
2
13
C841
10U_0805_10V4Z
1
2
R138330K_0402_5% 1 2
CF3
1
FM2
1
R598
100K_0402_5%
12
R233330K_0402_5%
12
C834
0.0
1U
_0
40
2_
25
V7
K
1
2
G
D
S
Q49
2N7002_SOT23-3
2
13
R152330K_0402_5%
12
C8644.7U_0805_10V4Z
1
2
G
D
S
Q38
2N7002_SOT23-3
21
3
R419 0_0603_5%
1 2
R234
750K_0402_5%
12
C11170.1U_0603_25V7K
1
2
CF2
1
R595
100K_0402_5%
12
C842
4.7U_0805_10V4Z
1
2
G
D
S
Q47
2N7002_SOT23-3
2
13
PJP7
PAD-OPEN 2x2m
21
R239
470_0805_5%
12
R279
470_0805_5%
12
G
D
S
Q512N7002_SOT23-3@2
13
G
D
S
Q50
2N7002_SOT23-3
2
13
C10690.1U_0402_16V4Z
@1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
EC_SMDEC_SMC
SMB_EC_DA1
SMB_EC_CK1
ADP_SIGNAL
ADPINADPIN
ENTRIP1 <39>
BATT_OVP <33>
EN0 <6,39>SMB_EC_CK1 <6,32,33,34>
SMB_EC_DA1 <6,32,33,34>
BAT_ID <38>
BATT_TEMP <33>
ADP_ID <33>
AC_LED# <33>
NB_OTP <33>
+5VS
+5VALW
BATT
+5VALW
VMB
+3VL
BATT
VIN +DOCKVIN
+3VALW
+3VL
+5VALW
+5VS
+5VALW
+5VS+3VL
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4111P 0.1
DC Connector/CPU_OTP
Custom
37 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
CPU
PH1 under CPU botten side :
CPU thermal protection at 95 +-3 degree C
PR14100_0402_5%
12
PR
24
@1
00
K_
04
02
_5
%
12
PR9
100K_0402_5%1 2
PU2
@LMV331IDCKRG4_SC70-5
P5
IN+1
IN-3
G2
O4
PR23@10K_0402_5%
12
PR7
604K_0402_1%
1 2
PC31000P_0402_50V7K
12
PC10
0.22U_0603_10V7K
12
PL1SMB3025500YA_2P
1 2
PC
41
00
P_
04
02
_5
0V
8J
12
G
D
S
PQ2SSM3K7002FU_SC70-3
2
13
PC90.01U_0402_50V4Z
12
PJP2
SUYIN_200275MR008GXOLZR
11
33
44
55
66
GND9
GND10
22
77
88
PR
13
40
K_
04
02
_1
%
12
PD3
@SM24.TC_SOT23-3
231
[email protected]_0402_1%
12
PD1
@PJSOT24C_SOT23-3
2 31
PR
61
05
K_
04
02
_1
%
12
PH1
10KB_0603_1%_TH11-3H103FT
12
PC15 0.1U_0402_16V7K
1 2
PC
60
.01
U_
04
02
_2
5V
7K
12
PC
14
820P
_0
40
2_
50
V7
K
12
PL2SMB3025500YA_2P
12
PR310K_0402_5%
1 2
PC
51
00
0P
_0
40
2_
50
V7
K
12
PR510K_0402_5%
12
G
D
S
PQ1@SSM3K7002FU_SC70-3
2
13PR11
150K_0402_1%
1 2
PU1ALM358ADT_SO8
+3
-2
01
P8
G4
PR13
100_0402_5%
12
PR166.49K_0402_1%1 2
PR210K_0402_5%
12
PC
21
00
P_
04
02
_5
0V
8J
12
PR22
@150K_0402_1%
12
PC81000P_0402_50V7K
12
PR10
200K_0402_1%
1 2
PR171K_0402_5%
12
PR15
150K_0402_1%
12
PD4
RLZ3.6B_LL34
12
PR
44
99
K_
04
02
_1
%
12
PD2@SM05_SOT23
2
31
PC17@1000P_0402_50V7K
12
PL3HCB2012KF-121T50_0805
1 2
PR122.21K_0402_1%
12
PC
72200
P_
04
02
_5
0V
7K
12
PR20
@150K_0402_1%
1 2
PC12
@1000P_0402_50V7K
12
PL4HCB2012KF-121T50_0805
1 2
PC
18
@0
.01
U_
04
02
_2
5V
7K
12
G
D
S
PQ4@SSM3K7002FU_SC70-3
2
13
PC
13
39
0P
_0
40
2_
50
V7
K 1
2
PR82K_0402_5%
12
PC16
@0.22U_0603_10V7K
12
PR19
@15K_0402_1%1 2
PU1BLM358ADT_SO8
+5
-6
07
P8
G4
PJP1
ACES_88334-057N
11
33
44
55
22
BATT1
CR2032 RTC BATTERY45@
PC
10
.01
U_
04
02
_2
5V
7K
12
PH2
@10KB_0603_1%_TH11-3H103FT
12
PC111000P_0402_50V7K
12
PQ3
TP0610K-T1-E3_SOT23-3
2
13
PR18
@47K_0402_1%1 2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
DL _CHG
DH_C HG
LX_CHG
CH GEN#
BST_CHG
RE GNVA DJ
BA
TT
ACDET
ACSET
IAD
AP
T
CH GEN#
FSTCHG#
ACDET
VIN_1
PA CIN
AC OFF#
AC OFF#
ACSET
VIN_1
PACIN
IR EF <33>
VCTRL<33>
ADP_I<33>
BAT_ID <37>
AC_SET<33>
SUSP#<26,28,33,36,41>
AC_IN <21,33>
STD_ADP <33>
FSTCHG<33>
AC OFF <33>
PACIN_1 <39>
VIN
P4
BATT
VIN
VIN
BATT
B+
VIN
CHG_B+
CHG_B+
P2
VIN
+3VL
BQ24740VREF
1.24VREF
BQ24740VREF
+3VL
+3VL
+3VL
1.24VREF
VIN
Title
Size Document Number R e v
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-3941P 0.1
Charger
38 56Monday, March 16, 2009
2007/05/29 2008/05/29Compal Electronics, Inc.
Charge Detector
PC
12
4
0.1
U_
06
03
_2
5V
7K
12
PD104
1SS355_SOD323-2
12
PR1113K_0402_1%
1 2
PR
14
01
00
K_
04
02
_5
%
12
PR113143K_0402_1%
12
PC1171U_0603_10V6K
12
PC
12
11
00
P_
04
02
_5
0V
8J
12
PR1394.7_1206_5%
12
PR119
47K_0402_5%
12
[email protected]_0402_16V7K
12
PR10510K_0402_5%
12
PR13410K_0402_5%
12
PR10347K_0402_5%
1 2
PC
10
60
.47
U_
06
03
_1
6V
7K
12
PC1021U_0603_6.3V6M
1 2
PC119
1U_0603_10V6K
12
PR126100K_0402_1%
12
PC1110.1U_0402_10V7K
1 2
PR117100K_0402_5%
1 2
PC112
1U_0603_6.3V6M
1 2
PR1040_0402_5%
1 2
PR10147K_0402_5%
1 2
PQ108AO4466_SO8
365 7 8
2
4
1
PR
13
21
00
K_
04
02
_5
%
12
PC
11
64
.7U
_0
80
5_
25
V6
-K
12
PR
12
81
0K
_0
40
2_
5%
12
PC127
22P_0402_50V8J
12
PC
10
8
0.1
U_
06
03
_2
5V
7K
12
PR1120.015_1206_1%
1 2
G
D
S
PQ109SSM3K7002FU_SC70-3
2
13
PD103RLZ4.3B_LL34
12
[email protected]_0603_25V7K
12
PQ110
FDS6690AS_SO8
365 7 8
2
4
1
PR127
10K_0402_1%
12
PQ106DTC115EUA_SC70-3
2
13
PC1180.1U_0402_10V7K
1 2
PQ105DTC115EUA_SC70-3
2
13
PC
12
91
20
0P
_0
40
2_
50
V7
K
12
G
D
S
PQ111SSM3K7002FU_SC70-3
2
13
PC
10
1
47
P_
04
02
_5
0V
8J
12
PC
10
54
.7U
_0
80
5_
25
V6
-K
12
PC
12
2@
0.1
U_
06
03
_2
5V
7K
12 PR122
681K_0402_1%
1 2
PC
11
34
.7U
_0
80
5_
25
V6
-K
12
PR10810_1206_5%
1 2
PD102
1SS355_SOD323-2
12
PR11810K_0402_5%
1 2
PR13720K_0402_1%
1 2
PR10747K_0402_1%
1 2
PU102B
LM393DG_SO8
+5
-6
O7
P8
G4
PR120
133K_0402_1%
12
PQ103
SI4835BDY-T1-E3_SO8
3 65
78
2
4
1
PR12547_1206_5%
12
PL10210U_LF919AS-100M-P3_4.5A_20%
1 2
BQ24740RHDR_QFN28_5X5PU101
AC
P3
LP
MD
4
CH
GE
N1
AC
N2
AC
DE
T5
AC
SE
T6
IADSLP8
SR
P19
BA
T17
IAD
AP
T15
PGND22
SR
SE
T16
ISYNSET14
VADJ12
VDAC11
LP
RE
F7
VREF10
DP
MD
ET
21
LODRV23
CE
LLS
20
SR
N18
AGND9
REGN24
EXTPWR13
PH25
HIDRV26
BTST27
PVCC28
TP29
PR131133K_0402_1%
12
PC
13
16
80
P_
06
03
_5
0V
7K
12
PR
12
91
0K
_0
40
2_
1%
12
PC1230.1U_0402_10V7K
12
PR1231M_0402_5%
1 2
PC
12
00
.22
U_
06
03
_1
0V
7K
12
PC
10
44
.7U
_0
80
5_
25
V6
-K
12
PR13660.4K_0402_1%
1 2
G
D
S
PQ112SSM3K7002FU_SC70-3
2
13
PQ101
SI4835BDY-T1-E3_SO8
365
78
2
4
1
PQ102
FDS6675BZ_SO8
3 65
78
2
4
1
PC
12
82
20
P_
04
02
_5
0V
7K
12
PR1100_0402_5%
1 2
PR115100K_0402_1%
12
G
D
S
PQ113SSM3K7002FU_SC70-3
2
13
PL101HCB2012KF-121T50_0805
1 2
PR109150K_0402_5%
12
PQ104DTA144EUA_SC70-3
2
13
PC1101U_0805_25V6K
1 2
PD101
1SS355_SOD323-2
1 2
PR121200K_0402_1%
12
PC
10
34
.7U
_0
80
5_
25
V6
-K
12
PU103
APL1431LBBC-TR_SOT23-5
NC2
REF4
NC1
CATHODE3
ANODE5
PC1250.1U_0603_25V7K
12
PR114@0_0402_5%
1 2
PR1020.012_2512_1%
1 2
PC
11
54
.7U
_0
80
5_
25
V6
-K
12
PR
13
81
00
K_
04
02
_1
%
12
PU102ALM393DG_SO8
+3
-2
O1
P8
G4
PR
10
62
00
K_
04
02
_5
%
12
PR1241K_0402_5%
1 2
PC
11
44
.7U
_0
80
5_
25
V6
-K
12
G
D
SPQ107SSM3K7002FU_SC70-3
2
13
PC1260.047U_0402_16V7K
12
PC
13
24
.7U
_0
80
5_
25
V6
-K
12
PR1302.15K_0402_1%
1 2
PR13310K_0603_0.1%
12
PC
13
06
80
P_
04
02
_5
0V
7K
12
PR135
10K_0603_0.1%
12
PR11615K_0402_1%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
BST_5V
LX_5V
LG_3V
LX_3V
UG_3VE
NT
RIP
2
UG
1_
3V
UG_5V
BST_3V
EN
TR
IP2
EN
TR
IP1
LG_5V
EC_ON <33,36>
ENTRIP1<37>
3/5V_OK <20,41>
PACIN_1<38>
EN0<6,37>
B++
+5VALWP
VL
+3VALWP
B++
B++
2VREF_51125
B+
+3VL+3VLP
+3VLP
2VREF_51125
VL
+5VALWP
+3VALW
+5VALW
+3VALWP +5VLVL
+3VLB++
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4111P 0.1
3.3VALWP/5VALWP
Custom
39 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
(4.5A,180mils ,Via NO.= 9)
(3A,120mils ,Via NO.= 6)
G
D
S
PQ307SSM3K7002FU_SC70-3
2
13
[email protected]_1206_5%
12
PR317100K_0402_5%
12
PC
30
34
.7U
_0
80
5_
25
V6
-K12
PR3082.2_0402_5%
1 2
PR30420K_0402_1%
1 2
PC
31
34
.7U
_0
80
5_
25
V6
-K
12
PR314100K_0402_5%
12
G
D
S
PQ306SSM3K7002FU_SC70-3
2
13
PR318@604K_0402_1%
1 2
PC
31
6@
0.1
U_
04
02
_2
5V
4K
12
PJP303
PAD-OPEN 4x4m
1 2
PR305140K_0402_1%
1 2
PJP304
PAD-OPEN 2x2m
2 1
+PC309
15
0U
_D
_6
.3V
M
1
2
PL301HCB2012KF-121T50_0805
<BOM Structure>1 2
PR307
0_0402_5%1 2
PC315680P_0603_50V8J
12
PC319@22U_0805_6.3V6M
12
PC
31
7@
0.1
U_
04
02
_2
5V
4K
12
PR30320K_0402_1%
1 2
PC
32
2390P
_0
40
2_
50
V7
K 1
2
PC
30
54
.7U
_0
80
5_
25
V6
-K
12
PQ302AO4466_SO8
365 7 8
2
4
1
PR306113K_0402_1%
1 2
PL3034.7UH_PCMC063T-4R7MN_5.5A_20%
1 2
PC31110U_0805_10V6K
12
+ PC310150U_D_6.3VM
1
2
PC3020.22U_0603_10V7K
12
PJP302
PAD-OPEN 4x4m
1 2
PR312
1M_0402_1%
1 2
PC30610U_0805_6.3V6M
12
PC
30
42200
P_
04
02
_5
0V
7K
12
PR3090_0402_5%
1 2
PR313100K_0402_5%
1 2
PC320
@22U_0805_6.3V6M
12
PR30113.7K_0402_1%
1 2
PC314@680P_0603_50V8J
12
PR311191K_0402_1%
12
PQ304SI4894BDY-T1-E3_SO8
365 7 8
2
4
1
PJP301
PAD-OPEN 2x2m
2 1
PC3070.1U_0402_10V7K
1 2
G
D
S
PQ305SSM3K7002FU_SC70-3
2
13
PC
32
12
20
0P
_0
40
2_
50
V7
K 1
2
PC
30
12200
P_
04
02
_5
0V
7K
12
[email protected]_0603_16V7K
12
PR3164.7_1206_5%
12
PL3024.7UH_SIQB74B-4R7PF_4A_20%
12
PC3080.1U_0402_10V7K
1 2
PU301TPS51125RGER_QFN24_4X4
VR
EF
3
TO
NS
EL
4
EN
TR
IP1
1
VF
B1
2
VF
B2
5
EN
TR
IP2
6
VREG38
DRVL119
VR
EG
51
7
GN
D1
5
VBST122
VIN
16
SK
IPS
EL
14
DRVL212
LL211
VO27
DRVH210
DRVH121
PGOOD23
LL120
VC
LK
18
VBST29
VO124
EN
01
3
P PAD25
G
D
S
PQ308@SSM3K7002FU_SC70-3
2
13
AO4932_SO8
PQ301
D12
1G8
G23
1S/2D5
D11
1S/2D7
S24
1S/2D6
PR30230.9K_0402_1%
1 2
PC3120.1U_0603_25V7K
12
PR3100_0402_5%
1 2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
+5
VA
LW
DH_1.8V
1.8V_B+
DL_1.8V
LX_1.8V
BST1_1.8VBST_1.8V
DH_1.8V_1
+5VALW+5VALW
SYSON<26,33,36>
+1.8VP
+1.8VP
+5VALW
+1.8VP
B+
+1.8V+1.8VP
Title
Size Document Number R ev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-3941P 0.1
1.8VP
40 56Monday, March 16, 2009
2007/05/29 2008/05/29Compal Electronics, Inc.
(7A,280mils ,Via NO.= 14)
PQ402SI4894BDY-T1-E3_SO8
365 7 8
2
4
1
PR40610.7K_0402_1%
1 2
PR405
0_0402_5%
12
PR4020_0402_5%
1 2
PC406470P_0402_50V7K
12
PC4091U_0603_10V6K
12
PL401
HCB1608KF-121T30_0603
1 2
PC413@10P_0402_50V8J
1 2
+
PC
40
82
20
U_
D2
_4
VY
_R
25
M
1
2
PL4022.2UH_PCMC063T-2R2MN_8A_20%
1 2
PR4010_0402_5%
1 2
PU401
TPS51117RGYR_QFN14_3.5x3.5
VOUT3
V5FILT4
EN
_P
SV
1
TON2
VFB5
PGOOD6 DRVL 9
DRVH 13
LL 12
GN
D7
PG
ND
8
TRIP 11
V5DRV 10
VB
ST
14
TP
15
PC
41
4@
0.1
U_
04
02
_2
5V
4K
12
[email protected]_1206_5%
12
PR404255K_0402_1%
1 2
PQ401AO4466_SO8
365 7 8
2
4
1
PC4020.1U_0402_10V7K
1 2
PC412@680P_0603_50V7K1
2
PJP401
PAD-OPEN 4x4m
1 2
PC
40
52
20
0P
_0
40
2_
50
V7
K
12
PC401@1000P_0402_50V7K
12
PR403316_0402_1%
12
PC
40
44
.7U
_0
80
5_
25
V6
-K
12
PR40910K_0603_0.1%
12
PC4154.7U_0805_10V6K
12
PC
40
34
.7U
_0
80
5_
25
V6
-K
12
PR410
0_0402_5%
1 2
PR408
14.3K_0603_0.1%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
LX_1.2V
UG1_1.1V
BST_1.2V
+1.2VALWP
LG_1.2V
UG1_1.2V
LG_1.1V
+1.1VSP
UG_1.2V
+1.1VSP
BST_1.1V
LX_1.1V
UG_1.1V
+1.2VALWP
+1.1VS
+1.1VSP
B+++
VCCP_POK
SUSP#<26,28,33,36,38>
3/5V_OK <20,39>
B+++
+1.2VALWP
B+
+1.1VSP
+5VALW
B+++
+1.1VS+1.1VSP +1.2VALW+1.2VALWP
+1.1VSP +1.1VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4111P 0.1
1.1VSP/1.2VALWP
Custom
41 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
(4A,160mils ,Via NO.=8)(6A,240mils ,Via NO.=12)
PQ503FDS6690AS_NL_SO8
36 578
2
4
1
PC520470P_0603_50V8J
12
PL5012.2UH_PCMC063T-2R2MN_8A_20%
12
PJP501
PAD-OPEN 4x4m
1 2
PR5154.7_1206_5%
12
PJP503
PAD-OPEN 4x4m
1 2
PC
51
64
70
P_
04
02
_5
0V
7K
12
PC
51
8@
0.1
U_
04
02
_2
5V
4K
12
PC
50
44
.7U
_0
80
5_
25
V6
-K
12
PC5060.1U_0402_10V7K
12
PC
50
14
.7U
_0
80
5_
25
V6
-K
12
PR50224.9K_0402_1%
1 2
PC507
0.1U_0402_10V7K
1 2
PC
50
94
.7U
_0
80
5_
6.3
V6
K
12
+
PC
51
12
20
U_
B2
_2
.5V
M
1
2
PC5120.1U_0402_16V7K
12
PJP502
PAD-OPEN 4x4m
1 2
PC
50
22
20
0P
_0
40
2_
50
V7
K
12
PC
50
52
20
0P
_0
40
2_
50
V7
K
12
PR5180_0402_5%
1 2
PC
51
74
.7U
_0
80
5_
25
V6
-K
12
PR51115.4K_0402_1%
1 2
[email protected]_0603_25V7K
12
PR5080_0402_5%12
+
PC
50
82
20
U_
D2
_4
VY
_R
25
M 1
2
PR51710_0402_5%
1 2
PR5143.3_0402_5%
1 2
PC5130.1U_0402_10V7K
12
PR50411.5K_0402_1%
12
PC
52
1@
0.1
U_
04
02
_2
5V
4K
12
PC
51
04
.7U
_0
80
5_
6.3
V6
K
12
PR50318.7K_0402_1%
12
PR5130_0402_5%
12
PR5164.7_1206_5%
12
PR5090_0402_5%
12
PC5154.7U_0805_10V6K
12
PR51010.5K_0402_1%
12
PQ504AO4468_SO8
365 7 8
2
4
1
PC5141U_0603_10V6K
12
PU501
TPS51124RGER_QFN24_4x4
GN
D3
TO
NS
EL
4
VO
11
VF
B1
2
VF
B2
5
VO
26
EN28
DR VL119
TR
IP1
17
V5
FIL
T1
5
VBST122
V5
IN1
6
TR
IP2
14
DR VL212
LL211
PGOOD27
DR VH210
DR VH121
EN123
LL120
PG
ND
11
8
VBST29
PGOOD124
PG
ND
21
3
P PAD25
PQ501
AO4466_SO8
36 578
2
4
1
PC519470P_0603_50V8J
12
PR5050_0402_5%
12
PR519
1K_0402_5%
12
PR5062.2_0402_5%
12
PR51233K_0402_5%
1 2
PL502HCB2012KF-121T50_0805
12
PL5033.3UH 30% MSCDRI-7030AB-3R3N 4.1A
1 2
PR50111.5K_0402_1%
1 2
PR5072.2_0402_5%
12
PQ502AO4466_SO8
365 7 8
2
4
1
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
VREF1.5V
SUSP<36>
SYSON#<34,35,36>
SUSP<36>
+5VALW
+0.9VP
+1.8V
+5VALW
+1.5VSP
+1.8V
+0.9VP +0.9V
+1.5VSP +1.5VS
+2.5VSP
+3VS
+2.5VSP +2.5VS
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4111P 0.1
0.9VSP/2.5VSP/1.5VSP
Custom
42 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
(2A,80mils ,Via NO.= 4)
(1A,40mils ,Via NO.= 2)
(500mA,40mils ,Via NO.= 1)
(500mA,40mils ,Via NO.= 1)
G
D
S
PQ601SSM3K7002FU_SC70-3
2
13
PC613
10U_0805_10V4Z
12
PJP602
PAD-OPEN 3x3m
1 2
PJP603
PAD-OPEN 3x3m
1 2
PC601
10U_0805_10V4Z
12
PU602APL5508-25DC-TRL_SOT89-3
IN2
GND
1
OUT3
PJP601
PAD-OPEN 3x3m
1 2
PC
60
71
U_
06
03
_6
.3V
6M
12
PC61410U_0805_6.3V6M
12
PR6020_0402_5%
1 2
PC60510U_0805_6.3V6M
12
PU603
G2992F1U_SO8
VOUT4
NC5
GND2
VREF3
VIN1
VCNTL6
NC7
NC8
TP9
PR6080_0402_5%
1 2
PU601
G2992F1U_SO8
VOUT4
NC5
GND2
VREF3
VIN1
VCNTL6
NC7
NC8
TP9
PC
60
84
.7U
_0
80
5_
6.3
V6
K
12
PC
60
40
.1U
_0
40
2_
16
V7
K
12
PC
60
2@
10
U_
08
05
_1
0V
4Z
12
[email protected]_0402_16V7K
12
PC6031U_0603_16V6K
12
PR601
1K_0402_1%
12
PR605@150_1206_5%
12
PC
61
10
.1U
_0
40
2_
16
V7
K
12
PC6121U_0603_16V6K
12
PR604@0_0402_5%
1 2
[email protected]_0402_16V7K
12
G
D
S
PQ602SSM3K7002FU_SC70-3
2
13
PR607
5.1K_0402_1%
12
PC
60
9@
10
U_
08
05
_1
0V
4Z
12
PR603
1K_0402_1%
12
PR606
1K_0402_1%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
BO
OT
_N
B1
ISP
0
+C
PU
_C
OR
E_
0
BO
OT
0
UGATE0
LGATE0
BOOT1
LGATE1
UGATE1
PHASE1
ISP 0PHASE0
ISP 1
+CPU_CORE_0
ISP 1
BO
OT
_N
B
RT
N_
NB
SVD
SVC
UG
AT
E N
B
PH
AS
E N
B
PH
AS
E N
B
UG
AT
E N
B
LG
AT
E N
B
LG
AT
E N
B
VS
EN
_N
B
RT
N1
RT
N0
ISL
62
65
_P
WR
OK
ISL6265_PWROK
UGATE0_1
UGATE1_1
ISL6265_PWROK
VS
EN
0
VS
EN
1
VDD_NB_FB_H<6>
VGATE<33>
SB_PWRGD<6,20,33>
CPU_SVD<6>
CPU_SVC<6>
VR_ON<33>
CPU_VDD0_FB_H<6>
CPU_VDD0_FB_L<6>
VDD_NB_FB_L<6>
VFIX_EN<33>
H_PWRGD<19>
+CPU_CORE_0
+5VS
B+
CPU_B+
CPU_B+
+CPU_CORE_NB
CPU_B+
+5VS
CPU_B+
+3VS+5VS
+CPU_CORE_0
+1.8V
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4111P 0.1
CPU_CORE
Custom
43 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
Connect to EC pin 110.
PC
21
42
20
0P
_0
40
2_
50
V7
K
12
PR2190_0603_5%1 2
PR2120_0402_5%
1 2
PR2111_0603_5%
12
PC
25
73
90
P_
04
02
_5
0V
7K
12
PC
25
41
80
0P
_0
40
2_
50
V7
K 1
2
PC
25
61
80
0P
_0
40
2_
50
V7
K 1
2PR225
255_0402_1%
1 2
PC2411000P_0402_50V7K
12
PR2220_0402_5%
1 2
PC
23
93
30
P_
04
02
_5
0V
7K
12
PQ208IRFH7932TRPBF_PQFN
35
2
4
1
PR
20
60
_0
40
2_
5%
12
PC
20
93
3P
_0
40
2_
50
V8
K
12
PR246 100K_0402_5%1 2
PR232
6.81K_0402_1%
1 2
PC
22
22
20
0P
_0
40
2_
50
V7
K
12
PC227180P_0402_50V8J
1 2
PC251
680P_0603_50V7K
12
PR226
0_0603_5%1 2
PC
23
74
.7U
_0
80
5_
25
V6
-K 12
[email protected]_0603_1%
1 2
PC
21
34
.7U
_0
80
5_
25
V6
-K
12
PC
23
64
.7U
_0
80
5_
25
V6
-K 12
PR
21
04
4.2
K_
04
02
_1
%
12
PL202SMB3025500YA_2P
12
G
D
S
PQ209
@SSM3K7002FU_SC70-3
2
13
PC
25
3
47
P_
04
02
_5
0V
8J
12
PC
22
04
.7U
_0
80
5_
25
V6
-K 12
PR
20
90
_0
40
2_
5%
12
PC
24
31
00
0P
_0
40
2_
50
V7
K
1 2
[email protected]_0402_1%
12
PR
22
13
.65
K_
04
02
_1
%
12
PC
24
93
30
0P
_0
40
2_
50
V7
K 1
2
PR
24
44
.7_
12
06
_5
%
12
PQ206IRF8714TRPBF_SO8
4
7 865
123
PC
25
01
80
0P
_0
40
2_
50
V7
K
12
PL203
0.36UH_PCMC104T-R36MN1R17_30A_20%
12
PR230
54.9K_0402_1%
1 2
PR2180_0402_5%1 2
PC
21
82200
P_
06
03
_5
0V
7K
12
PC2262200P_0603_50V7K
12
PR241@0_0402_5%
1 2
PC
24
6@
100
0P
_0
40
2_
50
V7
K1
2
PC
20
32
20
0P
_0
40
2_
50
V7
K
12
PR
22
04
.7_
12
06
_5
%
12
PC
21
51000
P_
04
02
_5
0V
7K
12
PC2190.1U_0603_25V7K
1 2
PR
24
54
.7_
12
06
_5
%
12
PR2370_0402_5%
1 2
PU201
ISL6265IRZ-T_QFN48_6X6
PWROK3
SVD4
OFS/VFIXEN1
PGOOD2
SVC5
ENABLE6
OCSET8
VD
IFF
11
9
RT
N1
17
VS
EN
01
5
VW
12
2
RT
N0
16
ISN
01
4
VW012
COMP011
RBIAS7
FB010
CO
MP
12
1
ISP
12
3
FB
12
0
VS
EN
11
8
VDIFF09
ISN
12
4
ISP
01
3
BOOT125
UGATE126
PHASE127
PGND128
LGATE129
PVCC30
LGATE031
PGND032
PHASE033
UGATE034
BOOT035
BOOT_NB36
UG
AT
E_
NB
37
PH
AS
E_
NB
38
LG
AT
E_
NB
39
PG
ND
_N
B4
0
OC
SE
T_
NB
41
RT
N_
NB
42
VS
EN
_N
B4
3
FS
ET
_N
B4
4
CO
MP
_N
B4
5
FB
_N
B4
6
VC
C4
7
VIN
48
TP
49
PC
24
7@
100
0P
_0
40
2_
50
V7
K1
2
PL2014.7UH_PCMC063T-4R7MN_5.5A_20%
12
PR227
1K_0402_1%
1 2
PR2082_0402_5%
1 2
PR224
10K_0402_1%
1 2
PR2052_0402_5%
1 2
PC2240.22U_0603_10V7K
1 2
PR234 @100K_0402_5%1 2
PC
22
14
.7U
_0
80
5_
25
V6
-K 12
PC
26
1
47
P_
04
02
_5
0V
8J
12
PR
24
24
.7_
12
06
_5
%
12
PR2350_0402_5%
1 2
PC232@1200P_0402_50V7K
12
PC
24
83
30
0P
_0
40
2_
50
V7
K
12
PC
24
4@
100
0P
_0
40
2_
50
V7
K1
2
PC
20
81200
P_
04
02
_5
0V
7K
12
PC223
4700P_0402_25V7K
1 2
[email protected]_0603_1%
1 2
PC242@1000P_0402_50V7K
12
PQ203IRF8714TRPBF_SO8<BOM Structure>
4
7 865
123
PC2290.1U_0603_25V7K 1 2
PC
23
54
.7U
_0
80
5_
25
V6
-K
12
PC230@1000P_0402_50V7K
12
PC231@180P_0402_50V8J
12
PR2390_0402_5%
1 2
PC
23
84
70
P_
04
02
_5
0V
7K
12
PC
25
24
7P
_0
40
2_
50
V8
J 1
2
PR240@1K_0402_1%
12
PC2160.1U_0603_25V7K
12
PC
20
11
0U
_0
80
5_
6.3
V6
M
12
PC2060.1U_0402_16V7K
12
PR215@10K_0402_5%
1 2
PC
26
0
47
P_
04
02
_5
0V
8J
12
PR2030_0402_5%
12
[email protected]_0402_1%
12
PC2070.1U_0402_16V7K
12
PR
22
94
.7_
12
06
_5
%
12
PR2282.2_0603_5%
1 2PL204
0.36UH_PCMC104T-R36MN1R17_30A_20%
12
PC2170.22U_0603_10V7K
1 2
PR223
107K_0402_1%
1 2
PQ205IRFH7932TRPBF_PQFN
35
2
4
1
PC
24
02
20
0P
_0
40
2_
50
V7
K 1
2
PR20422K_0402_1%
1 2
+ PC202220U_B2_2.5VM
1
2
PC233@4700P_0402_25V7K
12
PC
25
82
20
0P
_0
40
2_
50
V7
K
12
PC
23
44
.7U
_0
80
5_
25
V6
-K
12
PC2051000P_0402_50V7K
1 2
PC
25
9
47
P_
04
02
_5
0V
8J
12
PR2142.2_0603_5%
1 2
PR243@255_0402_1%
12
PC
24
5@
100
0P
_0
40
2_
50
V7
K1
2
PQ202
AO4466_SO8
3 65
78
2
4
1
PR
21
61
0K
_0
40
2_
1%
12
PQ201AO4468_SO8
3 65
78
2
4
1
PR213@0_0402_5%
1 2
PC225
1200P_0402_50V7K
1 2
PC
25
53
90
P_
04
02
_5
0V
7K
12
PR
23
13
.65
K_
04
02
_1
%
12
PC204
4.7
U_
08
05
_2
5V
6-K1
2
PC2281000P_0402_50V7K
1 2
PR
20
71
7.4
K_
04
02
_1
%
12
+
PC
26
26
8U
_2
5V
_M
1
2
PC2102.2U_0603_6.3V6K
12
+
PC
21
16
8U
_2
5V
_M
1
2
PC
21
24
.7U
_0
80
5_
25
V6
-K
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 1.C
Power Changed-List History-1
Custom
44 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
V ers io n C h a n g e L ist ( V ers io n C h a n g e L ist ( V ers io n C h a n g e L ist ( V ers io n C h a n g e L ist ( P . I . R . L ist ) fo r P ow er C ircu itP . I . R . L ist ) fo r P ow er C ircu itP . I . R . L ist ) fo r P ow er C ircu itP . I . R . L ist ) fo r P ow er C ircu it
P aP aP aP a g e #g e #g e #g e # TTTT it l ei t l ei t l ei t l e R e v .R e v .R e v .R e v .I s s u e DI s s u e DI s s u e DI s s u e D e s c r ip t i o ne s c r ip t i o ne s c r ip t i o ne s c r ip t i o nI t e mI t e mI t e mI t e m R e qR e qR e qR e q u e s tu e s tu e s tu e s t
O w nO w nO w nO w n e re re re rD a t eD a t eD a t eD a t e S oS oS oS o lu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io n
1 37PL3 change the value from SMB3025500YA_2P to HCB2012KF-121T50_0805
and add PL4 the same of the value.
2 41PC508 and PC511 change the value from 220U_6.3VM_R15 to
220U_D24VY_R25M
3
4 43
Add PJP503
5
41
PC202 change the value from 220U_6.3VM_R15 to 220U_D24VY_R25M
7
43
Add PC241 PC242 PC243, and the value are 1000P、 、 _0402_50V7K.
Reserve PC244 PC245 PC246 PC247, and the、 、 、 value are
1000P_0402_50V7K.
43 Add PJP201 PJ、 P202
9/29
9/29
9/29
9/29
9/29
9/29
DC Connector
/CPU_OTPfor Layout
HW request
Compal
Compal1.1VSP/1.2VALWP
1.1VSP/1.2VALWP Compal HW request
CPU_CORE Compal HW request
CPU_CORE CompalTI FAE suggested that after he review
the layout.
CPU_CORETI FAE suggested that after he review
the layout.Compal6
38 Charger 9/29 Compal the footprint is wrong Change the footprint of PR102
8 37DC Connector
/CPU_OTP10/08 Compal for Layout These two choke are parallel ,it's not series.
9 38 Charger 10/08 Compal the footprint is wrong Change the footprint of PR102
10 40 1.8VP 10/08 Compal Delete PC410 and PC411
11 41 1.1VSP/1.2VALWP 10/08 Compal Add PR517 P、 R518PWR request
PWR request
12 37
3.3VALWP/5VALWP
11/01 Compal PWR request Add PD4 P、 C12
13 37 11/01 Compal for Layout change PQ301, Cencel PQ303
DC Connector
/CPU_OTP
14 43 CPU_CORE EMI requestCompal11/02 Add PC248, PC249, PC250
15 37 3.3VALWP/5VALWP 11/12 Compal for Layout Change PC310, add PC319
16
17
Add PU302, control signal changed to ACOFF12/31 PWR requestCompal3.3VALWP/5VALWP37
Change PR221 and PR231 to 16.6K_ohm
Change PR217 and PR233 to 4.02K_ohm
Change PR223 to 17.8K_ohm
Change PR224 to 100K_ohm
12/31CPU_CORE Compal Vendor request43
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 1.C
Power Changed-List History-1
Custom
45 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
V ers io n C h a n g e L ist ( V ers io n C h a n g e L ist ( V ers io n C h a n g e L ist ( V ers io n C h a n g e L ist ( P . I . R . L ist ) fo r P ow er C ircu itP . I . R . L ist ) fo r P ow er C ircu itP . I . R . L ist ) fo r P ow er C ircu itP . I . R . L ist ) fo r P ow er C ircu it
P aP aP aP a g e #g e #g e #g e # TTTT it l ei t l ei t l ei t l e R e v .R e v .R e v .R e v .I s s u e DI s s u e DI s s u e DI s s u e D e s c r ip t i o ne s c r ip t i o ne s c r ip t i o ne s c r ip t i o nI t e mI t e mI t e mI t e m R e qR e qR e qR e q u e s tu e s tu e s tu e s t
O w nO w nO w nO w n e re re re rD a t eD a t eD a t eD a t e S oS oS oS o lu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io n
18
19
20
21
22
24
23
25
26
38 Charger 01/08 Compal EMI request Add PC128 220pF
DC Connector
/CPU_OTP
37 01/09 Compal AC LED change to KBC control AC_LED# connect to KBC pin 97
Change PC309 to D size and add PC32001/14 Compal for layout3.3VALWP/5VALWP37
Charger 02/2738 Compal EMI request CHG_B+ Add 1200pF and 330pF
02/27 Compal EMI request CPU_B+ Add 1800pF*2 2200pF*1 and 390pF*243 CPU_CORE
02/27 Compal3.3VALWP/5VALWP37 EMI request B+ Add 2200pF and 390pF
DC Connector
/CPU_OTP
02/2737 Compal EMI request VIN Add 2200pF and 390pF, ADPIN add 820pF
37 3.3VALWP/5VALWP 02/27 Change OTC shun down pin.Compal Change OTC shun down pin to PU301 pin13.
CPU_CORE Compal03/04 Change high-side MOS for WWAN issue Change PQ203 and PQ206 to powerpak43
27 CPU_CORE Compal03/04 HW request add H_PWRGD control net43
28 Compal04/02 AC LED issue37 Chaange AC_LED# pull high to +3VLDC Connector
/CPU_OTP
29 04/24 Compal acoustic noise43 Add PC262CPU_CORE
04/24 Compal HW CPU thermal protection
change to 95 +-3 degree C
Chaange PR12 to 2.21K_ohm30 37
3731 1.1VSP/1.2VALWP
DC Connector
/CPU_OTP
05/23 Compal +1.2VALW leakage Add PR519
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 1.C
HW Changed-List History-1
Custom
46 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
V ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it
I t e mI t e mI t e mI t e m I s s u e DI s s u e DI s s u e DI s s u e D e s c r ip t i o ne s c r ip t i o ne s c r ip t i o ne s c r ip t i o nD a t eD a t eD a t eD a t eR e qR e qR e qR e q u e s tu e s tu e s tu e s t
O w nO w nO w nO w n e re re re r S oS oS oS o lu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io n R e v .R e v .R e v .R e v .P aP aP aP a g e #g e #g e #g e # TTTT it l ei t l ei t l ei t l e
1111 2 52 52 52 5 LLLL A NA NA NA N 1 01 01 01 0 / 2 9/ 2 9/ 2 9/ 2 9 H WH WH WH W C h a n g e L A N C hC h a n g e L A N C hC h a n g e L A N C hC h a n g e L A N C h ip U 2 0 f r o m M a r v e l l 8 8 E 8 0 4 2 t oip U 2 0 f r o m M a r v e l l 8 8 E 8 0 4 2 t oip U 2 0 f r o m M a r v e l l 8 8 E 8 0 4 2 t oip U 2 0 f r o m M a r v e l l 8 8 E 8 0 4 2 t o
R e a l t e kR e a l t e kR e a l t e kR e a l t e k R T L 8 1 0 2 E L R T L 8 1 0 2 E L R T L 8 1 0 2 E L R T L 8 1 0 2 E LU pU pU pU p d a t e t h e L A N D e s ig n p a g e a n d s u p p o r t c i r c u itd a t e t h e L A N D e s ig n p a g e a n d s u p p o r t c i r c u itd a t e t h e L A N D e s ig n p a g e a n d s u p p o r t c i r c u itd a t e t h e L A N D e s ig n p a g e a n d s u p p o r t c i r c u it 0 . 20 . 20 . 20 . 2
2222 2 52 52 52 5 LLLL A NA NA NA N 1 01 01 01 0 / 2 9/ 2 9/ 2 9/ 2 9 H P QH P QH P QH P Q A d d A d d A d d A d d P O E (P o w e r O v e r E t h e r n e t ) d e s i g nP O E (P o w e r O v e r E t h e r n e t ) d e s i g nP O E (P o w e r O v e r E t h e r n e t ) d e s i g nP O E (P o w e r O v e r E t h e r n e t ) d e s i g n U pU pU pU p d a t e t h e L A N D e s ig n p a g e a n d s u p p o r t c i r c u itd a t e t h e L A N D e s ig n p a g e a n d s u p p o r t c i r c u itd a t e t h e L A N D e s ig n p a g e a n d s u p p o r t c i r c u itd a t e t h e L A N D e s ig n p a g e a n d s u p p o r t c i r c u it 0 . 20 . 20 . 20 . 2
0 . 20 . 20 . 20 . 23333 1 61 61 61 6 CCCC R TR TR TR T 1 01 01 01 0 / 2 9/ 2 9/ 2 9/ 2 9 H WH WH WH W C R TC R TC R TC R T c a n n o t d i s p la y c a n n o t d i s p la y c a n n o t d i s p la y c a n n o t d i s p la y C h a n g e t h e C R T C o n n .C h a n g e t h e C R T C o n n .C h a n g e t h e C R T C o n n .C h a n g e t h e C R T C o n n . s ig n a ls c o n n ec t io n f i r s t . s ig n a ls c o n n ec t io n f i r s t . s ig n a ls c o n n ec t io n f i r s t . s ig n a ls c o n n ec t io n f i r s t .
W a i t c o r r e c t s y m b o l fW a i t c o r r e c t s y m b o l fW a i t c o r r e c t s y m b o l fW a i t c o r r e c t s y m b o l f o r f ixo r f ixo r f ixo r f ix
4444 2 92 92 92 9 A u d ioA u d ioA u d ioA u d io 0 . 20 . 20 . 20 . 21 01 01 01 0 / 3 0/ 3 0/ 3 0/ 3 0 H WH WH WH W S p e a k eS p e a k eS p e a k eS p e a k e r n o s o u n dr n o s o u n dr n o s o u n dr n o s o u n d A d d R 9 7 3 (1 0 K _ 0 4 0 2 ) t o + 3 V A L W o n H P _ D E T #A d d R 9 7 3 (1 0 K _ 0 4 0 2 ) t o + 3 V A L W o n H P _ D E T #A d d R 9 7 3 (1 0 K _ 0 4 0 2 ) t o + 3 V A L W o n H P _ D E T #A d d R 9 7 3 (1 0 K _ 0 4 0 2 ) t o + 3 V A L W o n H P _ D E T #
FFFF A NA NA NA N44445555 0 . 20 . 20 . 20 . 2C h a n g e J P 2 P C B F o o t p r i n t f r o m A C E S _ 8 5 2 0 4 - 0 2C h a n g e J P 2 P C B F o o t p r i n t f r o m A C E S _ 8 5 2 0 4 - 0 2C h a n g e J P 2 P C B F o o t p r i n t f r o m A C E S _ 8 5 2 0 4 - 0 2C h a n g e J P 2 P C B F o o t p r i n t f r o m A C E S _ 8 5 2 0 4 - 0 2 0 0 1 _ 2 P t o0 0 1 _ 2 P t o0 0 1 _ 2 P t o0 0 1 _ 2 P t o
A C E S _ 8A C E S _ 8A C E S _ 8A C E S _ 8 8 2 3 1 - 0 2 0 0 1 _ 2 P8 2 3 1 - 0 2 0 0 1 _ 2 P8 2 3 1 - 0 2 0 0 1 _ 2 P8 2 3 1 - 0 2 0 0 1 _ 2 PFFFF A N C o n n . n o t c o r r e c t p a r tA N C o n n . n o t c o r r e c t p a r tA N C o n n . n o t c o r r e c t p a r tA N C o n n . n o t c o r r e c t p a r tH WH WH WH W1 11 11 11 1 / 0 1/ 0 1/ 0 1/ 0 1
6666 2 92 92 92 9 S pS pS pS p ea k e rea k e rea k e rea k e r 0 . 20 . 20 . 20 . 21 11 11 11 1 / 0 1/ 0 1/ 0 1/ 0 1 H WH WH WH W S p e a k e r C o n n . n o t c o r r e c t p aS p e a k e r C o n n . n o t c o r r e c t p aS p e a k e r C o n n . n o t c o r r e c t p aS p e a k e r C o n n . n o t c o r r e c t p a r tr tr tr t C h a n g e J P 2 0 P C B F o o t p r i n t f r o m A C E S _ 8 5 2 0 4 - 0 4 0C h a n g e J P 2 0 P C B F o o t p r i n t f r o m A C E S _ 8 5 2 0 4 - 0 4 0C h a n g e J P 2 0 P C B F o o t p r i n t f r o m A C E S _ 8 5 2 0 4 - 0 4 0C h a n g e J P 2 0 P C B F o o t p r i n t f r o m A C E S _ 8 5 2 0 4 - 0 4 0 0 1 _ 4 P t o0 1 _ 4 P t o0 1 _ 4 P t o0 1 _ 4 P t o
A C E S _ 8A C E S _ 8A C E S _ 8A C E S _ 8 8 2 3 1 - 0 4 0 0 1 _ 4 P8 2 3 1 - 0 4 0 0 1 _ 4 P8 2 3 1 - 0 4 0 0 1 _ 4 P8 2 3 1 - 0 4 0 0 1 _ 4 P
7777 3 43 43 43 4 M D CM D CM D CM D C 1 11 11 11 1 / 0 1/ 0 1/ 0 1/ 0 1 H WH WH WH W M D C C o n n . n o t c o r r e c t M D C C o n n . n o t c o r r e c t M D C C o n n . n o t c o r r e c t M D C C o n n . n o t c o r r e c t p a r tp a rtp a rtp a rt 0 . 20 . 20 . 20 . 2C h a n g e J P 2 0 P C B F o o t p r i n t f r o m A C E S _ 8 8 0 1 8 - 1C h a n g e J P 2 0 P C B F o o t p r i n t f r o m A C E S _ 8 8 0 1 8 - 1C h a n g e J P 2 0 P C B F o o t p r i n t f r o m A C E S _ 8 8 0 1 8 - 1C h a n g e J P 2 0 P C B F o o t p r i n t f r o m A C E S _ 8 8 0 1 8 - 1 2 4 G _ 1 2 P t o2 4 G _ 1 2 P t o2 4 G _ 1 2 P t o2 4 G _ 1 2 P t o
A C E S _ 8 8A C E S _ 8 8A C E S _ 8 8A C E S _ 8 8 0 2 0 - 1 2 1 0 1 _ 1 2 P0 2 0 - 1 2 1 0 1 _ 1 2 P0 2 0 - 1 2 1 0 1 _ 1 2 P0 2 0 - 1 2 1 0 1 _ 1 2 P
8888 1 1 ,1 1 ,1 1 ,1 1 , 3 53 53 53 5 TTTT V _ O U TV _ O U TV _ O U TV _ O U T 1 11 11 11 1 / 0 5/ 0 5/ 0 5/ 0 5 H WH WH WH W T V - O U T F u nT V - O U T F u nT V - O U T F u nT V - O U T F u n c t i o n n o s u p p o r tc t i o n n o s u p p o r tc t i o n n o s u p p o r tc t i o n n o s u p p o r t DDDD e l R 5 9 , R 6 0 , R 6 1 , R 1 1 5 , R 1 1 6 , R 1 1 7 a n d T V - O U T r e l a t e d d e s i g n .e l R 5 9 , R 6 0 , R 6 1 , R 1 1 5 , R 1 1 6 , R 1 1 7 a n d T V - O U T r e l a t e d d e s i g n .e l R 5 9 , R 6 0 , R 6 1 , R 1 1 5 , R 1 1 6 , R 1 1 7 a n d T V - O U T r e l a t e d d e s i g n .e l R 5 9 , R 6 0 , R 6 1 , R 1 1 5 , R 1 1 6 , R 1 1 7 a n d T V - O U T r e l a t e d d e s i g n . 0 . 20 . 20 . 20 . 2
9999 1 1 ,1 1 ,1 1 ,1 1 , 2 12 12 12 1 N B / S B T h eN B / S B T h eN B / S B T h eN B / S B T h e rm a lrm a lrm a lrm a l 1 11 11 11 1 / 0 5/ 0 5/ 0 5/ 0 5 H WH WH WH W N B T h e r mN B T h e r mN B T h e r mN B T h e r m a l F u n c t i o n n o s u p p o r t ( l o c a t e t o o f a r )a l F u n c t i o n n o s u p p o r t ( l o c a t e t o o f a r )a l F u n c t i o n n o s u p p o r t ( l o c a t e t o o f a r )a l F u n c t i o n n o s u p p o r t ( l o c a t e t o o f a r ) C a n c e l N B _ T H E R M A L _ D A / D C c o n n e c t i o n b eC a n c e l N B _ T H E R M A L _ D A / D C c o n n e c t i o n b eC a n c e l N B _ T H E R M A L _ D A / D C c o n n e c t i o n b eC a n c e l N B _ T H E R M A L _ D A / D C c o n n e c t i o n b e t w een N B a n dt w een N B a n dt w een N B a n dt w een N B a n d
S BS BS BS B , d e l C 5 0 0, d e l C 5 0 0, d e l C 5 0 0, d e l C 5 0 00 . 20 . 20 . 20 . 2
0 . 20 . 20 . 20 . 21 01 01 01 0 2 1 ,2 1 ,2 1 ,2 1 , 3 13 13 13 1 S BS BS BS B S A T A S A T A S A T A S A T A 1 11 11 11 1 / 0 5/ 0 5/ 0 5/ 0 5 H WH WH WH W S B SS B SS B SS B S A T A P o r t 5 c h a n g e t o P o r t 2 f o r A T I C o m m o nA T A P o r t 5 c h a n g e t o P o r t 2 f o r A T I C o m m o nA T A P o r t 5 c h a n g e t o P o r t 2 f o r A T I C o m m o nA T A P o r t 5 c h a n g e t o P o r t 2 f o r A T I C o m m o n
DDDD e s i g ne s i g ne s i g ne s i g n
C h a n g e S B S A T A C h a n g e S B S A T A C h a n g e S B S A T A C h a n g e S B S A T A p o rt 5 t o p o r t 2p o rt 5 t o p o r t 2p o rt 5 t o p o r t 2p o rt 5 t o p o r t 2
1 11 11 11 1 0 . 20 . 20 . 20 . 22 12 12 12 1 S BS BS BS B S A T A S A T A S A T A S A T A 1 11 11 11 1 / 0 5/ 0 5/ 0 5/ 0 5 H WH WH WH W S B S A T A _ A C T # P u l l H ig h b e c o mS B S A T A _ A C T # P u l l H ig h b e c o mS B S A T A _ A C T # P u l l H ig h b e c o mS B S A T A _ A C T # P u l l H ig h b e c o m e + 3 V Se + 3 V Se + 3 V Se + 3 V S C h a n g e R 3 4 3 . 1 p o w e r r a i l f r o m + 5 V S t o + 3 VC h a n g e R 3 4 3 . 1 p o w e r r a i l f r o m + 5 V S t o + 3 VC h a n g e R 3 4 3 . 1 p o w e r r a i l f r o m + 5 V S t o + 3 VC h a n g e R 3 4 3 . 1 p o w e r r a i l f r o m + 5 V S t o + 3 V S . I n s t a l l R 3 4 3 .S . I n s t a l l R 3 4 3 .S . I n s t a l l R 3 4 3 .S . I n s t a l l R 3 4 3 .
1 21 21 21 2 2 12 12 12 1 0 . 20 . 20 . 20 . 2SSSS B G P I OB G P I OB G P I OB G P I O 1 11 11 11 1 / 0 5/ 0 5/ 0 5/ 0 5 H WH WH WH W CCCC h a n g e S B G P I O r e f e r t o J B K 0 0 f o r c o m m o nh a n g e S B G P I O r e f e r t o J B K 0 0 f o r c o m m o nh a n g e S B G P I O r e f e r t o J B K 0 0 f o r c o m m o nh a n g e S B G P I O r e f e r t o J B K 0 0 f o r c o m m o n 1 . C o n n e c t U 1 5 . C 6 t o G1 . C o n n e c t U 1 5 . C 6 t o G1 . C o n n e c t U 1 5 . C 6 t o G1 . C o n n e c t U 1 5 . C 6 t o G N D b y 0 _ 0 4 0 2 .N D b y 0 _ 0 4 0 2 .N D b y 0 _ 0 4 0 2 .N D b y 0 _ 0 4 0 2 .
2 . C h a n g e W L O F F # f r o m G P I O 5 0 t o G P I O 62 . C h a n g e W L O F F # f r o m G P I O 5 0 t o G P I O 62 . C h a n g e W L O F F # f r o m G P I O 5 0 t o G P I O 62 . C h a n g e W L O F F # f r o m G P I O 5 0 t o G P I O 6 1 .1 .1 .1 .
3 . C h a n g e B T _ C O M B O _ E N # f r o m G P I O 53 . C h a n g e B T _ C O M B O _ E N # f r o m G P I O 53 . C h a n g e B T _ C O M B O _ E N # f r o m G P I O 53 . C h a n g e B T _ C O M B O _ E N # f r o m G P I O 5 1 t o G P I O 6 2 .1 t o G P I O 6 2 .1 t o G P I O 6 2 .1 t o G P I O 6 2 .
4 . C h a n g e W W O F F # f r o m G P I O 5 2 t o G P I O 6 3 .4 . C h a n g e W W O F F # f r o m G P I O 5 2 t o G P I O 6 3 .4 . C h a n g e W W O F F # f r o m G P I O 5 2 t o G P I O 6 3 .4 . C h a n g e W W O F F # f r o m G P I O 5 2 t o G P I O 6 3 .
1 31 31 31 3 3 13 13 13 1 0 . 20 . 20 . 20 . 2S BS BS BS B S A T A S A T A S A T A S A T A 1 11 11 11 1 / 0 5/ 0 5/ 0 5/ 0 5 H WH WH WH W V e r t i c aV e r t i c aV e r t i c aV e r t i c a l L 5 1 1 < - -> 4 , 2 < - -> 3 f o r l a y o u t r o u t in gl L 5 1 1 < - -> 4 , 2 < - -> 3 f o r l a y o u t r o u t in gl L 5 1 1 < - -> 4 , 2 < - -> 3 f o r l a y o u t r o u t in gl L 5 1 1 < - -> 4 , 2 < - -> 3 f o r l a y o u t r o u t in g V e r t i c a l L 5 1 1 < - - > 4 , 2 < - - > 3 f o r l a y o u tV e r t i c a l L 5 1 1 < - - > 4 , 2 < - - > 3 f o r l a y o u tV e r t i c a l L 5 1 1 < - - > 4 , 2 < - - > 3 f o r l a y o u tV e r t i c a l L 5 1 1 < - - > 4 , 2 < - - > 3 f o r l a y o u t ro u t in g ro u t in g ro u t in g ro u t in g
1 41 41 41 4 2 92 92 92 9 A u d io HA u d io HA u d io HA u d io H P O U TP O U TP O U TP O U T 1 11 11 11 1 / 0 5/ 0 5/ 0 5/ 0 5 H WH WH WH W 0 . 20 . 20 . 20 . 2A d d A d d A d d A d d 1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R / L1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R / L1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R / L1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R / L A d d 1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R / LA d d 1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R / LA d d 1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R / LA d d 1 5 0 U F C a p s f o r e a c h D O C K _ L O U T _ R / L
1 51 51 51 5 2 52 52 52 5 L A NL A NL A NL A N T r a n s f e r m o r T r a n s f e r m o r T r a n s f e r m o r T r a n s f e r m o r 1 11 11 11 1 / 0 5/ 0 5/ 0 5/ 0 5 H WH WH WH W C o r r e c t C o r r e c t C o r r e c t C o r r e c t U 1 9 L A N T r a n s f e r m o r p in d e f in i t i o nU 1 9 L A N T r a n s f e r m o r p in d e f in i t i o nU 1 9 L A N T r a n s f e r m o r p in d e f in i t i o nU 1 9 L A N T r a n s f e r m o r p in d e f in i t i o n C o r r e c t U 1 9 L A N T r a n s f e r m o r p i n d eC o r r e c t U 1 9 L A N T r a n s f e r m o r p i n d eC o r r e c t U 1 9 L A N T r a n s f e r m o r p i n d eC o r r e c t U 1 9 L A N T r a n s f e r m o r p i n d e f in i t io nf in i t io nf in i t io nf in i t io n 0 . 20 . 20 . 20 . 2
1 61 61 61 6 0 . 20 . 20 . 20 . 22 1 ,2 1 ,2 1 ,2 1 , 2 42 42 42 4 S BS BS BS B S A T A S A T A S A T A S A T A 1 11 11 11 1 / 0 6/ 0 6/ 0 6/ 0 6 H WH WH WH W SSSS B S A T A P o r t 4 c h a n g e t o P o r t 3 f o r A T I O p e n I s s u eB S A T A P o r t 4 c h a n g e t o P o r t 3 f o r A T I O p e n I s s u eB S A T A P o r t 4 c h a n g e t o P o r t 3 f o r A T I O p e n I s s u eB S A T A P o r t 4 c h a n g e t o P o r t 3 f o r A T I O p e n I s s u e C h a n g e S B S A T A C h a n g e S B S A T A C h a n g e S B S A T A C h a n g e S B S A T A p o rt 4 t o p o r t 3p o rt 4 t o p o r t 3p o rt 4 t o p o r t 3p o rt 4 t o p o r t 3
1 71 71 71 7 3 63 63 63 6 D I M L E DD I M L E DD I M L E DD I M L E D 1 11 11 11 1 / 0 6/ 0 6/ 0 6/ 0 6 H WH WH WH W 0 . 20 . 20 . 20 . 2R eR eR eR e d u c e D I M L E D u n n e c e s s a r y d e s i g nd u c e D I M L E D u n n e c e s s a r y d e s i g nd u c e D I M L E D u n n e c e s s a r y d e s i g nd u c e D I M L E D u n n e c e s s a r y d e s i g n D e l R 1 0 2 6 a n d Q 1 6 7 , a d d N e t " D I M _ L E D # " f oD e l R 1 0 2 6 a n d Q 1 6 7 , a d d N e t " D I M _ L E D # " f oD e l R 1 0 2 6 a n d Q 1 6 7 , a d d N e t " D I M _ L E D # " f oD e l R 1 0 2 6 a n d Q 1 6 7 , a d d N e t " D I M _ L E D # " f o r c o n n ec t .r c o n n ec t .r c o n n ec t .r c o n n ec t .
C h a n g e l o c a t i o n f r o m P J P 6 0C h a n g e l o c a t i o n f r o m P J P 6 0C h a n g e l o c a t i o n f r o m P J P 6 0C h a n g e l o c a t i o n f r o m P J P 6 0 4 t o P J P 8 .4 t o P J P 8 .4 t o P J P 8 .4 t o P J P 8 .
1 81 81 81 8 2 72 72 72 7 C a rC a rC a rC a r d R ea d e rd R ea d e rd R ea d e rd R ea d e r 1 11 11 11 1 / 0 6/ 0 6/ 0 6/ 0 6 H WH WH WH W 0 . 20 . 20 . 20 . 2C h a n g e C a r d R e a d e r S o c k e t f o r M / E n e w p a r tC h a n g e C a r d R e a d e r S o c k e t f o r M / E n e w p a r tC h a n g e C a r d R e a d e r S o c k e t f o r M / E n e w p a r tC h a n g e C a r d R e a d e r S o c k e t f o r M / E n e w p a r t a n d a n d a n d a n d
C h i p f oC h i p f oC h i p f oC h i p f o r J M ic r o n n e w v e r s i o nr J M ic r o n n e w v e r s i o nr J M ic r o n n e w v e r s i o nr J M ic r o n n e w v e r s i o n
C h a n g e J R E A D t o T A I T W _ R 0 1 5 - B 1 0 - LC h a n g e J R E A D t o T A I T W _ R 0 1 5 - B 1 0 - LC h a n g e J R E A D t o T A I T W _ R 0 1 5 - B 1 0 - LC h a n g e J R E A D t o T A I T W _ R 0 1 5 - B 1 0 - L M .M .M .M .
R e s e r v e R 4 1 3 , C 9 0 2 c l o s e t o J R E A D . 2R e s e r v e R 4 1 3 , C 9 0 2 c l o s e t o J R E A D . 2R e s e r v e R 4 1 3 , C 9 0 2 c l o s e t o J R E A D . 2R e s e r v e R 4 1 3 , C 9 0 2 c l o s e t o J R E A D . 2 0 ; 0 ; 0 ; 0 ;
R 4 1 2 , C 9 0 1 c l o s e t o J R E A D . 2 6 ; R 4 1 1 , C 9 0 0 c l o s eR 4 1 2 , C 9 0 1 c l o s e t o J R E A D . 2 6 ; R 4 1 1 , C 9 0 0 c l o s eR 4 1 2 , C 9 0 1 c l o s e t o J R E A D . 2 6 ; R 4 1 1 , C 9 0 0 c l o s eR 4 1 2 , C 9 0 1 c l o s e t o J R E A D . 2 6 ; R 4 1 1 , C 9 0 0 c l o s e t o J R E A D .3 7 . t o J R E A D .3 7 . t o J R E A D .3 7 . t o J R E A D .3 7 .
CCCC h a n g e R 4 5 7 c l o s e t o U 2 3 . 4 2h a n g e R 4 5 7 c l o s e t o U 2 3 . 4 2h a n g e R 4 5 7 c l o s e t o U 2 3 . 4 2h a n g e R 4 5 7 c l o s e t o U 2 3 . 4 2
A d d A d d A d d A d d R 4 5 5 , R 4 5 6 c l o s e t o U 2 3 . 4 2R 4 5 5 , R 4 5 6 c l o s e t o U 2 3 . 4 2R 4 5 5 , R 4 5 6 c l o s e t o U 2 3 . 4 2R 4 5 5 , R 4 5 6 c l o s e t o U 2 3 . 4 2
D e l QD e l QD e l QD e l Q 1 6 9 , R 1 0 5 1 .1 6 9 , R 1 0 5 1 .1 6 9 , R 1 0 5 1 .1 6 9 , R 1 0 5 1 .
C h a n g e n e t C R _ L E D # b e c o m e C R _ L E D c o n n e c t UC h a n g e n e t C R _ L E D # b e c o m e C R _ L E D c o n n e c t UC h a n g e n e t C R _ L E D # b e c o m e C R _ L E D c o n n e c t UC h a n g e n e t C R _ L E D # b e c o m e C R _ L E D c o n n e c t U 2 3 .2 1 a n d Q 5 3 .22 3 .2 1 a n d Q 5 3 .22 3 .2 1 a n d Q 5 3 .22 3 .2 1 a n d Q 5 3 .2
A d d R 4 5 4 p u l l d o w n t o A d d R 4 5 4 p u l l d o w n t o A d d R 4 5 4 p u l l d o w n t o A d d R 4 5 4 p u l l d o w n t o G N DG N DG N DG N D
C h a n g e R 4 0 5 , R 1 2 2 f r o m 2 0 0 K t o 1 0 K p u l l - hC h a n g e R 4 0 5 , R 1 2 2 f r o m 2 0 0 K t o 1 0 K p u l l - hC h a n g e R 4 0 5 , R 1 2 2 f r o m 2 0 0 K t o 1 0 K p u l l - hC h a n g e R 4 0 5 , R 1 2 2 f r o m 2 0 0 K t o 1 0 K p u l l - h ig hig hig hig h
R e m o vR e m o vR e m o vR e m o v e C 8 9 5 , U 2 2e C 8 9 5 , U 2 2e C 8 9 5 , U 2 2e C 8 9 5 , U 2 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 1.C
HW Changed-List History-2
Custom
47 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
V ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it
I t e mI t e mI t e mI t e m I s s u e DI s s u e DI s s u e DI s s u e D e s c r ip t i o ne s c r ip t i o ne s c r ip t i o ne s c r ip t i o nD a t eD a t eD a t eD a t eR e qR e qR e qR e q u e s tu e s tu e s tu e s t
O w nO w nO w nO w n e re re re r S oS oS oS o lu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io n R e v .R e v .R e v .R e v .P aP aP aP a g e #g e #g e #g e # TTTT it l ei t l ei t l ei t l e
1 91 91 91 9 1 61 61 61 6 CCCC R TR TR TR T 1 11 11 11 1 / 0 7/ 0 7/ 0 7/ 0 7 H WH WH WH W N o r m a l iN o r m a l iN o r m a l iN o r m a l i z e C R T d e s i g n f o r c o m m o nz e C R T d e s i g n f o r c o m m o nz e C R T d e s i g n f o r c o m m o nz e C R T d e s i g n f o r c o m m o n C h a nC h a nC h a nC h a n g e L 8 3 , L 8 4 (1 0 _ 0 4 0 2 ) b e c o m e R 2 4 1 , R 2 4 0 (0 _ 0 6 0 3 )g e L 8 3 , L 8 4 (1 0 _ 0 4 0 2 ) b e c o m e R 2 4 1 , R 2 4 0 (0 _ 0 6 0 3 )g e L 8 3 , L 8 4 (1 0 _ 0 4 0 2 ) b e c o m e R 2 4 1 , R 2 4 0 (0 _ 0 6 0 3 )g e L 8 3 , L 8 4 (1 0 _ 0 4 0 2 ) b e c o m e R 2 4 1 , R 2 4 0 (0 _ 0 6 0 3 ) 0 . 20 . 20 . 20 . 2
1 71 71 71 72 02 02 02 0 L C DL C DL C DL C D 1 11 11 11 1 / 0 7/ 0 7/ 0 7/ 0 7 H WH WH WH W N o r m a l i z eN o r m a l i z eN o r m a l i z eN o r m a l i z e L C D d e s i g n f o r c o m m o n L C D d e s i g n f o r c o m m o n L C D d e s i g n f o r c o m m o n L C D d e s i g n f o r c o m m o n C h a n g e RC h a n g e RC h a n g e RC h a n g e R 4 9 1 f r o m 2 0 0 _ 0 4 0 2 t o 2 0 0 _ 0 8 0 54 9 1 f r o m 2 0 0 _ 0 4 0 2 t o 2 0 0 _ 0 8 0 54 9 1 f r o m 2 0 0 _ 0 4 0 2 t o 2 0 0 _ 0 8 0 54 9 1 f r o m 2 0 0 _ 0 4 0 2 t o 2 0 0 _ 0 8 0 5 0 . 20 . 20 . 20 . 2
2 12 12 12 1 1 81 81 81 8 L C DL C DL C DL C D 1 11 11 11 1 / 0 7/ 0 7/ 0 7/ 0 7 CCCC I CI CI CI C C I C f e e d b a c k R M A c o n c e r n f o rC I C f e e d b a c k R M A c o n c e r n f o rC I C f e e d b a c k R M A c o n c e r n f o rC I C f e e d b a c k R M A c o n c e r n f o r c o m m o n c o m m o n c o m m o n c o m m o n C h a n g e Q 4 3 f r o m A O S 3 4 1 3 t o S I 2 3C h a n g e Q 4 3 f r o m A O S 3 4 1 3 t o S I 2 3C h a n g e Q 4 3 f r o m A O S 3 4 1 3 t o S I 2 3C h a n g e Q 4 3 f r o m A O S 3 4 1 3 t o S I 2 3 0 10 10 10 1 0 . 20 . 20 . 20 . 2
2 22 22 22 2 3 33 33 33 3 K B CK B CK B CK B C 1 11 11 11 1 / 0 7/ 0 7/ 0 7/ 0 7 H WH WH WH W N o r m a l i z e KN o r m a l i z e KN o r m a l i z e KN o r m a l i z e K B 9 2 6 C r y s t a l p a r t f o r c o m m o nB 9 2 6 C r y s t a l p a r t f o r c o m m o nB 9 2 6 C r y s t a l p a r t f o r c o m m o nB 9 2 6 C r y s t a l p a r t f o r c o m m o n C h a n g e Y 7 f r o m 9 H 0 3 2 0 0 4 1 3 s m a l l t o 1 T J S 1 2 5 D J 4 A 4C h a n g e Y 7 f r o m 9 H 0 3 2 0 0 4 1 3 s m a l l t o 1 T J S 1 2 5 D J 4 A 4C h a n g e Y 7 f r o m 9 H 0 3 2 0 0 4 1 3 s m a l l t o 1 T J S 1 2 5 D J 4 A 4C h a n g e Y 7 f r o m 9 H 0 3 2 0 0 4 1 3 s m a l l t o 1 T J S 1 2 5 D J 4 A 4 2 0 P n o rm a l .2 0 P n o rm a l .2 0 P n o rm a l .2 0 P n o rm a l . 0 . 20 . 20 . 20 . 2
1 71 71 71 72 32 32 32 3 W e b CW e b CW e b CW e b C a ma ma ma m 1 11 11 11 1 / 0 9/ 0 9/ 0 9/ 0 9 H WH WH WH W C h a nC h a nC h a nC h a n g e U 5 4 W e b C a m p o w e r d e s i g n a n d r e l a t e dg e U 5 4 W e b C a m p o w e r d e s i g n a n d r e l a t e dg e U 5 4 W e b C a m p o w e r d e s i g n a n d r e l a t e dg e U 5 4 W e b C a m p o w e r d e s i g n a n d r e l a t e d C h a nC h a nC h a nC h a n g e U 5 4 f r o m G 9 1 6 - 3 9 0 T 1 U F t o R T 9 1 9 3 - 3 9 G B .g e U 5 4 f r o m G 9 1 6 - 3 9 0 T 1 U F t o R T 9 1 9 3 - 3 9 G B .g e U 5 4 f r o m G 9 1 6 - 3 9 0 T 1 U F t o R T 9 1 9 3 - 3 9 G B .g e U 5 4 f r o m G 9 1 6 - 3 9 0 T 1 U F t o R T 9 1 9 3 - 3 9 G B .
R e m oR e m oR e m oR e m o v e R 8 9 1 , R 8 9 2 i f n o u s e G 9 1 6 - 3 9 0 T 1 U F .v e R 8 9 1 , R 8 9 2 i f n o u s e G 9 1 6 - 3 9 0 T 1 U F .v e R 8 9 1 , R 8 9 2 i f n o u s e G 9 1 6 - 3 9 0 T 1 U F .v e R 8 9 1 , R 8 9 2 i f n o u s e G 9 1 6 - 3 9 0 T 1 U F .
A d d C 7 1 8 c l o s e t o U 5 4 . 4 f o r R T 9 1 9 3 - 3 9 G B .A d d C 7 1 8 c l o s e t o U 5 4 . 4 f o r R T 9 1 9 3 - 3 9 G B .A d d C 7 1 8 c l o s e t o U 5 4 . 4 f o r R T 9 1 9 3 - 3 9 G B .A d d C 7 1 8 c l o s e t o U 5 4 . 4 f o r R T 9 1 9 3 - 3 9 G B .
R e m o v e R 1 0 2 7 ~ R 1 0 3 0 f o r J P 7 n o i n sR e m o v e R 1 0 2 7 ~ R 1 0 3 0 f o r J P 7 n o i n sR e m o v e R 1 0 2 7 ~ R 1 0 3 0 f o r J P 7 n o i n sR e m o v e R 1 0 2 7 ~ R 1 0 3 0 f o r J P 7 n o i n s t a l l .t a l l .t a l l .t a l l .
C h a n g e J P 7 f r o m 8 p i nC h a n g e J P 7 f r o m 8 p i nC h a n g e J P 7 f r o m 8 p i nC h a n g e J P 7 f r o m 8 p i n t o 6 p in t o 6 p in t o 6 p in t o 6 p in
0 . 20 . 20 . 20 . 2
1 81 81 81 82 42 42 42 4 H WH WH WH W1 11 11 11 1 / 0 9/ 0 9/ 0 9/ 0 9HHHH D M ID M ID M ID M I 0 . 20 . 20 . 20 . 2R e m o vR e m o vR e m o vR e m o v e R 4 9 0 (1 0 0 K _ 0 4 0 2 )e R 4 9 0 (1 0 0 K _ 0 4 0 2 )e R 4 9 0 (1 0 0 K _ 0 4 0 2 )e R 4 9 0 (1 0 0 K _ 0 4 0 2 )R e d u c e H D M I D e s ig nR e d u c e H D M I D e s ig nR e d u c e H D M I D e s ig nR e d u c e H D M I D e s ig n
2 52 52 52 5 1 9 ,1 9 ,1 9 ,1 9 , 3 23 23 23 2 S B -C L K -D e b u gS B -C L K -D e b u gS B -C L K -D e b u gS B -C L K -D e b u g 1 11 11 11 1 / 0 9/ 0 9/ 0 9/ 0 9 H WH WH WH W D e b u gD e b u gD e b u gD e b u g C a r d n o f u n c t i o n i s s u e C a r d n o f u n c t i o n i s s u e C a r d n o f u n c t i o n i s s u e C a r d n o f u n c t i o n i s s u e D e l RD e l RD e l RD e l R 1 0 3 1 ,a d d R 3 0 3 c l o s e t o R 3 0 1 a n d U 1 5 .P 21 0 3 1 ,a d d R 3 0 3 c l o s e t o R 3 0 1 a n d U 1 5 .P 21 0 3 1 ,a d d R 3 0 3 c l o s e t o R 3 0 1 a n d U 1 5 .P 21 0 3 1 ,a d d R 3 0 3 c l o s e t o R 3 0 1 a n d U 1 5 .P 2
C o n n e c t f oC o n n e c t f oC o n n e c t f oC o n n e c t f o r C L K _ P C I _ S I O 2 t o J P 4 1 .1 5r C L K _ P C I _ S I O 2 t o J P 4 1 .1 5r C L K _ P C I _ S I O 2 t o J P 4 1 .1 5r C L K _ P C I _ S I O 2 t o J P 4 1 .1 5
0 . 20 . 20 . 20 . 2
2 62 62 62 6 2 52 52 52 5 LLLL A NA NA NA N 1 11 11 11 1 / 0 9/ 0 9/ 0 9/ 0 9 H WH WH WH W R J 4R J 4R J 4R J 4 5 L E D P o w e r c o r r e c t b a c k5 L E D P o w e r c o r r e c t b a c k5 L E D P o w e r c o r r e c t b a c k5 L E D P o w e r c o r r e c t b a c k C h a n g e J R J 4 5 . 1 3 , J R J 4 5 . 1 1 f r o m + 3 V _ L A NC h a n g e J R J 4 5 . 1 3 , J R J 4 5 . 1 1 f r o m + 3 V _ L A NC h a n g e J R J 4 5 . 1 3 , J R J 4 5 . 1 1 f r o m + 3 V _ L A NC h a n g e J R J 4 5 . 1 3 , J R J 4 5 . 1 1 f r o m + 3 V _ L A N _ L E D t o + 3 V _ L A N_ L E D t o + 3 V _ L A N_ L E D t o + 3 V _ L A N_ L E D t o + 3 V _ L A N 0 . 20 . 20 . 20 . 2
2 72 72 72 7 1 81 81 81 8 HHHH D M ID M ID M ID M I 1 11 11 11 1 / 0 9/ 0 9/ 0 9/ 0 9 H WH WH WH W R e d u c e H D M I D e s ig nR e d u c e H D M I D e s ig nR e d u c e H D M I D e s ig nR e d u c e H D M I D e s ig n R e m o vR e m o vR e m o vR e m o v e R 4 9 0 (1 0 0 K _ 0 4 0 2 )e R 4 9 0 (1 0 0 K _ 0 4 0 2 )e R 4 9 0 (1 0 0 K _ 0 4 0 2 )e R 4 9 0 (1 0 0 K _ 0 4 0 2 ) 0 . 20 . 20 . 20 . 2
2 82 82 82 8 6666 C P UC P UC P UC P U 1 11 11 11 1 / 0 9/ 0 9/ 0 9/ 0 9 H WH WH WH W AAAA d d H _ T H E R M T R I P # o n e m o r e w a yd d H _ T H E R M T R I P # o n e m o r e w a yd d H _ T H E R M T R I P # o n e m o r e w a yd d H _ T H E R M T R I P # o n e m o r e w a y A d d R 1 6A d d R 1 6A d d R 1 6A d d R 1 6 c lo s e t o Q 3 .1 f o r H _ T H E R M T R I P # c lo s e t o Q 3 .1 f o r H _ T H E R M T R I P # c lo s e t o Q 3 .1 f o r H _ T H E R M T R I P # c lo s e t o Q 3 .1 f o r H _ T H E R M T R I P # 0 . 20 . 20 . 20 . 2
2 92 92 92 9 3 33 33 33 3 K B CK B CK B CK B C 1 11 11 11 1 / 0 9/ 0 9/ 0 9/ 0 9 H WH WH WH W U p d a t e K BU p d a t e K BU p d a t e K BU p d a t e K B C P in D e f in i t i o n f o r c o m m o nC P in D e f in i t i o n f o r c o m m o nC P in D e f in i t i o n f o r c o m m o nC P in D e f in i t i o n f o r c o m m o n A d d H _ T H E RA d d H _ T H E RA d d H _ T H E RA d d H _ T H E R M T R I P # t o U 3 3 .2 5M T R I P # t o U 3 3 .2 5M T R I P # t o U 3 3 .2 5M T R I P # t o U 3 3 .2 5 0 . 20 . 20 . 20 . 2
3 03 03 03 0 3 53 53 53 5 H o le sH o le sH o le sH o le s 1 11 11 11 1 / 0 9/ 0 9/ 0 9/ 0 9 M EM EM EM E U p d a t e fU p d a t e fU p d a t e fU p d a t e f o r M / E D r a w in go r M / E D r a w in go r M / E D r a w in go r M / E D r a w in g D e l H 4 9 H 5 0 H 3 8 H 4 5 f o r M / E d r a w inD e l H 4 9 H 5 0 H 3 8 H 4 5 f o r M / E d r a w inD e l H 4 9 H 5 0 H 3 8 H 4 5 f o r M / E d r a w inD e l H 4 9 H 5 0 H 3 8 H 4 5 f o r M / E d r a w in g ch a n g eg ch a n g eg ch a n g eg ch a n g e 0 . 20 . 20 . 20 . 2
H WH WH WH W1 11 11 11 1 / 0 9/ 0 9/ 0 9/ 0 9M in iM in iM in iM in i -C a r d-C a r d-C a r d-C a r d2 62 62 62 63 13 13 13 1 0 . 20 . 20 . 20 . 2R e p l a c e D 1 7 a nR e p l a c e D 1 7 a nR e p l a c e D 1 7 a nR e p l a c e D 1 7 a n d D 4 7 b e c o m e R 5 2 a n d R 5 3d D 4 7 b e c o m e R 5 2 a n d R 5 3d D 4 7 b e c o m e R 5 2 a n d R 5 3d D 4 7 b e c o m e R 5 2 a n d R 5 3
D e l R 4 0 0 a n d R 4 6D e l R 4 0 0 a n d R 4 6D e l R 4 0 0 a n d R 4 6D e l R 4 0 0 a n d R 4 6 , C h a n g e J P 6 p in d e f in i t i o n f o r c o m m o n, C h a n g e J P 6 p in d e f in i t i o n f o r c o m m o n, C h a n g e J P 6 p in d e f in i t i o n f o r c o m m o n, C h a n g e J P 6 p in d e f in i t i o n f o r c o m m o n
R e d u c e M in i -C a r d d e s i g n , c h a n g e S I M C a r d d eR e d u c e M in i -C a r d d e s i g n , c h a n g e S I M C a r d d eR e d u c e M in i -C a r d d e s i g n , c h a n g e S I M C a r d d eR e d u c e M in i -C a r d d e s i g n , c h a n g e S I M C a r d d e s ig ns ig ns ig ns ig n
3 23 23 23 2 3 33 33 33 3 K B CK B CK B CK B C 1 11 11 11 1 / 0 9/ 0 9/ 0 9/ 0 9 H WH WH WH W R e s e r vR e s e r vR e s e r vR e s e r v e 0 _ 0 6 0 3 f o r K B B a c k L ig h te 0 _ 0 6 0 3 f o r K B B a c k L ig h te 0 _ 0 6 0 3 f o r K B B a c k L ig h te 0 _ 0 6 0 3 f o r K B B a c k L ig h t A d d R 5 1 6 ( 0 _ 0A d d R 5 1 6 ( 0 _ 0A d d R 5 1 6 ( 0 _ 0A d d R 5 1 6 ( 0 _ 0 6 0 3 ) b e t w e e n J P 4 8 .1 / 4 a n d + 5 V S _ L E D6 0 3 ) b e t w e e n J P 4 8 .1 / 4 a n d + 5 V S _ L E D6 0 3 ) b e t w e e n J P 4 8 .1 / 4 a n d + 5 V S _ L E D6 0 3 ) b e t w e e n J P 4 8 .1 / 4 a n d + 5 V S _ L E D 0 . 20 . 20 . 20 . 2
3 33 33 33 3 2 72 72 72 7 C a rC a rC a rC a r d R ea d e rd R ea d e rd R ea d e rd R ea d e r 1 11 11 11 1 / 1 0/ 1 0/ 1 0/ 1 0 H WH WH WH W C o r r e c t C a r d R e a d e r LC o r r e c t C a r d R e a d e r LC o r r e c t C a r d R e a d e r LC o r r e c t C a r d R e a d e r L E D p a rtE D p a rtE D p a rtE D p a rt C h a n g e D 5 f r o m S C 5 0 0 0 0 4 E 0 0 (A Q U A _C h a n g e D 5 f r o m S C 5 0 0 0 0 4 E 0 0 (A Q U A _C h a n g e D 5 f r o m S C 5 0 0 0 0 4 E 0 0 (A Q U A _C h a n g e D 5 f r o m S C 5 0 0 0 0 4 E 0 0 (A Q U A _ W H I T E ) t oW H I T E ) t oW H I T E ) t oW H I T E ) t o
S C 5 0 0 0 0 4 WS C 5 0 0 0 0 4 WS C 5 0 0 0 0 4 WS C 5 0 0 0 0 4 W 0 0 (W H I T E )0 0 (W H I T E )0 0 (W H I T E )0 0 (W H I T E )0 . 20 . 20 . 20 . 2
3 43 43 43 4 3 43 43 43 4 L E D L E D L E D L E D F u n c t io nF u n c t io nF u n c t io nF u n c t io n 1 11 11 11 1 / 1 0/ 1 0/ 1 0/ 1 0 H WH WH WH W C o r r e cC o r r e cC o r r e cC o r r e c t L E D f u n c t i o n f o r c o m m o nt L E D f u n c t i o n f o r c o m m o nt L E D f u n c t i o n f o r c o m m o nt L E D f u n c t i o n f o r c o m m o n C h a n g e L E D f r o m D 5 0 , D 3 0 , D 2 7 S C 5C h a n g e L E D f r o m D 5 0 , D 3 0 , D 2 7 S C 5C h a n g e L E D f r o m D 5 0 , D 3 0 , D 2 7 S C 5C h a n g e L E D f r o m D 5 0 , D 3 0 , D 2 7 S C 5 0 0 0 0 4 E 0 00 0 0 0 4 E 0 00 0 0 0 4 E 0 00 0 0 0 4 E 0 0
(A Q U A _ W H I T E ) t o D 6 , D 7 , D 8 S C 5 0 0 0 0 4 W 0 0 (W H I T E )(A Q U A _ W H I T E ) t o D 6 , D 7 , D 8 S C 5 0 0 0 0 4 W 0 0 (W H I T E )(A Q U A _ W H I T E ) t o D 6 , D 7 , D 8 S C 5 0 0 0 0 4 W 0 0 (W H I T E )(A Q U A _ W H I T E ) t o D 6 , D 7 , D 8 S C 5 0 0 0 0 4 W 0 0 (W H I T E )
C h a n g e L E D f r o m D 4 5 , D 4 6 S C 5 0 0 0C h a n g e L E D f r o m D 4 5 , D 4 6 S C 5 0 0 0C h a n g e L E D f r o m D 4 5 , D 4 6 S C 5 0 0 0C h a n g e L E D f r o m D 4 5 , D 4 6 S C 5 0 0 0 0 4 B 0 00 4 B 0 00 4 B 0 00 4 B 0 0
(A Q U A _ W H I T E / A M B E R ) t o D 1 7 , D 1 8 S C 5 0 0 0 0 5 M 0 0(A Q U A _ W H I T E / A M B E R ) t o D 1 7 , D 1 8 S C 5 0 0 0 0 5 M 0 0(A Q U A _ W H I T E / A M B E R ) t o D 1 7 , D 1 8 S C 5 0 0 0 0 5 M 0 0(A Q U A _ W H I T E / A M B E R ) t o D 1 7 , D 1 8 S C 5 0 0 0 0 5 M 0 0
(Y E L L O W / W H I T E ) ; A d d Q 7 , R 2 0 a n d R 4 2 c l o s e t o D 1 8(Y E L L O W / W H I T E ) ; A d d Q 7 , R 2 0 a n d R 4 2 c l o s e t o D 1 8(Y E L L O W / W H I T E ) ; A d d Q 7 , R 2 0 a n d R 4 2 c l o s e t o D 1 8(Y E L L O W / W H I T E ) ; A d d Q 7 , R 2 0 a n d R 4 2 c l o s e t o D 1 8
0 . 20 . 20 . 20 . 2
3 53 53 53 5 2 12 12 12 1 SSSS B -G P I OB -G P I OB -G P I OB -G P I O 1 11 11 11 1 / 1 0/ 1 0/ 1 0/ 1 0 H WH WH WH W A d d o n e mA d d o n e mA d d o n e mA d d o n e m o r e w a y f o r G S E N S O R L E D # in f o r m p ino r e w a y f o r G S E N S O R L E D # in f o r m p ino r e w a y f o r G S E N S O R L E D # in f o r m p ino r e w a y f o r G S E N S O R L E D # in f o r m p in A d d H D D _ H A L TA d d H D D _ H A L TA d d H D D _ H A L TA d d H D D _ H A L T L E D # c o n n e c t f r o m U 1 5 .P 8L E D # c o n n e c t f r o m U 1 5 .P 8L E D # c o n n e c t f r o m U 1 5 .P 8L E D # c o n n e c t f r o m U 1 5 .P 8 0 . 20 . 20 . 20 . 2
3 63 63 63 6 3 33 33 33 3 K B C -K B C -K B C -K B C - G P I OG P I OG P I OG P I O 1 11 11 11 1 / 1 1/ 1 1/ 1 1/ 1 1 H WH WH WH W A d d C I R _ I N P H t o + 5A d d C I R _ I N P H t o + 5A d d C I R _ I N P H t o + 5A d d C I R _ I N P H t o + 5 V LV LV LV L
AAAA d d E S B _ C L K / D A T P H t o + 3 V Ld d E S B _ C L K / D A T P H t o + 3 V Ld d E S B _ C L K / D A T P H t o + 3 V Ld d E S B _ C L K / D A T P H t o + 3 V L
A d d R 4 6 1 0 K _ 0 4 0 2 P H t o + 5 V L c l o s e t o U 3 3A d d R 4 6 1 0 K _ 0 4 0 2 P H t o + 5 V L c l o s e t o U 3 3A d d R 4 6 1 0 K _ 0 4 0 2 P H t o + 5 V L c l o s e t o U 3 3A d d R 4 6 1 0 K _ 0 4 0 2 P H t o + 5 V L c l o s e t o U 3 3
A d d R 5 1 4 ,R 5 1 5 1 0 K _ 0 4 0 2 P H t o + 3 V L c l o s e t o UA d d R 5 1 4 ,R 5 1 5 1 0 K _ 0 4 0 2 P H t o + 3 V L c l o s e t o UA d d R 5 1 4 ,R 5 1 5 1 0 K _ 0 4 0 2 P H t o + 3 V L c l o s e t o UA d d R 5 1 4 ,R 5 1 5 1 0 K _ 0 4 0 2 P H t o + 3 V L c l o s e t o U 3 33 33 33 3
0 . 20 . 20 . 20 . 2
CCCC P U ,F P RP U ,F P RP U ,F P RP U ,F P R
3 93 93 93 9 1 71 71 71 7 W e b CW e b CW e b CW e b C a ma ma ma m 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W U p d a t e t h e W e b C a m + D ig i t a l M ic r e s e r v e r U p d a t e t h e W e b C a m + D ig i t a l M ic r e s e r v e r U p d a t e t h e W e b C a m + D ig i t a l M ic r e s e r v e r U p d a t e t h e W e b C a m + D ig i t a l M ic r e s e r v e r c o n n .c o n n .c o n n .c o n n . C h a n g e C h a n g e C h a n g e C h a n g e J P 7 f r o m S P 0 2 0 0 0 H C 0 0 (8 p i n ) - - > S P 0 2 0 0 0 I L 0 0 (6 p in )J P 7 f r o m S P 0 2 0 0 0 H C 0 0 (8 p i n ) - - > S P 0 2 0 0 0 I L 0 0 (6 p i n )J P 7 f r o m S P 0 2 0 0 0 H C 0 0 (8 p i n ) - - > S P 0 2 0 0 0 I L 0 0 (6 p i n )J P 7 f r o m S P 0 2 0 0 0 H C 0 0 (8 p i n ) - - > S P 0 2 0 0 0 I L 0 0 (6 p i n ) 0 . 20 . 20 . 20 . 2
3 73 73 73 7 6 ,6 ,6 ,6 , 3 13 13 13 1 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W R e d u c e S 3 R e d u c e S 3 R e d u c e S 3 R e d u c e S 3 p o w e r c o n s u m p t io np o w e r c o n s u m p t io np o w e r c o n s u m p t io np o w e r c o n s u m p t io n C h a n g e R 1 5 . 2 , R 2 1 . 2 , R 3 6 . 2 , R 3 0 . 2 c o nC h a n g e R 1 5 . 2 , R 2 1 . 2 , R 3 6 . 2 , R 3 0 . 2 c o nC h a n g e R 1 5 . 2 , R 2 1 . 2 , R 3 6 . 2 , R 3 0 . 2 c o nC h a n g e R 1 5 . 2 , R 2 1 . 2 , R 3 6 . 2 , R 3 0 . 2 c o n n ec t io n f ro mn ec t io n f ro mn ec t io n f ro mn ec t io n f ro m
+ 1 . 8 V t o + 1 . 8 V S ; R e m o v e R 6 2 2 , i n s+ 1 . 8 V t o + 1 . 8 V S ; R e m o v e R 6 2 2 , i n s+ 1 . 8 V t o + 1 . 8 V S ; R e m o v e R 6 2 2 , i n s+ 1 . 8 V t o + 1 . 8 V S ; R e m o v e R 6 2 2 , i n s t a l l R 5 8 1t a l l R 5 8 1t a l l R 5 8 1t a l l R 5 8 10 . 20 . 20 . 20 . 2
N BN BN BN B3 83 83 83 8 1 11 11 11 1 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W R e d u c eR e d u c eR e d u c eR e d u c e t h e l e v e l s h i f t d e s i g n f o r C h ip A 1 2 . t h e l e v e l s h i f t d e s i g n f o r C h ip A 1 2 . t h e l e v e l s h i f t d e s i g n f o r C h ip A 1 2 . t h e l e v e l s h i f t d e s i g n f o r C h ip A 1 2 . D e l Q 6 , R 8 7 ; QD e l Q 6 , R 8 7 ; QD e l Q 6 , R 8 7 ; QD e l Q 6 , R 8 7 ; Q 5 ,R 8 4 a n d r e p la c e b y 0 o h m (a d d R 6 7 ,R 6 8 )5 ,R 8 4 a n d r e p la c e b y 0 o h m (a d d R 6 7 ,R 6 8 )5 ,R 8 4 a n d r e p la c e b y 0 o h m (a d d R 6 7 ,R 6 8 )5 ,R 8 4 a n d r e p la c e b y 0 o h m (a d d R 6 7 ,R 6 8 )
c o n n e c t c o n n e c t c o n n e c t c o n n e c t d i r e c t l y . I n s t a l l R 3 7 1 (1 0 K o h m )d i r e c t l y . I n s t a l l R 3 7 1 (1 0 K o h m )d i r e c t l y . I n s t a l l R 3 7 1 (1 0 K o h m )d i r e c t l y . I n s t a l l R 3 7 1 (1 0 K o h m )
0 . 20 . 20 . 20 . 2
4 04 04 04 0 6 ,6 ,6 ,6 , 3 33 33 33 3 C P U ,C P U ,C P U ,C P U , K B CK B CK B CK B C 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W UUUU p d a t e T H E R M T R I P # d e s i g n t o E Cp d a t e T H E R M T R I P # d e s i g n t o E Cp d a t e T H E R M T R I P # d e s i g n t o E Cp d a t e T H E R M T R I P # d e s i g n t o E C C h a n g e R 1 6 . 2 c o n n e cC h a n g e R 1 6 . 2 c o n n e cC h a n g e R 1 6 . 2 c o n n e cC h a n g e R 1 6 . 2 c o n n e c t i o n f r o m T H E R M T R I P # t ot i o n f r o m T H E R M T R I P # t ot i o n f r o m T H E R M T R I P # t ot i o n f r o m T H E R M T R I P # t o
T H E R M T R I P # _ E C f o rT H E R M T R I P # _ E C f o rT H E R M T R I P # _ E C f o rT H E R M T R I P # _ E C f o r s e p a r a t e s e p a r a t e s e p a r a t e s e p a r a t e
0 . 20 . 20 . 20 . 2
4 14 14 14 1 1 81 81 81 8 HHHH D M ID M ID M ID M I 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W R eR eR eR e m o v e E M I s o lu t i o n b e c o m e r e s e r v e f o r v e r i f ym o v e E M I s o lu t i o n b e c o m e r e s e r v e f o r v e r i f ym o v e E M I s o lu t i o n b e c o m e r e s e r v e f o r v e r i f ym o v e E M I s o lu t i o n b e c o m e r e s e r v e f o r v e r i f y A d d RA d d RA d d RA d d R 1 1 2 , R 1 1 3 , R 1 1 5 ~ R 1 2 0 c l o s e t o e a c h L 8 5 ~ L 8 8 f o r c o - l a y1 1 2 , R 1 1 3 , R 1 1 5 ~ R 1 2 0 c l o s e t o e a c h L 8 5 ~ L 8 8 f o r c o - l a y1 1 2 , R 1 1 3 , R 1 1 5 ~ R 1 2 0 c l o s e t o e a c h L 8 5 ~ L 8 8 f o r c o - l a y1 1 2 , R 1 1 3 , R 1 1 5 ~ R 1 2 0 c l o s e t o e a c h L 8 5 ~ L 8 8 f o r c o - l a y 0 . 20 . 20 . 20 . 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 1.C
HW Changed-List History-2
Custom
48 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
V ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it
I t e mI t e mI t e mI t e m I s s u e DI s s u e DI s s u e DI s s u e D e s c r ip t i o ne s c r ip t i o ne s c r ip t i o ne s c r ip t i o nD a t eD a t eD a t eD a t eR e qR e qR e qR e q u e s tu e s tu e s tu e s t
O w nO w nO w nO w n e re re re r S oS oS oS o lu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io n R e v .R e v .R e v .R e v .P aP aP aP a g e #g e #g e #g e # TTTT it l ei t l ei t l ei t l e
4 24 24 24 2 1 9 .1 9 .1 9 .1 9 . 3 23 23 23 2 S BS BS BS B ,B I O S,B I O S,B I O S,B I O S 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W R e dR e dR e dR e d u c e S B r e l a t e d d e s i g n f o r C h ip A 1 2 a n d o t h e r su c e S B r e l a t e d d e s i g n f o r C h ip A 1 2 a n d o t h e r su c e S B r e l a t e d d e s i g n f o r C h ip A 1 2 a n d o t h e r su c e S B r e l a t e d d e s i g n f o r C h ip A 1 2 a n d o t h e r s D eD eD eD e l Q 1 5 5 ,R 9 8 6 , a n d a d d R 3 1 1 c l o s e t o U 1 5 .l Q 1 5 5 ,R 9 8 6 , a n d a d d R 3 1 1 c l o s e t o U 1 5 .l Q 1 5 5 ,R 9 8 6 , a n d a d d R 3 1 1 c l o s e t o U 1 5 .l Q 1 5 5 ,R 9 8 6 , a n d a d d R 3 1 1 c l o s e t o U 1 5 .
D e l R 1 0 1 1 b e c o m e TD e l R 1 0 1 1 b e c o m e TD e l R 1 0 1 1 b e c o m e TD e l R 1 0 1 1 b e c o m e T 1 8 , C a n c e l R 1 0 1 2 a n d c o n n e c t t o H 3 11 8 , C a n c e l R 1 0 1 2 a n d c o n n e c t t o H 3 11 8 , C a n c e l R 1 0 1 2 a n d c o n n e c t t o H 3 11 8 , C a n c e l R 1 0 1 2 a n d c o n n e c t t o H 3 1
a n d J P 4 1 a n d J P 4 1 a n d J P 4 1 a n d J P 4 1 d i r e c t l yd i r e c t l yd i r e c t l yd i r e c t l y
0 . 20 . 20 . 20 . 2
4 34 34 34 3 2 1 ,2 1 ,2 1 ,2 1 , 3 23 23 23 2 S BS BS BS B ,B I O S,B I O S,B I O S,B I O S 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W B I O S D e b u g T o o l r e s e rB I O S D e b u g T o o l r e s e rB I O S D e b u g T o o l r e s e rB I O S D e b u g T o o l r e s e r v ev ev ev e 0 . 20 . 20 . 20 . 2A d d S B _ I N T _ F L A S H _ S EA d d S B _ I N T _ F L A S H _ S EA d d S B _ I N T _ F L A S H _ S EA d d S B _ I N T _ F L A S H _ S E L a n d r e l a t e dL a n d r e l a t e dL a n d r e l a t e dL a n d r e l a t e d
(J P 1 2 ,U 3 0 ,R 2 2 8 ,R 2 2 6 ,C 4 8 9 c l o s e t o U(J P 1 2 ,U 3 0 ,R 2 2 8 ,R 2 2 6 ,C 4 8 9 c l o s e t o U(J P 1 2 ,U 3 0 ,R 2 2 8 ,R 2 2 6 ,C 4 8 9 c l o s e t o U(J P 1 2 ,U 3 0 ,R 2 2 8 ,R 2 2 6 ,C 4 8 9 c l o s e t o U 2 9 )2 9 )2 9 )2 9 )4 44 44 44 4 2 52 52 52 5 LLLL A NA NA NA N 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W U p d a t eU p d a t eU p d a t eU p d a t e L A N C h ip S y m b o l l i n k t o C I S s e r v e r L A N C h ip S y m b o l l i n k t o C I S s e r v e r L A N C h ip S y m b o l l i n k t o C I S s e r v e r L A N C h ip S y m b o l l i n k t o C I S s e r v e r U p d a t e L A N U p d a t e L A N U p d a t e L A N U p d a t e L A N C h ip U 2 0 S y m b o l l i n k t o C I S s e r v e rC h ip U 2 0 S y m b o l l i n k t o C I S s e r v e rC h ip U 2 0 S y m b o l l i n k t o C I S s e r v e rC h ip U 2 0 S y m b o l l i n k t o C I S s e r v e r 0 . 20 . 20 . 20 . 2
4 54 54 54 5 1 31 31 31 3 N BN BN BN B 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W A d d 0 o h m _ 0 6 0 3 t oA d d 0 o h m _ 0 6 0 3 t oA d d 0 o h m _ 0 6 0 3 t oA d d 0 o h m _ 0 6 0 3 t o s e p a r a t e V D D 1 8 _ M E M s e p a r a t e V D D 1 8 _ M E M s e p a r a t e V D D 1 8 _ M E M s e p a r a t e V D D 1 8 _ M E M A d d R 1 0 5 1 ( 0 _ 0 6 0 3 ) bA d d R 1 0 5 1 ( 0 _ 0 6 0 3 ) bA d d R 1 0 5 1 ( 0 _ 0 6 0 3 ) bA d d R 1 0 5 1 ( 0 _ 0 6 0 3 ) b e t w e e n + 1 .8 V S & + 1 .8 V _ V D D _ S Pe t w e e n + 1 .8 V S & + 1 .8 V _ V D D _ S Pe t w e e n + 1 .8 V S & + 1 .8 V _ V D D _ S Pe t w e e n + 1 .8 V S & + 1 .8 V _ V D D _ S P 0 . 20 . 20 . 20 . 2
4 64 64 64 6 1 81 81 81 8 HHHH D M ID M ID M ID M I 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W R eR eR eR e d u c e H D M I r e la t e d d e s i g n f o r c o m m o nd u c e H D M I r e la t e d d e s i g n f o r c o m m o nd u c e H D M I r e la t e d d e s i g n f o r c o m m o nd u c e H D M I r e la t e d d e s i g n f o r c o m m o n D e lD e lD e lD e l R 4 9 0 (1 0 0 K _ 0 4 0 2 ) R 4 9 0 (1 0 0 K _ 0 4 0 2 ) R 4 9 0 (1 0 0 K _ 0 4 0 2 ) R 4 9 0 (1 0 0 K _ 0 4 0 2 ) 0 . 20 . 20 . 20 . 2
4 74 74 74 7 2 02 02 02 0 S BS BS BS B 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W R e d uR e d uR e d uR e d u c e S B r e l a t e d d e s i g n f o r c o m m o n a n d A 1 2 c h ipc e S B r e l a t e d d e s i g n f o r c o m m o n a n d A 1 2 c h ipc e S B r e l a t e d d e s i g n f o r c o m m o n a n d A 1 2 c h ipc e S B r e l a t e d d e s i g n f o r c o m m o n a n d A 1 2 c h ip R e m o v e R e m o v e R e m o v e R e m o v e R 9 9 4 (0 _ 0 4 0 2 )R 9 9 4 (0 _ 0 4 0 2 )R 9 9 4 (0 _ 0 4 0 2 )R 9 9 4 (0 _ 0 4 0 2 )
C h a n g e U 1C h a n g e U 1C h a n g e U 1C h a n g e U 1 5 .F 1 c o n n e c t i o n b e c o m e t e s t p o in t5 .F 1 c o n n e c t i o n b e c o m e t e s t p o in t5 .F 1 c o n n e c t i o n b e c o m e t e s t p o in t5 .F 1 c o n n e c t i o n b e c o m e t e s t p o in t
R e m o v e R 1 0 5 3 ,R e m o v e R 1 0 5 3 ,R e m o v e R 1 0 5 3 ,R e m o v e R 1 0 5 3 , c h a n g e R 1 0 5 2 b e c o m e 0 _ 0 4 0 2 c h a n g e R 1 0 5 2 b e c o m e 0 _ 0 4 0 2 c h a n g e R 1 0 5 2 b e c o m e 0 _ 0 4 0 2 c h a n g e R 1 0 5 2 b e c o m e 0 _ 0 4 0 2
0 . 20 . 20 . 20 . 2
4 84 84 84 8 2 0 , 2 1 ,2 0 , 2 1 ,2 0 , 2 1 ,2 0 , 2 1 ,
2 72 72 72 7S B ,CS B ,CS B ,CS B ,C a rd rea d e ra rd rea d e ra rd rea d e ra rd rea d e r 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W R e s e r v e C a r d r e a d e r D 3 E f u n c t i o n (C R _ W AR e s e r v e C a r d r e a d e r D 3 E f u n c t i o n (C R _ W AR e s e r v e C a r d r e a d e r D 3 E f u n c t i o n (C R _ W AR e s e r v e C a r d r e a d e r D 3 E f u n c t i o n (C R _ W A K E # &K E # &K E # &K E # &
C R _ CC R _ CC R _ CC R _ C P P E # )P P E # )P P E # )P P E # )
A d d RA d d RA d d RA d d R 8 1 c l o s e t o U 1 5 ; Q 5 4 , R 1 2 4 c l o s e t o U 2 3 f o r c o n n e c t U 1 5 . F 88 1 c l o s e t o U 1 5 ; Q 5 4 , R 1 2 4 c l o s e t o U 2 3 f o r c o n n e c t U 1 5 . F 88 1 c l o s e t o U 1 5 ; Q 5 4 , R 1 2 4 c l o s e t o U 2 3 f o r c o n n e c t U 1 5 . F 88 1 c l o s e t o U 1 5 ; Q 5 4 , R 1 2 4 c l o s e t o U 2 3 f o r c o n n e c t U 1 5 . F 8
t o U 2 3 . 1 3 ; A d d R 3 6 9 c l o s e t o U 2 3 f o r c o n n e c t U 1 5 . M 5 t o U 2 3 . t o U 2 3 . 1 3 ; A d d R 3 6 9 c l o s e t o U 2 3 f o r c o n n e c t U 1 5 . M 5 t o U 2 3 . t o U 2 3 . 1 3 ; A d d R 3 6 9 c l o s e t o U 2 3 f o r c o n n e c t U 1 5 . M 5 t o U 2 3 . t o U 2 3 . 1 3 ; A d d R 3 6 9 c l o s e t o U 2 3 f o r c o n n e c t U 1 5 . M 5 t o U 2 3 . 1 61 61 61 60 . 20 . 20 . 20 . 2
4 94 94 94 9 2 1 ,2 1 ,2 1 ,2 1 , 3 33 33 33 3 S B ,K B CS B ,K B CS B ,K B CS B ,K B C 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W RRRR e d u c e S B r e l a t e d d e s i g n f o r c o m m o ne d u c e S B r e l a t e d d e s i g n f o r c o m m o ne d u c e S B r e l a t e d d e s i g n f o r c o m m o ne d u c e S B r e l a t e d d e s i g n f o r c o m m o n D e l D 5 1 a n d R 1 0 3 4 , C h a n g e t h e n e t A C _ I ND e l D 5 1 a n d R 1 0 3 4 , C h a n g e t h e n e t A C _ I ND e l D 5 1 a n d R 1 0 3 4 , C h a n g e t h e n e t A C _ I ND e l D 5 1 a n d R 1 0 3 4 , C h a n g e t h e n e t A C _ I N b e co m e A C _ I N _ D b eco m e A C _ I N _ D b eco m e A C _ I N _ D b eco m e A C _ I N _ D 0 . 20 . 20 . 20 . 2
5 05 05 05 0 2 8 ,2 8 ,2 8 ,2 8 , 3 33 33 33 3 CCCC o d e c ,K B Co d e c ,K B Co d e c ,K B Co d e c ,K B C 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H P QH P QH P QH P Q E CE CE CE C _ B E E P f u n c t i o n f o r K B C a d d_ B E E P f u n c t i o n f o r K B C a d d_ B E E P f u n c t i o n f o r K B C a d d_ B E E P f u n c t i o n f o r K B C a d d A dA dA dA d d R 5 6 3 c l o s e t o C 9 5 5 ; A d d R 5 4 4 c l o s e t o U 3 3 . 3 1d R 5 6 3 c l o s e t o C 9 5 5 ; A d d R 5 4 4 c l o s e t o U 3 3 . 3 1d R 5 6 3 c l o s e t o C 9 5 5 ; A d d R 5 4 4 c l o s e t o U 3 3 . 3 1d R 5 6 3 c l o s e t o C 9 5 5 ; A d d R 5 4 4 c l o s e t o U 3 3 . 3 1 0 . 20 . 20 . 20 . 2
5 15 15 15 1 3 33 33 33 3 K B CK B CK B CK B C 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W R e d u c e R e d u c e R e d u c e R e d u c e S 5 P o w e r C o n s u m p t io nS 5 P o w e r C o n s u m p t io nS 5 P o w e r C o n s u m p t io nS 5 P o w e r C o n s u m p t io n C h a n g e R 1 0 4 0 . 1 c o n n e c t i o n f r o m + 3 V L _C h a n g e R 1 0 4 0 . 1 c o n n e c t i o n f r o m + 3 V L _C h a n g e R 1 0 4 0 . 1 c o n n e c t i o n f r o m + 3 V L _C h a n g e R 1 0 4 0 . 1 c o n n e c t i o n f r o m + 3 V L _ E C t o + 3 V A L WE C t o + 3 V A L WE C t o + 3 V A L WE C t o + 3 V A L W
D e l R 5 4 6 P H t o + 3 V L _ E C , D e l D 2 6 r e p l a c e b y a d d R 5 4 7 c l o sD e l R 5 4 6 P H t o + 3 V L _ E C , D e l D 2 6 r e p l a c e b y a d d R 5 4 7 c l o sD e l R 5 4 6 P H t o + 3 V L _ E C , D e l D 2 6 r e p l a c e b y a d d R 5 4 7 c l o sD e l R 5 4 6 P H t o + 3 V L _ E C , D e l D 2 6 r e p l a c e b y a d d R 5 4 7 c l o s e t oe t oe t oe t o
UUUU 3 3 f o r s h o r t3 3 f o r s h o r t3 3 f o r s h o r t3 3 f o r s h o r t
0 . 20 . 20 . 20 . 2
5 25 25 25 2 3 33 33 33 3 K B CK B CK B CK B C 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W R e d u c e K B C D e s i g n f o r c o m m o n a n d V e r :C 0R e d u c e K B C D e s i g n f o r c o m m o n a n d V e r :C 0R e d u c e K B C D e s i g n f o r c o m m o n a n d V e r :C 0R e d u c e K B C D e s i g n f o r c o m m o n a n d V e r :C 0 C h ip C h ip C h ip C h ip
C h a n g e f r o m S A 0 0 0 0 1 J 5 3 0 t o S AC h a n g e f r o m S A 0 0 0 0 1 J 5 3 0 t o S AC h a n g e f r o m S A 0 0 0 0 1 J 5 3 0 t o S AC h a n g e f r o m S A 0 0 0 0 1 J 5 3 0 t o S A 0 0 0 0 1 J 5 4 00 0 0 0 1 J 5 4 00 0 0 0 1 J 5 4 00 0 0 0 1 J 5 4 0
D e l R 5 3 7 b e c o m e T e s t P o i n t , c h a n g e R 5 1 6 b e c o m e 1 5 0 _ 0 6D e l R 5 3 7 b e c o m e T e s t P o i n t , c h a n g e R 5 1 6 b e c o m e 1 5 0 _ 0 6D e l R 5 3 7 b e c o m e T e s t P o i n t , c h a n g e R 5 1 6 b e c o m e 1 5 0 _ 0 6D e l R 5 3 7 b e c o m e T e s t P o i n t , c h a n g e R 5 1 6 b e c o m e 1 5 0 _ 0 6 0 30 30 30 3
R e m o v e R 1 0 4 4 , c h a n g e R 1 0 4 0 f r o m 1 0 K t o 1R e m o v e R 1 0 4 4 , c h a n g e R 1 0 4 0 f r o m 1 0 K t o 1R e m o v e R 1 0 4 4 , c h a n g e R 1 0 4 0 f r o m 1 0 K t o 1R e m o v e R 1 0 4 4 , c h a n g e R 1 0 4 0 f r o m 1 0 K t o 1 0 0 K0 0 K0 0 K0 0 K
C h a n g e R 5 2 8 . 2 , R 5 2 9 . 2 c o n n e c t i o n f r o m + 5C h a n g e R 5 2 8 . 2 , R 5 2 9 . 2 c o n n e c t i o n f r o m + 5C h a n g e R 5 2 8 . 2 , R 5 2 9 . 2 c o n n e c t i o n f r o m + 5C h a n g e R 5 2 8 . 2 , R 5 2 9 . 2 c o n n e c t i o n f r o m + 5 V A L W t o + 5 V LV A L W t o + 5 V LV A L W t o + 5 V LV A L W t o + 5 V L
I n s t a l l C 8 1 4 (4 . 7 U _ 0 8 0 5 )I n s t a l l C 8 1 4 (4 . 7 U _ 0 8 0 5 )I n s t a l l C 8 1 4 (4 . 7 U _ 0 8 0 5 )I n s t a l l C 8 1 4 (4 . 7 U _ 0 8 0 5 )
0 . 20 . 20 . 20 . 2
5 35 35 35 3 3 43 43 43 4 S w iS w iS w iS w i t c h D e s ig nt c h D e s ig nt c h D e s ig nt c h D e s ig n 1 11 11 11 1 / 1 3/ 1 3/ 1 3/ 1 3 H WH WH WH W U p d a t e C S D fU p d a t e C S D fU p d a t e C S D fU p d a t e C S D f u n c t i o n b o a r d d e s i g n f o r c o m m o nu n c t i o n b o a r d d e s i g n f o r c o m m o nu n c t i o n b o a r d d e s i g n f o r c o m m o nu n c t i o n b o a r d d e s i g n f o r c o m m o n C h a n g e J P 3 6 . 1 c o n n e c t i o n b e c o m e + 3 V L ; C h a n g e R 1C h a n g e J P 3 6 . 1 c o n n e c t i o n b e c o m e + 3 V L ; C h a n g e R 1C h a n g e J P 3 6 . 1 c o n n e c t i o n b e c o m e + 3 V L ; C h a n g e R 1C h a n g e J P 3 6 . 1 c o n n e c t i o n b e c o m e + 3 V L ; C h a n g e R 1 0 4 6 .1 0 4 6 .1 0 4 6 .1 0 4 6 .1
a n d R 1 0 4 7 . 1 c o n n e c t i o n b e c o m e S M B _a n d R 1 0 4 7 . 1 c o n n e c t i o n b e c o m e S M B _a n d R 1 0 4 7 . 1 c o n n e c t i o n b e c o m e S M B _a n d R 1 0 4 7 . 1 c o n n e c t i o n b e c o m e S M B _ E C _ C K 1 /D A 1E C _ C K 1 /D A 1E C _ C K 1 /D A 1E C _ C K 1 /D A 1
C h a n g e J P 3 6 . 7 c o n n e c t i o n f r o m G NC h a n g e J P 3 6 . 7 c o n n e c t i o n f r o m G NC h a n g e J P 3 6 . 7 c o n n e c t i o n f r o m G NC h a n g e J P 3 6 . 7 c o n n e c t i o n f r o m G N D t o + 5 V A L W _ L E D b y D t o + 5 V A L W _ L E D b y D t o + 5 V A L W _ L E D b y D t o + 5 V A L W _ L E D b y
0 . 20 . 20 . 20 . 2
5 45 45 45 4 3 43 43 43 4 LLLL E DE DE DE D 1 11 11 11 1 / 1 4/ 1 4/ 1 4/ 1 4 H WH WH WH W C o r r e c t T / P O n / O f f L E D d e s i g n d e fC o r r e c t T / P O n / O f f L E D d e s i g n d e fC o r r e c t T / P O n / O f f L E D d e s i g n d e fC o r r e c t T / P O n / O f f L E D d e s i g n d e f in ein ein ein e
C o r r eC o r r eC o r r eC o r r e c t G -S e n s o r L E D d e s i g n d e f in ec t G -S e n s o r L E D d e s i g n d e f in ec t G -S e n s o r L E D d e s i g n d e f in ec t G -S e n s o r L E D d e s i g n d e f in e
CCCC h a n g e Q 1 5 3 f r o m 2 N 7 0 0 2 D W t o 2 N 7 0 0 2h a n g e Q 1 5 3 f r o m 2 N 7 0 0 2 D W t o 2 N 7 0 0 2h a n g e Q 1 5 3 f r o m 2 N 7 0 0 2 D W t o 2 N 7 0 0 2h a n g e Q 1 5 3 f r o m 2 N 7 0 0 2 D W t o 2 N 7 0 0 2
C h a n g e R 9 8 8 . 1 c o n n e c t i o n f r o m +C h a n g e R 9 8 8 . 1 c o n n e c t i o n f r o m +C h a n g e R 9 8 8 . 1 c o n n e c t i o n f r o m +C h a n g e R 9 8 8 . 1 c o n n e c t i o n f r o m + 5 V S _ L E D t o + 3 V S5 V S _ L E D t o + 3 V S5 V S _ L E D t o + 3 V S5 V S _ L E D t o + 3 V S0 . 20 . 20 . 20 . 2
2 92 92 92 9 A u d ioA u d ioA u d ioA u d io -D o c k-D o c k-D o c k-D o c k 1 11 11 11 1 / 1 4/ 1 4/ 1 4/ 1 4 H P QH P QH P QH P Q FFFF o r G S m a r k r e q u i r e m e n to r G S m a r k r e q u i r e m e n to r G S m a r k r e q u i r e m e n to r G S m a r k r e q u i r e m e n t A dA dA dA d d R 9 6 8 , R 9 6 9 c l o s e t o C 7 7 5 / C 7 7 6 .d R 9 6 8 , R 9 6 9 c l o s e t o C 7 7 5 / C 7 7 6 .d R 9 6 8 , R 9 6 9 c l o s e t o C 7 7 5 / C 7 7 6 .d R 9 6 8 , R 9 6 9 c l o s e t o C 7 7 5 / C 7 7 6 . 0 . 20 . 20 . 20 . 25 55 55 55 5
H o le sH o le sH o le sH o le s 1 11 11 11 1 / 1 4/ 1 4/ 1 4/ 1 4 M EM EM EM E U p d a t e U p d a t e U p d a t e U p d a t e H o l e s t o m e e t M / E D r a w in gH o l e s t o m e e t M / E D r a w in gH o l e s t o m e e t M / E D r a w in gH o l e s t o m e e t M / E D r a w in g A d d A d d A d d A d d b a c k H 5 2 b e c o m e H _ 1 P 5 N ; D e l C F 4b a c k H 5 2 b e c o m e H _ 1 P 5 N ; D e l C F 4b a c k H 5 2 b e c o m e H _ 1 P 5 N ; D e l C F 4b a c k H 5 2 b e c o m e H _ 1 P 5 N ; D e l C F 4 0 . 20 . 20 . 20 . 25 65 65 65 6 2 92 92 92 9
M uM uM uM u lt i -B a ylt i -B a ylt i -B a ylt i -B a y 1 11 11 11 1 / 1 4/ 1 4/ 1 4/ 1 45 75 75 75 7 M EM EM EM E U p d a t e S yU p d a t e S yU p d a t e S yU p d a t e S y m b o l t o m e e t M / E D r a w in gm b o l t o m e e t M / E D r a w in gm b o l t o m e e t M / E D r a w in gm b o l t o m e e t M / E D r a w in g U p d a t e J P 2 , J P 9 , J P 1 0 , J P 1 1 , J P 2 0 , J P 4 0 , J H D M I , JU p d a t e J P 2 , J P 9 , J P 1 0 , J P 1 1 , J P 2 0 , J P 4 0 , J H D M I , JU p d a t e J P 2 , J P 9 , J P 1 0 , J P 1 1 , J P 2 0 , J P 4 0 , J H D M I , JU p d a t e J P 2 , J P 9 , J P 1 0 , J P 1 1 , J P 2 0 , J P 4 0 , J H D M I , J E S A T ,J C R T ,E S A T ,J C R T ,E S A T ,J C R T ,E S A T ,J C R T ,
J D O C KJ D O C KJ D O C KJ D O C K S y m b o l S y m b o l S y m b o l S y m b o l0 . 20 . 20 . 20 . 24 ,4 ,4 ,4 , 2 42 42 42 4
H o le sH o le sH o le sH o le s 1 11 11 11 1 / 1 4/ 1 4/ 1 4/ 1 45 85 85 85 8 M EM EM EM E U p d a t e U p d a t e U p d a t e U p d a t e H o l e s t o m e e t M / E D r a w in gH o l e s t o m e e t M / E D r a w in gH o l e s t o m e e t M / E D r a w in gH o l e s t o m e e t M / E D r a w in g A d d A d d A d d A d d b a c k H 5 2 b e c o m e H _ 1 P 5 N ; D e l C F 4b a c k H 5 2 b e c o m e H _ 1 P 5 N ; D e l C F 4b a c k H 5 2 b e c o m e H _ 1 P 5 N ; D e l C F 4b a c k H 5 2 b e c o m e H _ 1 P 5 N ; D e l C F 4 0 . 20 . 20 . 20 . 23 33 33 33 3
S BS BS BS B 1 11 11 11 1 / 1 6/ 1 6/ 1 6/ 1 65 95 95 95 9 AAAA T IT IT IT I R eR eR eR e s e r v e t o f i x t h e O T S 3 2 5 0 5 5 I s s u e s e r v e t o f i x t h e O T S 3 2 5 0 5 5 I s s u e s e r v e t o f i x t h e O T S 3 2 5 0 5 5 I s s u e s e r v e t o f i x t h e O T S 3 2 5 0 5 5 I s s u e R e sR e sR e sR e s e r v e R 8 3 P H t o + 3 V Se r v e R 8 3 P H t o + 3 V Se r v e R 8 3 P H t o + 3 V Se r v e R 8 3 P H t o + 3 V S 0 . 20 . 20 . 20 . 22 02 02 02 0
6 06 06 06 0 K B CK B CK B CK B C 1 11 11 11 1 / 1 6/ 1 6/ 1 6/ 1 6 E CE CE CE C3 33 33 33 3 C hC hC hC h a n g e d e s i g n f o r E C t e a m d e b u ga n g e d e s i g n f o r E C t e a m d e b u ga n g e d e s i g n f o r E C t e a m d e b u ga n g e d e s i g n f o r E C t e a m d e b u g C h a n g e J P 3 4 . 1 f r o m + 5 V A L W C h a n g e J P 3 4 . 1 f r o m + 5 V A L W C h a n g e J P 3 4 . 1 f r o m + 5 V A L W C h a n g e J P 3 4 . 1 f r o m + 5 V A L W t o + 5 V Lt o + 5 V Lt o + 5 V Lt o + 5 V L 0 . 20 . 20 . 20 . 2
6 16 16 16 1 3 53 53 53 5 D O C KD O C KD O C KD O C K 1 11 11 11 1 / 1 6/ 1 6/ 1 6/ 1 6 EEEE M CM CM CM C C o n n eC o n n eC o n n eC o n n e c t D O C K g u id e p in t o G N Dc t D O C K g u id e p in t o G N Dc t D O C K g u id e p in t o G N Dc t D O C K g u id e p in t o G N D A d d J D O C K . 4 5 / 4 6 A d d J D O C K . 4 5 / 4 6 A d d J D O C K . 4 5 / 4 6 A d d J D O C K . 4 5 / 4 6 t o G N Dt o G N Dt o G N Dt o G N D 0 . 20 . 20 . 20 . 2
6 26 26 26 2 3 33 33 33 3 KKKK / B/ B/ B/ B 1 11 11 11 1 / 1 6/ 1 6/ 1 6/ 1 6 H WH WH WH W F ix K B m a t r iF ix K B m a t r iF ix K B m a t r iF ix K B m a t r i x i s su ex i s su ex i s su ex i s su e D e l K S I 6 a n d K S O 9 o u t o f pD e l K S I 6 a n d K S O 9 o u t o f pD e l K S I 6 a n d K S O 9 o u t o f pD e l K S I 6 a n d K S O 9 o u t o f p a g e n e t c o n n ec ta g e n e t c o n n ec ta g e n e t c o n n ec ta g e n e t c o n n ec t 0 . 20 . 20 . 20 . 2
6 36 36 36 3 2 8 ,2 8 ,2 8 ,2 8 , 2 92 92 92 9 A UA UA UA U D I OD I OD I OD I O 1 11 11 11 1 / 1 8/ 1 8/ 1 8/ 1 8 H P QH P QH P QH P Q M a k e sM a k e sM a k e sM a k e s o m e A u d io r e l a t e d d e s i g n c h a n g eo m e A u d io r e l a t e d d e s i g n c h a n g eo m e A u d io r e l a t e d d e s i g n c h a n g eo m e A u d io r e l a t e d d e s i g n c h a n g e C h a n g e C 9 8 3 , C 9 8 4 f r o m 1 U F t o 0 . 0 2 2 U F . C h a n g e C 1 0 4 9 , CC h a n g e C 9 8 3 , C 9 8 4 f r o m 1 U F t o 0 . 0 2 2 U F . C h a n g e C 1 0 4 9 , CC h a n g e C 9 8 3 , C 9 8 4 f r o m 1 U F t o 0 . 0 2 2 U F . C h a n g e C 1 0 4 9 , CC h a n g e C 9 8 3 , C 9 8 4 f r o m 1 U F t o 0 . 0 2 2 U F . C h a n g e C 1 0 4 9 , C 1 0 5 0 ,C 1 0 4 0 ,C 1 0 4 1 1 0 5 0 ,C 1 0 4 0 ,C 1 0 4 1 1 0 5 0 ,C 1 0 4 0 ,C 1 0 4 1 1 0 5 0 ,C 1 0 4 0 ,C 1 0 4 1
f r o m 0 . 4 7 U F t o 0 . 0 2 2 U F . C h a n g e R 1 0 0 2 , R 1 0 0 5 f r o m 2 0 K t o 0 o h m . C h a n gf r o m 0 . 4 7 U F t o 0 . 0 2 2 U F . C h a n g e R 1 0 0 2 , R 1 0 0 5 f r o m 2 0 K t o 0 o h m . C h a n gf r o m 0 . 4 7 U F t o 0 . 0 2 2 U F . C h a n g e R 1 0 0 2 , R 1 0 0 5 f r o m 2 0 K t o 0 o h m . C h a n gf r o m 0 . 4 7 U F t o 0 . 0 2 2 U F . C h a n g e R 1 0 0 2 , R 1 0 0 5 f r o m 2 0 K t o 0 o h m . C h a n g e e e e
C 1 0 4 4 f r o m 1 0 U F t o 4 . 7 U F . R e m o v e R 1 0 0 0 , RC 1 0 4 4 f r o m 1 0 U F t o 4 . 7 U F . R e m o v e R 1 0 0 0 , RC 1 0 4 4 f r o m 1 0 U F t o 4 . 7 U F . R e m o v e R 1 0 0 0 , RC 1 0 4 4 f r o m 1 0 U F t o 4 . 7 U F . R e m o v e R 1 0 0 0 , R 1 0 0 4 ; I n s t a l l R 1 0 0 1 ,R 1 0 0 3 .1 0 0 4 ; I n s t a l l R 1 0 0 1 ,R 1 0 0 3 .1 0 0 4 ; I n s t a l l R 1 0 0 1 ,R 1 0 0 3 .1 0 0 4 ; I n s t a l l R 1 0 0 1 ,R 1 0 0 3 .
0 . 20 . 20 . 20 . 2
6 46 46 46 4 2 92 92 92 9 A UA UA UA U D I OD I OD I OD I O 1 11 11 11 1 / 1 9/ 1 9/ 1 9/ 1 9 H P QH P QH P QH P Q M a k e sM a k e sM a k e sM a k e s o m e A u d io r e l a t e d d e s i g n c h a n g eo m e A u d io r e l a t e d d e s i g n c h a n g eo m e A u d io r e l a t e d d e s i g n c h a n g eo m e A u d io r e l a t e d d e s i g n c h a n g e C h a n g e R 9 6 8 , R 9 6 9 f r o m 4 0 . 2 _ 0 4 0 2 t o 4 7 _ 0 6 0 3C h a n g e R 9 6 8 , R 9 6 9 f r o m 4 0 . 2 _ 0 4 0 2 t o 4 7 _ 0 6 0 3C h a n g e R 9 6 8 , R 9 6 9 f r o m 4 0 . 2 _ 0 4 0 2 t o 4 7 _ 0 6 0 3C h a n g e R 9 6 8 , R 9 6 9 f r o m 4 0 . 2 _ 0 4 0 2 t o 4 7 _ 0 6 0 3 0 . 20 . 20 . 20 . 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 1.C
HW Changed-List History-2
Custom
49 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
V ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it
I t e mI t e mI t e mI t e m I s s u e DI s s u e DI s s u e DI s s u e D e s c r ip t i o ne s c r ip t i o ne s c r ip t i o ne s c r ip t i o nD a t eD a t eD a t eD a t eR e qR e qR e qR e q u e s tu e s tu e s tu e s t
O w nO w nO w nO w n e re re re r S oS oS oS o lu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io n R e v .R e v .R e v .R e v .P aP aP aP a g e #g e #g e #g e # TTTT it l ei t l ei t l ei t l e
6 56 56 56 5 1 31 31 31 3 N BN BN BN B 1 11 11 11 1 / 2 0/ 2 0/ 2 0/ 2 0 AAAA T IT IT IT I D e s i gD e s i gD e s i gD e s i g n C h a n g e f o r N B A 1 2 V e r s i o n c h ipn C h a n g e f o r N B A 1 2 V e r s i o n c h ipn C h a n g e f o r N B A 1 2 V e r s i o n c h ipn C h a n g e f o r N B A 1 2 V e r s i o n c h ip R e mR e mR e mR e m o v e U 6 4 , C 1 0 6 4 , C 1 0 6 5 , C 1 0 6 6 , C 1 0 6 7 , R 1 0 1 5 , R 1 0 1 6 , Q 1 6 3 , R 1 0 1 7 .o v e U 6 4 , C 1 0 6 4 , C 1 0 6 5 , C 1 0 6 6 , C 1 0 6 7 , R 1 0 1 5 , R 1 0 1 6 , Q 1 6 3 , R 1 0 1 7 .o v e U 6 4 , C 1 0 6 4 , C 1 0 6 5 , C 1 0 6 6 , C 1 0 6 7 , R 1 0 1 5 , R 1 0 1 6 , Q 1 6 3 , R 1 0 1 7 .o v e U 6 4 , C 1 0 6 4 , C 1 0 6 5 , C 1 0 6 6 , C 1 0 6 7 , R 1 0 1 5 , R 1 0 1 6 , Q 1 6 3 , R 1 0 1 7 .
I nI nI nI n s t a l l L 1 9 , r e m o v e L 9 5s t a l l L 1 9 , r e m o v e L 9 5s t a l l L 1 9 , r e m o v e L 9 5s t a l l L 1 9 , r e m o v e L 9 50 . 20 . 20 . 20 . 2
6 66 66 66 6 2 22 22 22 2 S BS BS BS B 1 11 11 11 1 / 2 0/ 2 0/ 2 0/ 2 0 AAAA T IT IT IT I D e s i gD e s i gD e s i gD e s i g n C h a n g e f o r S B A 1 2 V e r s i o n c h ipn C h a n g e f o r S B A 1 2 V e r s i o n c h ipn C h a n g e f o r S B A 1 2 V e r s i o n c h ipn C h a n g e f o r S B A 1 2 V e r s i o n c h ip I n s t a l l I n s t a l l I n s t a l l I n s t a l l R 5 9 3 , r e m o v e R 5 9 2R 5 9 3 , r e m o v e R 5 9 2R 5 9 3 , r e m o v e R 5 9 2R 5 9 3 , r e m o v e R 5 9 2 0 . 20 . 20 . 20 . 2
6 76 76 76 7 2 22 22 22 2 S BS BS BS B 1 11 11 11 1 / 2 0/ 2 0/ 2 0/ 2 0 H WH WH WH W R e d u c e S B R e d u c e S B R e d u c e S B R e d u c e S B P o w e r D e s i g n -N o I D E s u p p o r tP o w e r D e s i g n -N o I D E s u p p o r tP o w e r D e s i g n -N o I D E s u p p o r tP o w e r D e s i g n -N o I D E s u p p o r t R eR eR eR e m o v e R 1 2 ,C 5 4 3 ,C 5 4 4 ,C 5 4 7 ,C 5 3 6m o v e R 1 2 ,C 5 4 3 ,C 5 4 4 ,C 5 4 7 ,C 5 3 6m o v e R 1 2 ,C 5 4 3 ,C 5 4 4 ,C 5 4 7 ,C 5 3 6m o v e R 1 2 ,C 5 4 3 ,C 5 4 4 ,C 5 4 7 ,C 5 3 6 0 . 20 . 20 . 20 . 2
6 86 86 86 8 3 3 ,3 3 ,3 3 ,3 3 , 3 43 43 43 4 F u n c t io n B oF u n c t io n B oF u n c t io n B oF u n c t io n B o a rda rda rda rd 1 11 11 11 1 / 2 0/ 2 0/ 2 0/ 2 0 H WH WH WH W R e s e r v e f o r R a c h m a n U M A s e l e cR e s e r v e f o r R a c h m a n U M A s e l e cR e s e r v e f o r R a c h m a n U M A s e l e cR e s e r v e f o r R a c h m a n U M A s e l e c t iv et iv et iv et iv e R e s e rR e s e rR e s e rR e s e r v e R 5 5 5 f o r + 5 V A L W _ L E D , a d d R 5 5 4 f o r + 3 V L c l o s e t o J P 3 6 . 1v e R 5 5 5 f o r + 5 V A L W _ L E D , a d d R 5 5 4 f o r + 3 V L c l o s e t o J P 3 6 . 1v e R 5 5 5 f o r + 5 V A L W _ L E D , a d d R 5 5 4 f o r + 3 V L c l o s e t o J P 3 6 . 1v e R 5 5 5 f o r + 5 V A L W _ L E D , a d d R 5 5 4 f o r + 3 V L c l o s e t o J P 3 6 . 1
R e s e r v e R 1 0 3 4 c l o s eR e s e r v e R 1 0 3 4 c l o s eR e s e r v e R 1 0 3 4 c l o s eR e s e r v e R 1 0 3 4 c l o s e t o J P 3 6 . 4 , R 1 0 3 5 c l o s e J P 3 6 . 5 , R e m o v e R 1 0 3 6 t o J P 3 6 . 4 , R 1 0 3 5 c l o s e J P 3 6 . 5 , R e m o v e R 1 0 3 6 t o J P 3 6 . 4 , R 1 0 3 5 c l o s e J P 3 6 . 5 , R e m o v e R 1 0 3 6 t o J P 3 6 . 4 , R 1 0 3 5 c l o s e J P 3 6 . 5 , R e m o v e R 1 0 3 6
A d d R 5 1 3 P H t o + 3 V S c l o s e t o U 3 3 . 1 9A d d R 5 1 3 P H t o + 3 V S c l o s e t o U 3 3 . 1 9A d d R 5 1 3 P H t o + 3 V S c l o s e t o U 3 3 . 1 9A d d R 5 1 3 P H t o + 3 V S c l o s e t o U 3 3 . 1 9
0 . 20 . 20 . 20 . 2
6 96 96 96 9 2 32 32 32 3 S BS BS BS B 1 11 11 11 1 / 2 0/ 2 0/ 2 0/ 2 0 H WH WH WH W M a kM a kM a kM a k e t h e S B S t r a p S e e t in g f o r c o m m o ne t h e S B S t r a p S e e t in g f o r c o m m o ne t h e S B S t r a p S e e t in g f o r c o m m o ne t h e S B S t r a p S e e t in g f o r c o m m o n I n s tI n s tI n s tI n s t a l l R 3 5 6 (1 0 K _ 0 4 0 2 )a l l R 3 5 6 (1 0 K _ 0 4 0 2 )a l l R 3 5 6 (1 0 K _ 0 4 0 2 )a l l R 3 5 6 (1 0 K _ 0 4 0 2 ) 0 . 20 . 20 . 20 . 2
7 07 07 07 0 3 13 13 13 1 BBBB lu e T o o t hlu e T o o t hlu e T o o t hlu e T o o t h 1 11 11 11 1 / 2 0/ 2 0/ 2 0/ 2 0 H WH WH WH W U p d a t e BU p d a t e BU p d a t e BU p d a t e B T d e s i g n f o r c o m m o nT d e s i g n f o r c o m m o nT d e s i g n f o r c o m m o nT d e s i g n f o r c o m m o n C h a n g e R 5 2 0 f r o m 4 7 K _ 0 4 0 2 t o 1 0 K _ 0C h a n g e R 5 2 0 f r o m 4 7 K _ 0 4 0 2 t o 1 0 K _ 0C h a n g e R 5 2 0 f r o m 4 7 K _ 0 4 0 2 t o 1 0 K _ 0C h a n g e R 5 2 0 f r o m 4 7 K _ 0 4 0 2 t o 1 0 K _ 0 4 0 24 0 24 0 24 0 2 0 . 20 . 20 . 20 . 2
7 17 17 17 1 3 43 43 43 4 P o w e r O n S w iP o w e r O n S w iP o w e r O n S w iP o w e r O n S w i tchtchtchtch 1 11 11 11 1 / 2 2/ 2 2/ 2 2/ 2 2 H WH WH WH W C a n c eC a n c eC a n c eC a n c e l o n e r e s e r v e d p o w e r o n s w i t c hl o n e r e s e r v e d p o w e r o n s w i t c hl o n e r e s e r v e d p o w e r o n s w i t c hl o n e r e s e r v e d p o w e r o n s w i t c h D e l SD e l SD e l SD e l S W 3W 3W 3W 3 0 . 20 . 20 . 20 . 2
7 27 27 27 2 3 33 33 33 3 K B CK B CK B CK B C 1 11 11 11 1 / 2 2/ 2 2/ 2 2/ 2 2 H WH WH WH W M o d i f y M o d i f y M o d i f y M o d i f y S M B _ E C _ D A 1 / C K 1 P H f o r c o m m o nS M B _ E C _ D A 1 / C K 1 P H f o r c o m m o nS M B _ E C _ D A 1 / C K 1 P H f o r c o m m o nS M B _ E C _ D A 1 / C K 1 P H f o r c o m m o n C h a n g e C h a n g e C h a n g e C h a n g e R 5 2 8 ,R 5 2 9 p in 2 c o n n e c t i o n f r o m + 5 V L t o + 3 V LR 5 2 8 ,R 5 2 9 p in 2 c o n n e c t i o n f r o m + 5 V L t o + 3 V LR 5 2 8 ,R 5 2 9 p in 2 c o n n e c t i o n f r o m + 5 V L t o + 3 V LR 5 2 8 ,R 5 2 9 p in 2 c o n n e c t i o n f r o m + 5 V L t o + 3 V L 0 . 20 . 20 . 20 . 2
7 37 37 37 3 6666 C P UC P UC P UC P U 1 11 11 11 1 / 2 2/ 2 2/ 2 2/ 2 2 H WH WH WH W L in k P R O C H O T # b e t w e e n C PL in k P R O C H O T # b e t w e e n C PL in k P R O C H O T # b e t w e e n C PL in k P R O C H O T # b e t w e e n C P U a n d N BU a n d N BU a n d N BU a n d N B A d d R 5 9 c l o s e t o Q 2A d d R 5 9 c l o s e t o Q 2A d d R 5 9 c l o s e t o Q 2A d d R 5 9 c l o s e t o Q 2 0 . 20 . 20 . 20 . 2
7 47 47 47 4 1 91 91 91 9 S BS BS BS B 1 11 11 11 1 / 2 2/ 2 2/ 2 2/ 2 2 H WH WH WH W RRRR e s e r v e L P C C L K 1 f o r d e b u g c a r d f u n c t i o ne s e r v e L P C C L K 1 f o r d e b u g c a r d f u n c t i o ne s e r v e L P C C L K 1 f o r d e b u g c a r d f u n c t i o ne s e r v e L P C C L K 1 f o r d e b u g c a r d f u n c t i o n A d dA d dA d dA d d R 3 0 8 2 2 _ 0 4 0 2 f o r U 1 5 . E 2 2 c l o s e t o R 3 6 2 . 1 , r e m o v e R 3 0 1 R 3 0 8 2 2 _ 0 4 0 2 f o r U 1 5 . E 2 2 c l o s e t o R 3 6 2 . 1 , r e m o v e R 3 0 1 R 3 0 8 2 2 _ 0 4 0 2 f o r U 1 5 . E 2 2 c l o s e t o R 3 6 2 . 1 , r e m o v e R 3 0 1 R 3 0 8 2 2 _ 0 4 0 2 f o r U 1 5 . E 2 2 c l o s e t o R 3 6 2 . 1 , r e m o v e R 3 0 1 0 . 20 . 20 . 20 . 2
7 57 57 57 5 2 62 62 62 6 E x p r e s s C aE x p r e s s C aE x p r e s s C aE x p r e s s C a rdrdrdrd 1 11 11 11 1 / 2 2/ 2 2/ 2 2/ 2 2 H WH WH WH W T o a v o i d NT o a v o i d NT o a v o i d NT o a v o i d N e w C a r d S w i t c h l e a k a g e i s s u ee w C a r d S w i t c h l e a k a g e i s s u ee w C a r d S w i t c h l e a k a g e i s s u ee w C a r d S w i t c h l e a k a g e i s s u e A d d R 5 4 (0 _ 0 4 0 2 ) c l o s e t o U 2A d d R 5 4 (0 _ 0 4 0 2 ) c l o s e t o U 2A d d R 5 4 (0 _ 0 4 0 2 ) c l o s e t o U 2A d d R 5 4 (0 _ 0 4 0 2 ) c l o s e t o U 2 1 .61 .61 .61 .6 0 . 20 . 20 . 20 . 2
7 67 67 67 6 2 82 82 82 8 A u dA u dA u dA u d io C o d e cio C o d e cio C o d e cio C o d e c 1 11 11 11 1 / 2 2/ 2 2/ 2 2/ 2 2 H WH WH WH W R e s e r vR e s e r vR e s e r vR e s e r v e S P D I F O U T 1 t e s t p o in t f o r v e r i f ye S P D I F O U T 1 t e s t p o in t f o r v e r i f ye S P D I F O U T 1 t e s t p o in t f o r v e r i f ye S P D I F O U T 1 t e s t p o in t f o r v e r i f y A d d T 2 1 c l o s e t o U 2 7 .A d d T 2 1 c l o s e t o U 2 7 .A d d T 2 1 c l o s e t o U 2 7 .A d d T 2 1 c l o s e t o U 2 7 . 4 54 54 54 5 0 . 20 . 20 . 20 . 2
7 77 77 77 7 1 01 01 01 0 ~ 1 3~ 1 3~ 1 3~ 1 3 NNNN B ,B ,B ,B , 1 11 11 11 1 / 2 3/ 2 3/ 2 3/ 2 3 H WH WH WH W B O M c o r r e c t f o r S I -1 S M T b uB O M c o r r e c t f o r S I -1 S M T b uB O M c o r r e c t f o r S I -1 S M T b uB O M c o r r e c t f o r S I -1 S M T b u i ldi ldi ldi ld U p d a t e U 3 ( S A 0 0 0 0 1 Z G 0 0 - - > S A 0 0 0 0 1 Z G 2 0 ) ; U 1 0 ( S A 0 0 0 0U p d a t e U 3 ( S A 0 0 0 0 1 Z G 0 0 - - > S A 0 0 0 0 1 Z G 2 0 ) ; U 1 0 ( S A 0 0 0 0U p d a t e U 3 ( S A 0 0 0 0 1 Z G 0 0 - - > S A 0 0 0 0 1 Z G 2 0 ) ; U 1 0 ( S A 0 0 0 0U p d a t e U 3 ( S A 0 0 0 0 1 Z G 0 0 - - > S A 0 0 0 0 1 Z G 2 0 ) ; U 1 0 ( S A 0 0 0 0 1 Z 3 0 0 - ->1 Z 3 0 0 - ->1 Z 3 0 0 - ->1 Z 3 0 0 - ->
S A 0 0 0 0 1 Z 3 1 0 ) ; U 1 5 ( S A 0 0 0 0 1 S 5 1 0 - - > S A 0S A 0 0 0 0 1 Z 3 1 0 ) ; U 1 5 ( S A 0 0 0 0 1 S 5 1 0 - - > S A 0S A 0 0 0 0 1 Z 3 1 0 ) ; U 1 5 ( S A 0 0 0 0 1 S 5 1 0 - - > S A 0S A 0 0 0 0 1 Z 3 1 0 ) ; U 1 5 ( S A 0 0 0 0 1 S 5 1 0 - - > S A 0 0 0 0 1 S 5 6 0 )0 0 0 1 S 5 6 0 )0 0 0 1 S 5 6 0 )0 0 0 1 S 5 6 0 )0 . 20 . 20 . 20 . 2
7 87 87 87 8 1 91 91 91 9 S BS BS BS B 1 11 11 11 1 / 2 3/ 2 3/ 2 3/ 2 3 H WH WH WH W CCCC h a n g e C r y s t a l R e s . s i z e f o r l a y o u t s p a c eh a n g e C r y s t a l R e s . s i z e f o r l a y o u t s p a c eh a n g e C r y s t a l R e s . s i z e f o r l a y o u t s p a c eh a n g e C r y s t a l R e s . s i z e f o r l a y o u t s p a c e C h a n g e R 3 8 9 f r o m 0 6 0 3 t oC h a n g e R 3 8 9 f r o m 0 6 0 3 t oC h a n g e R 3 8 9 f r o m 0 6 0 3 t oC h a n g e R 3 8 9 f r o m 0 6 0 3 t o 0 4 0 2 0 4 0 2 0 4 0 2 0 4 0 2 0 . 20 . 20 . 20 . 2
7 97 97 97 9 2 22 22 22 2 S BS BS BS B 1 11 11 11 1 / 2 6/ 2 6/ 2 6/ 2 6 H WH WH WH W R e d u c e S B S A T A P o w e r C a p s (C o n f i r m w i t h A T I F A E )R e d u c e S B S A T A P o w e r C a p s (C o n f i r m w i t h A T I F A E )R e d u c e S B S A T A P o w e r C a p s (C o n f i r m w i t h A T I F A E )R e d u c e S B S A T A P o w e r C a p s (C o n f i r m w i t h A T I F A E ) C h a n g e C 5 6 7 ,C 5 6 8 f r o m 1 0 U _ 0 8 0 5 t o 1 U _ 0C h a n g e C 5 6 7 ,C 5 6 8 f r o m 1 0 U _ 0 8 0 5 t o 1 U _ 0C h a n g e C 5 6 7 ,C 5 6 8 f r o m 1 0 U _ 0 8 0 5 t o 1 U _ 0C h a n g e C 5 6 7 ,C 5 6 8 f r o m 1 0 U _ 0 8 0 5 t o 1 U _ 0 8 0 58 0 58 0 58 0 5 0 . 20 . 20 . 20 . 2
8 08 08 08 0 2 82 82 82 8 C o d e cC o d e cC o d e cC o d e c 1 11 11 11 1 / 2 6/ 2 6/ 2 6/ 2 6 H WH WH WH W S P D I F 0 - - > 1S P D I F 0 - - > 1S P D I F 0 - - > 1S P D I F 0 - - > 1 d e s i g n c h a n g e t o f o l l o w V a d e r d e s i g n c h a n g e t o f o l l o w V a d e r d e s i g n c h a n g e t o f o l l o w V a d e r d e s i g n c h a n g e t o f o l l o w V a d e r C h a n g e U 2 7 . 4C h a n g e U 2 7 . 4C h a n g e U 2 7 . 4C h a n g e U 2 7 . 4 8 / 4 5 p in c o n n e c t i o n8 / 4 5 p in c o n n e c t i o n8 / 4 5 p in c o n n e c t i o n8 / 4 5 p in c o n n e c t i o n 0 . 20 . 20 . 20 . 2
8 18 18 18 1 3 43 43 43 4 T / PT / PT / PT / P 1 11 11 11 1 / 2 8/ 2 8/ 2 8/ 2 8 H WH WH WH W C h a n g e T /C h a n g e T /C h a n g e T /C h a n g e T / P P o w e r f o r r e d u c e S 4 / S 5 p o w e r c o n s u m p t io nP P o w e r f o r r e d u c e S 4 / S 5 p o w e r c o n s u m p t io nP P o w e r f o r r e d u c e S 4 / S 5 p o w e r c o n s u m p t io nP P o w e r f o r r e d u c e S 4 / S 5 p o w e r c o n s u m p t io n R e m o vR e m o vR e m o vR e m o v e R 2 3 5 ; A d d Q 8 5 , R 6 4 5 , Q 3 4e R 2 3 5 ; A d d Q 8 5 , R 6 4 5 , Q 3 4e R 2 3 5 ; A d d Q 8 5 , R 6 4 5 , Q 3 4e R 2 3 5 ; A d d Q 8 5 , R 6 4 5 , Q 3 4 0 . 20 . 20 . 20 . 2
8 28 28 28 2 1 41 41 41 4 HHHH D M ID M ID M ID M I 1 11 11 11 1 / 2 8/ 2 8/ 2 8/ 2 8 AAAA T IT IT IT I F iF iF iF i x H D M I n o f u n c t i o n i s s u ex H D M I n o f u n c t i o n i s s u ex H D M I n o f u n c t i o n i s s u ex H D M I n o f u n c t i o n i s s u e R e m o v eR e m o v eR e m o v eR e m o v e R 1 0 2 ; A d d R 1 0 1 R 1 0 2 ; A d d R 1 0 1 R 1 0 2 ; A d d R 1 0 1 R 1 0 2 ; A d d R 1 0 1 0 . 20 . 20 . 20 . 2
8 38 38 38 3 1 51 51 51 5 C L KC L KC L KC L K G e n . G e n . G e n . G e n . 1 11 11 11 1 / 2 8/ 2 8/ 2 8/ 2 8 H WH WH WH W C h a nC h a nC h a nC h a n g e d e s i g n f o r n e w v e r s i o n C L K G e n .g e d e s i g n f o r n e w v e r s i o n C L K G e n .g e d e s i g n f o r n e w v e r s i o n C L K G e n .g e d e s i g n f o r n e w v e r s i o n C L K G e n . R e m o v e R e m o v e R e m o v e R e m o v e R 1 0 4 5R 1 0 4 5R 1 0 4 5R 1 0 4 5 0 . 20 . 20 . 20 . 2
8 48 48 48 4 2 82 82 82 8 C o d e cC o d e cC o d e cC o d e c 1 11 11 11 1 / 2 8/ 2 8/ 2 8/ 2 8 H WH WH WH W C h a n g e E C _ B E E P f u n c t i o n b e c o m e r eC h a n g e E C _ B E E P f u n c t i o n b e c o m e r eC h a n g e E C _ B E E P f u n c t i o n b e c o m e r eC h a n g e E C _ B E E P f u n c t i o n b e c o m e r e s e rv es e rv es e rv es e rv e R e m o v e R e m o v e R e m o v e R e m o v e R 5 6 3R 5 6 3R 5 6 3R 5 6 3 0 . 20 . 20 . 20 . 2
2 0 ,2 0 ,2 0 ,2 0 , 2 72 72 72 78 58 58 58 5 S B ,CS B ,CS B ,CS B ,C a rd R ea d e ra rd R ea d e ra rd R ea d e ra rd R ea d e r 1 11 11 11 1 / 2 8/ 2 8/ 2 8/ 2 8 H WH WH WH W D i s c o n n e c t D 3 E s u pD i s c o n n e c t D 3 E s u pD i s c o n n e c t D 3 E s u pD i s c o n n e c t D 3 E s u p p o r t f o r A v e r s i o n t o a v o id r i s kp o r t f o r A v e r s i o n t o a v o id r i s kp o r t f o r A v e r s i o n t o a v o id r i s kp o r t f o r A v e r s i o n t o a v o id r i s k R e m o v e R e m o v e R e m o v e R e m o v e R 8 1 ,R 3 6 9R 8 1 ,R 3 6 9R 8 1 ,R 3 6 9R 8 1 ,R 3 6 9 0 . 20 . 20 . 20 . 2
3 23 23 23 28 68 68 68 6 BBBB I O SI O SI O SI O S 1 11 11 11 1 / 2 8/ 2 8/ 2 8/ 2 8 H WH WH WH W U s e E x t . B I O S a s dU s e E x t . B I O S a s dU s e E x t . B I O S a s dU s e E x t . B I O S a s d e fa u lte fa u lte fa u lte fa u lt R e m o v e R e m o v e R e m o v e R e m o v e R 2 2 1R 2 2 1R 2 2 1R 2 2 1 0 . 20 . 20 . 20 . 2
8 78 78 78 7 3 43 43 43 4 LLLL E DE DE DE D 1 11 11 11 1 / 2 8/ 2 8/ 2 8/ 2 8 H WH WH WH W C a n c e l W L A N / W W A N e x t p u l l h i g hC a n c e l W L A N / W W A N e x t p u l l h i g hC a n c e l W L A N / W W A N e x t p u l l h i g hC a n c e l W L A N / W W A N e x t p u l l h i g h R e m o v e R e m o v e R e m o v e R e m o v e R 1 0 4 1R 1 0 4 1R 1 0 4 1R 1 0 4 1 0 . 20 . 20 . 20 . 2
8 88 88 88 8 1 91 91 91 9 S BS BS BS B 1 11 11 11 1 / 3 0/ 3 0/ 3 0/ 3 0 H WH WH WH W F ix P A M / E I n t e r f e r e i s s u e f oF ix P A M / E I n t e r f e r e i s s u e f oF ix P A M / E I n t e r f e r e i s s u e f oF ix P A M / E I n t e r f e r e i s s u e f o r S I -1r S I -1r S I -1r S I -1 c h a n g e Yc h a n g e Yc h a n g e Yc h a n g e Y 3 f r o m S J 1 0 0 0 0 1 U 0 0 t o S J 1 0 0 0 0 6 6 0 0 w i t h 1 0 P P M3 f r o m S J 1 0 0 0 0 1 U 0 0 t o S J 1 0 0 0 0 6 6 0 0 w i t h 1 0 P P M3 f r o m S J 1 0 0 0 0 1 U 0 0 t o S J 1 0 0 0 0 6 6 0 0 w i t h 1 0 P P M3 f r o m S J 1 0 0 0 0 1 U 0 0 t o S J 1 0 0 0 0 6 6 0 0 w i t h 1 0 P P M 0 . 20 . 20 . 20 . 2
8 98 98 98 9 0 60 60 60 6 , 1 9 ,, 1 9 ,, 1 9 ,, 1 9 ,
2 32 32 32 3S BS BS BS B 1 11 11 11 1 / 3 0/ 3 0/ 3 0/ 3 0 AAAA T IT IT IT I A T I A T I A T I A T I r e c o m m e n d f o r u p d a t er e c o m m e n d f o r u p d a t er e c o m m e n d f o r u p d a t er e c o m m e n d f o r u p d a t e C h a n g e R 3 1 2 f r o m 0 _ 0 4 0 2 t o 3 3 _ 0 4 0 2 ; C h a nC h a n g e R 3 1 2 f r o m 0 _ 0 4 0 2 t o 3 3 _ 0 4 0 2 ; C h a nC h a n g e R 3 1 2 f r o m 0 _ 0 4 0 2 t o 3 3 _ 0 4 0 2 ; C h a nC h a n g e R 3 1 2 f r o m 0 _ 0 4 0 2 t o 3 3 _ 0 4 0 2 ; C h a n g e R 3 5 6 f r o m 1 0 K _ 0 4 0 2g e R 3 5 6 f r o m 1 0 K _ 0 4 0 2g e R 3 5 6 f r o m 1 0 K _ 0 4 0 2g e R 3 5 6 f r o m 1 0 K _ 0 4 0 2
t o 2 . 2 K _ 0 4 0 2 ; I n s t a l l t o 2 . 2 K _ 0 4 0 2 ; I n s t a l l t o 2 . 2 K _ 0 4 0 2 ; I n s t a l l t o 2 . 2 K _ 0 4 0 2 ; I n s t a l l C 2 3 a s 0 .1 U F _ 0 4 0 2C 2 3 a s 0 .1 U F _ 0 4 0 2C 2 3 a s 0 .1 U F _ 0 4 0 2C 2 3 a s 0 .1 U F _ 0 4 0 20 . 20 . 20 . 20 . 2
9 09 09 09 0 3 33 33 33 3 K B CK B CK B CK B C 1 11 11 11 1 / 3 0/ 3 0/ 3 0/ 3 0 H WH WH WH W CCCC h a n g e 3 2 .7 6 8 K H z M a in S o u r c e V e n d o r b e c o m e E P S O Nh a n g e 3 2 .7 6 8 K H z M a in S o u r c e V e n d o r b e c o m e E P S O Nh a n g e 3 2 .7 6 8 K H z M a in S o u r c e V e n d o r b e c o m e E P S O Nh a n g e 3 2 .7 6 8 K H z M a in S o u r c e V e n d o r b e c o m e E P S O N CCCC h a n g e Y 7 f r o m S J 1 0 0 0 0 1 V 0 0 t o S J 1 3 2 P 7 K 2 2 0h a n g e Y 7 f r o m S J 1 0 0 0 0 1 V 0 0 t o S J 1 3 2 P 7 K 2 2 0h a n g e Y 7 f r o m S J 1 0 0 0 0 1 V 0 0 t o S J 1 3 2 P 7 K 2 2 0h a n g e Y 7 f r o m S J 1 0 0 0 0 1 V 0 0 t o S J 1 3 2 P 7 K 2 2 0 0 . 20 . 20 . 20 . 2
3 23 23 23 2 BBBB I O SI O SI O SI O S9 19 19 19 1 1 21 21 21 2 / 0 3/ 0 3/ 0 3/ 0 3 H WH WH WH W C a n c e l E x t . B I O S r e f l a s h d e s i g n b e c a uC a n c e l E x t . B I O S r e f l a s h d e s i g n b e c a uC a n c e l E x t . B I O S r e f l a s h d e s i g n b e c a uC a n c e l E x t . B I O S r e f l a s h d e s i g n b e c a u se o f + 3 V L e r ro es e o f + 3 V L e r ro es e o f + 3 V L e r ro es e o f + 3 V L e r ro e A d dA d dA d dA d d R 2 2 1 ; R e m o v e U 3 0 ,R 2 2 6 ,R 2 2 8 ,C 4 8 9 R 2 2 1 ; R e m o v e U 3 0 ,R 2 2 6 ,R 2 2 8 ,C 4 8 9 R 2 2 1 ; R e m o v e U 3 0 ,R 2 2 6 ,R 2 2 8 ,C 4 8 9 R 2 2 1 ; R e m o v e U 3 0 ,R 2 2 6 ,R 2 2 8 ,C 4 8 9 0 . 20 . 20 . 20 . 2
3 43 43 43 4 LLLL E DE DE DE D9 29 29 29 2 1 21 21 21 2 / 0 3/ 0 3/ 0 3/ 0 3 H WH WH WH W C a n c e lC a n c e lC a n c e lC a n c e l G -S e n s o r I N T 2 L E D f u n c t i o n G -S e n s o r I N T 2 L E D f u n c t i o n G -S e n s o r I N T 2 L E D f u n c t i o n G -S e n s o r I N T 2 L E D f u n c t i o n R e m o v e R e m o v e R e m o v e R e m o v e Q 1 5 6Q 1 5 6Q 1 5 6Q 1 5 6 0 . 20 . 20 . 20 . 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 1.C
HW Changed-List History-2
Custom
50 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
V ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it
I t e mI t e mI t e mI t e m I s s u e DI s s u e DI s s u e DI s s u e D e s c r ip t i o ne s c r ip t i o ne s c r ip t i o ne s c r ip t i o nD a t eD a t eD a t eD a t eR e qR e qR e qR e q u e s tu e s tu e s tu e s t
O w nO w nO w nO w n e re re re r S oS oS oS o lu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io n R e v .R e v .R e v .R e v .P aP aP aP a g e #g e #g e #g e # TTTT it l ei t l ei t l ei t l e
01 19 SB HW Remove R303 from PCICLK3 and add R301 as 0 ohm. 0.3
Add R303 and connect to CLK_PCI_ISO2.
23 Chage net name to PCI_CLK3.
29 Amplifier Change value from 4.7uF to 1uF.
Speaker Speaker right and left channel reverse. Reverse JP20 pin define.
31 Finger Printer Delete R622
32 BIOS ROM Reserve R221
Stuff U30, R228, R226, C489. Change power from +3VALW to +3VL
33 Add pull down resistor R1063.
T/P ON/OFF LED Reverse TP on/off LED
35 Docking Change R572 to 22 ohm and R566 to 2K ohm
35 MDC Change PCB Footprint from 3P3 to 4P0
12/26
12/26
12/26
12/26
12/26
12/26
EC
12/26
12/26
12/26
12/26
12/26
12/26
SB
SB
BIOS ROM
HW
HW
HW
HW
HW
HW
HW
HW
EC
HW
ME
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
0.3
02
03
04
05
06
07
08
09
11
12
13
01/03
HW
HW
HW
0.3
0.3
0.3
Delete R556, R557.
34
R1036
Connect R1046 to JP36.3 and connect R1047 to JP36.9
Switch board
Switch board
Switch board
01/03
01/03 Option Cypress and ENE Cap. board.
Useless
Useless
ME change stand off.
Common design.
19
15
16
17
34
34
34
23
32
Power 0.333 Connect VFIX_EN to EC pin 110.EC 01/0718
14 HW 0.319 SB 01/08 Add pull high resistor R1064.
HW17 0.3Remove reserve circuit for Webcam and Digital MIC.01/08Webcam and Digital MIC
20
19 EMI
0.3
24 SB 01/09 Add reserve cap. C1085~C1087.
25 19 EMI
0.3
SB Fine-tune R302, R303, R308 from 22 ohm to 33 ohm.
26 20 SB EMI
0.3
Add reserve cap. C1088~C1091
27 21 SB DFB Y4 Change Footprint to the same as Y2.
0.3
28 25 LAN DFB Change Y5 Footprint to the same as Y2.
0.3
25 Realtek22 LAN 01/08 Chage part number from SA000026Q00 to SA000026Q10
31 Layout23 USB port 01/08 Swap D11, D12, L51 pin define per layout request.
22 HW21 SB 01/08Change L61, L63, L66, L60, L67, L68, L69 to 0 ohm resistor.Change C528, C543, C566, C504 to MLCC tpye.Change C552 from 22uF to 4.7uF.
0.3
29 26 WWAN EMI Add C738, C739, C740, C750, C751 as 39pF
30 33 EC HW Connect AC_LED# to PQ3
31 35 M/B ME Add screw hole.
32 36 DC-DC HW Remove +1.2V and +3V circuit.
01/09
01/09
01/09
01/09
01/09
01/09
01/09
01/09
0.3
0.3
0.3
0.3
0.3
0.3
33 34 Switch board HW Add R1065 and R1066 for OPP power button board01/10 0.3
34 33 Keyboard connector 01/10 DFB Change Keyboard connector same as JBK00. 0.3
35 34 Lid switch connector 01/10 DFB Change Lid switch connector type. 0.3
36 34 Switch board 01/10 EMI Change R1048 and R1049 from 0 ohm to bead. 0.3
36 06 HDT debug port 01/14 AMD Stuff R26, R28 and R41. 0.3
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 1.C
HW Changed-List History-2
Custom
51 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
V ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it
I t e mI t e mI t e mI t e m I s s u e DI s s u e DI s s u e DI s s u e D e s c r ip t i o ne s c r ip t i o ne s c r ip t i o ne s c r ip t i o nD a t eD a t eD a t eD a t eR e qR e qR e qR e q u e s tu e s tu e s tu e s t
O w nO w nO w nO w n e re re re r S oS oS oS o lu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io n R e v .R e v .R e v .R e v .P aP aP aP a g e #g e #g e #g e # TTTT it l ei t l ei t l ei t l e
37 25 LAN 01/14 HW Reserve Q1056, Q1057, C1077 and Q144. Change PJP605 to R1067. 0.38102E (10/100M 48 pin) can not support DSM function.
38 33 EC 01/14 HW Reserve R544 0.38102E (10/100M 48 pin) can not support DSM function.
39 11 NB 01/15 HW No support daul channel panel. Remove LVDS signal of Channel B. 0.3
40 17 LVDS 01/15 HW Remove LVDS signal of Channel B (remove C1061~C1063) 0.3No support daul channel panel.
41 15 Clock GEN. 01/15 HW Chagne C1074~C1076 to 12pF 0.3To slove noise issue.
42 15 Clock GEN. 01/15 Vendor Clock Gen. spec. update Change R379 to 158 ohm and R380 to 90.9 ohm. 0.3
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 1.C
HW Changed-List History-2
Custom
52 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
V ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it
I t e mI t e mI t e mI t e m I s s u e DI s s u e DI s s u e DI s s u e D e s c r ip t i o ne s c r ip t i o ne s c r ip t i o ne s c r ip t i o nD a t eD a t eD a t eD a t eR e qR e qR e qR e q u e s tu e s tu e s tu e s t
O w nO w nO w nO w n e re re re r S oS oS oS o lu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io n R e v .R e v .R e v .R e v .P aP aP aP a g e #g e #g e #g e # TTTT it l ei t l ei t l ei t l e
01 25 LAN 02/12 HW Reserve D55. 0.4For ESD protect.
HW
HW
HW
HW
3402 S/W board connector 02/12 Reserve R558. 0.4To avoid cap. sensor board abnormal.
03 06 CPU Reserve R59. 0.402/12
06 CPU Change CPU SM BUS from EC2 to EC1. 0.402/1504 Follow Trinity design.
Reserve C16.06 CPU 02/15
06 CPU 02/15
05
06 Change R18 and R19 from 330 to 2.2K ohm.Follow Trinity design.HW
0.4
0.4
07 CPU 02/1507 Reserve C54.HW 0.4
12 NB 02/1508 Remove L96.HW 0.4
12 NB 02/1509 Change L12, L13 from bead to 0 ohm.HW 0.4
13 NB 02/1510 Change L16, L18, L19, L22 from bead to 0 ohm.HW 0.4
13 NB 02/1511 Remove L95.HW 0.4
24 Multibay connector 02/1512 Change JP10 Footprint.ME 0.4
27 Card Reader 02/1513 Change Card Reader LED active status. Reserve Q53 and R454, add R1070.HW 0.4
27 02/1514 Reserve R112 and add pull low resistor R1069.HW 0.4
31 BT 02/1515 Change JP32 Footprint and reverse pin define.ME 0.4
31 BT 02/1516 Saving Power consumption. Change BT power source from +3VALW to +3VS.HW 0.4
33 EC 02/1517 Remove JP34 and reserve R1068 for EC debug.HW 0.4
33 EC 02/1518 To solve can't power on when first plug in AC adapter. Change R1040 from 100K to 10K ohm and connect to +3VL_EC.HW 0.4
Change Card Reader LED active status.Card Reader
19 34 Debug SW 02/15 Remove SW2.HW 0.4
20 34 TP LED 02/15 Add D19 for PR sku.ME 0.4
21 11 NB 02/18 Change R371 from 10K to 300 ohm.HW 0.4
22 11 NB 02/18 Add pull low resistor R1072.HW 0.4
23 19 SB 02/18 Reserve C1085 and R303.HW 0.4
24 21 SB 02/18 To solve can't power on when first plug in AC adapter. Add R1071 and D56 to connect to AC_IN.HW 0.4
25 32 SPI BIOS 02/18 Remove U30, C489, R226, and R228. Stuff R221.HW 0.4
26 34 WL/BT LED control 02/18 Modify circuit WLAN/WWAN/BT LED control.HW 0.4
27 33 EC 02/18 Change R514 and R515 from 10K to 4.7K ohm.HW 0.4Follow Trinity design.
28 35 Screw hole 02/19 ME Add H57.To slove TP on/off button feeling no good when press. 0.4
29 34 02/19 ENE For ENE cap. board. Add LDO circuit (U65, R1073, C1097,C1099, J2). 0.4S/W board connector
For ENE cap. board.30 34 02/19 ENES/W board connector Change R554 pin 1 power plan from +3VL to +3VL_CAP. 0.4
31 For cap. board.34 S/W board connector 02/22 HW Add C1098. 0.4
32 11 To splve CRT rising/falling fail issue.NB 02/22 HW Reserve R62, R63, R64. 0.4
33 16 CRT connector 02/22 HW Change R211, R214 and R217 from 150 ohm to 75 ohm 0.4To splve CRT rising/falling fail issue.
1634 Change C472, C476, C858 from 22pF to 6pF.HW02/22CRT connector 0.4To splve CRT rising/falling fail issue.
35 34 Lid switch connector 02/22 HW To solve short issue for lid switch board. Move C1100 and C1101 from lid swtich board to M/B 0.4
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 1.C
HW Changed-List History-2
Custom
53 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
V ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it
0.4
I t e mI t e mI t e mI t e m I s s u e DI s s u e DI s s u e DI s s u e D e s c r ip t i o ne s c r ip t i o ne s c r ip t i o ne s c r ip t i o nD a t eD a t eD a t eD a t eR e qR e qR e qR e q u e s tu e s tu e s tu e s t
O w nO w nO w nO w n e re re re r S oS oS oS o lu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io n R e v .R e v .R e v .R e v .P aP aP aP a g e #g e #g e #g e # TTTT it l ei t l ei t l ei t l e
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
36 25 LAN 02/22 DFB To solve kink pin to interfere with PCB. Update JRJ45 PCB Footprint.
37 35 Screw hole 02/22 DFB Change H53 and H54 from non PTH to PTH hole.
38 34 02/22 EMI Change R1048 and R1049 from bead to 0 ohm.
39 34 02/22 EMI Reserve R1074/C1102 for ESB_CLK1 and R1075/C1103 for ESB_DAT1.
S/W board connector
S/W board connector
To solve EMI issue for ENE cap. board.
To solve EMI issue for ENE cap. board.
40 33 02/22 EMI Add R1076, C1104 and R1077.EC To solve EMI issue for ENE cap. board.
41 33 EC 02/22 EMI Add C1105.
42 36 DC/DC 02/25 EMI Add C1110~C1117.
43 31 USB connector EMI Add C1109.
44 15 Clock GEN. EMI Add C1106.
For EMI request.
For EMI request.
For EMI request.
02/25
02/25
45 16 CRT Connector EMI Add C1107.02/25 For EMI request.
46 17 LCD Connector 02/25 EMI For EMI request. Add C1108.
47 32 Debug connector 02/26 EMI For EMI request. Add C1118.
48 17 WEBcam LDO 02/26 HW To reduce power consumption in S3 mode. Add PJP6 to connect to +5VS. Stuff R1013 and reserve R1014.
49 34 Lid switch connector 02/26 HW Connect JP40 pin 4 to +3VALW.
50 06 CPU 02/27 POWER Change net name ENTRIP2 to EN0.
51 34 03/03 EMI Change R558 to C1119 (0.1uF)S/W board connector For EMI request.
52 11 NB 03/03 EMI Change C1120 (0.1uF)For EMI request.
53 31 USB connector 03/03 EMI For EMI request. Change C1121 (0.1uF)
54 22 SB 03/03 HW Change L60, L61, L63, L66, L67, L68, L69 from 0 ohm to bead.
55 13 NB 03/03 HW Remove L20, L21 and use PJP604 to replace.
56 35 Docking connector 03/03 DFB Change JDOCK connector Footprint.
57 11 NB 03/03 AMD Add D58 and connect to INV_PWM.
59 33 EC 03/03 AMD Change JDOCK connector Footprint.
To support VariBright feature.
58 11 NB 03/03 AMD Change backlight inform signal (R70, R1072) from LVDS_BLON to LVDS_ENA_BL.To support VariBright feature.
To support VariBright feature.
60 06 CPU 03/04 AMD Reserve R175, R814, C939, Q127 and Q129.
61 19 SB 03/04 AMD Change net name from H_PWRGD to H_PWRGD_SB.
62 20 SB 03/05 EMI Add SSC circuit (U66, R1080, R1081, R1082, R1083, C1122) for HDA_BITCLK.
To solve can not power on when use single core CPU.
For EMI request
64 21 SB 03/06 AMD Change C520 and C521 from 0.01uF to 1000pF.For eSATA GEN1 fail issue.
65 31 eSATA connector 03/06 AMD For eSATA GEN1 fail issue. Change C792 and C793 from 0.01uF to 1000pF.
63 21 SB 03/06 AMD For eSATA GEN1 fail issue. Change C520 and C521 from 0.01uF to 1000pF.
66 17 LCDVCC circuit 03/06 HW To solve LCD power up sequence fail. Change R225 from 470 ohm to 220 ohm.
67 15 Clock GEN. 03/06 HW Add C1123.
68 20 SB 03/06 HW Add D58 and connect to 3/5V_OK.
67 15 WWAN connector 03/06 HW Add power on/off control circuit (Q167, R1087).
67 15 WWAN/WLAN 03/06 HW Add D59 and D60.
To avoid CMOS data lose when shutdown suddenly.
To support wake on WWAN feature.
To avoid leakage power from SB.
For IDT CLOCK GEN.
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 1.C
HW Changed-List History-2
Custom
54 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it
0.4
0.4
0.4
0.4
0.4
0.4
R e v .R e v .R e v .R e v .R e qR e qR e qR e q u e s tu e s tu e s tu e s t
O w nO w nO w nO w n e re re re r
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
I t e mI t e mI t e mI t e m I s s u e DI s s u e DI s s u e DI s s u e D e s c r ip t i o ne s c r ip t i o ne s c r ip t i o ne s c r ip t i o nD a t eD a t eD a t eD a t e S oS oS oS o lu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nP aP aP aP a g e #g e #g e #g e # TTTT it l ei t l ei t l ei t l e
68 20 SB 03/06 HW To solve can not power on if use CPU with single core Stuff R83.
69 11 NB 03/06 HW Add R1085 and R1086.To support VariBright feature.
70 25 LAN 03/06 HW Stuff Q144, R1056, R1057, C1077 and reserve R1067.To reduce power consumption in S3 mode.
71 33 LAN 03/06 HW Stuff R544.To reduce power consumption in S3 mode.
72 18 HDMI 03/07 HW To pass HDMI test. Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.
73 18 HDMI 03/07 HW For EMI request. Reserve 0 ohm and stuff common choke.
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 1.C
HW Changed-List History-2
Custom
55 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it
0.4
0.4
0.4
0.4
0.4
0.4
R e v .R e v .R e v .R e v .R e qR e qR e qR e q u e s tu e s tu e s tu e s t
O w nO w nO w nO w n e re re re r
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
I t e mI t e mI t e mI t e m I s s u e DI s s u e DI s s u e DI s s u e D e s c r ip t i o ne s c r ip t i o ne s c r ip t i o ne s c r ip t i o nD a t eD a t eD a t eD a t e S oS oS oS o lu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nP aP aP aP a g e #g e #g e #g e # TTTT it l ei t l ei t l ei t l e
68 20 SB 03/06 HW To solve can not power on if use CPU with single core Stuff R83.
69 11 NB 03/06 HW Add R1085 and R1086.To support VariBright feature.
70 25 LAN 03/06 HW Stuff Q144, R1056, R1057, C1077 and reserve R1067.To reduce power consumption in S3 mode.
71 33 LAN 03/06 HW Stuff R544.To reduce power consumption in S3 mode.
72 18 HDMI 03/07 HW To pass HDMI test. Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet o f
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4117P 1.C
HW Changed-List History-2
Custom
56 56Monday, March 16, 2009
2007/08/02 2008/08/02Compal Electronics, Inc.
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
1.0
0.4
0.4
0.4
0.4
0.4
0.4
0.4
V ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L istV ers io n C h a n g e L ist ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it ( P . I . R . L ist ) fo r H W C ircu it
0.4
0.4
0.4
0.4
0.4
R e v .R e v .R e v .R e v .R e qR e qR e qR e q u e s tu e s tu e s tu e s t
O w nO w nO w nO w n e re re re r
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
0.4
I t e mI t e mI t e mI t e m I s s u e DI s s u e DI s s u e DI s s u e D e s c r ip t i o ne s c r ip t i o ne s c r ip t i o ne s c r ip t i o nD a t eD a t eD a t eD a t e S oS oS oS o lu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nlu t io n D e s c r ip t io nP aP aP aP a g e #g e #g e #g e # TTTT it l ei t l ei t l ei t l e
68 20 SB 03/06 HW To solve can not power on if use CPU with single core Stuff R83.
69 11 NB 03/06 HW Add R1085 and R1086.To support VariBright feature.
70 25 LAN 03/06 HW Stuff Q144, R1056, R1057, C1077 and reserve R1067.To reduce power consumption in S3 mode.
71 33 LAN 03/06 HW Stuff R544.To reduce power consumption in S3 mode.
72 18 HDMI 03/07 HW To pass HDMI test. Chagnge R315, R307, R173, R297, R172, R304, R139, R141 from 750 ohm to 715 ohm.
33 EC73 HW09/10 R589 R590 use 10k ohm pull highAvoid DOCK_VOL_UP# and DOCK_VOL_down# folating