ECE 340ELECTRONICS I
BJT
APPLICATIONS AND BIASING
SHORTHAND CIRCUIT DIAGRAM
VS
R1
R2
R1
R2
VX
VX
VS
BJT REGIONS OF OPERATION
• CUTOFF
• ACTIVE OR LINEAR
• SATURATION
NPN BJT BIAS CIRCUIT ANALYSIS
VE
VC
VB
RB
RE
Q1
RC
VBB
VCC
+ VBE -
-VCB+ +VCE
-IB
IC
IE
NPN INPUT CIRCUIT ANALYSIS
EB
BEBBB
BE
EEBEBBBB
RR
VVI
II
RIVRIV
1
1
0
NPN OUTPUT CIRCUIT ANALYSIS
EC
CECCC
CE
EECECCCC
RR
VVI
II
RIVRIV
0
NPN DC VOLTAGES
EEE
BBBBB
CCCCC
RIV
RIVV
RIVV
NPN REGIONS OF OPERATION
SATCECEBCEB
BCEB
CEB
VVVVandVVSATURATION
VVandVVLINEARorACTIVE
IVVCUTOFF
,:
:
0:
NPN OPERATING LIMITS
CCMAXCEE
C
CCMAXC
EC
CCCE
EC
C
VVR
R
VI
RR
VV
RR
I
,,
1
NPN OPERATING LIMITS
CCMAXCE
EC
MAXCECCMINCSATCEMINCE
EC
CCCE
EC
C
VV
RR
VVIVV
RR
VV
RR
I
,
,,,,
1
PNP BIAS CIRCUIT ANALYSIS
VC
VEVB
QRB
RC
RE
VBB
VEE
IB
IE
IC
PNP INPUT CIRCUIT ANALYSIS
EB
EBEEB
BE
BBBBEBEEEE
RR
VVI
II
VRIVRIV
1
1
0
PNP OUTPUT CIRCUIT ANALYSIS
EC
ECEEC
CE
CCECEEEE
RR
VVI
II
RIVRIV
0
PNP DC VOLTAGES
CCC
BBBBB
EEEEE
RIV
RIVV
RIVV
PNP REGIONS OF OPERATION
SATECECBCEB
BCEB
CEB
VVVVandVVSATURATION
VVandVVLINEARorACTIVE
IVVCUTOFF
,:
:
0:
PNP OPERATING LIMITS
EEMAXECE
C
EEMAXC
EC
EEEC
EC
C
VVR
R
VI
RR
VV
RR
I
,,
1
PNP OPERATING LIMITS
EEMAXEC
EC
MAXECEEMINCSATECMINEC
EC
EEEC
EC
C
VV
RR
VVIVV
RR
VV
RR
I
,
,,,,
1
SINGLE RESISTOR BIASING CIRCUIT
Q1
RB RC
VCC
ICIB
SINGLE RESISTOR BIASING
• SETS BASE CURRENT
• DIRECTLY CONTROLLED BY SUPPLY VOLTAGE
INPUT KVL EQUATION
B
BECCB
BEBBCC
BEBBCC
R
VVI
VRIV
VRIV
0
0
INPUT LOAD LINE EQUATION
B
CCBEQ
BBQ
B
BECCB
R
VV
RI
R
VVI
1
COLLECTOR CURRENT DEPENDENCE ON VBE
CCB
BEQB
CQ
B
BECCC
B
BECCB
VR
VR
I
R
VVI
R
VVI
OUTPUT KVL EQUATION
CCCB
BEB
CCCE
CCCCCE
CECCCC
RVR
VR
VV
RIVV
VRIV
0
OUTPUT LOAD LINE EQUATION
CB
BEQCCCCCEQ
CCCCCEQ
RR
VVVV
RIVV
RESISTOR DIVIDER BIASING CIRCUIT
Q1
R1
RC
VCC
R2
IC
VOLTAGE DIVIDER BIASING
• PROVIDES TWO METHODS OF DETERMINING BIAS CONDITIONS
• SETS VBE VOLTAGE
• SUPPRESSES DEPENDENCE ON β
DIRECT METHOD
• FIND THEVENIN CIRCUIT AT BASE NODE
• CREATES INPUT CIRCUIT
RESIDUAL CIRCUIT FROM THEVENIN CONVERSION
Q1
RC
VCC
VBB
RB
IB
IC
INPUT EQUATION
B
BEBBB
BEBBBB
R
VVI
VRIV
0
INPUT LOAD LINE EQUATION
B
BBBEQ
BBQ
B
BEBBB
R
VV
RI
R
VVI
1
COLLECTOR CURRENT DEPENDANCE
BBB
BEQB
CQ
B
BEBBC
B
BEBBB
VR
VR
I
R
VVI
R
VVI
OUTPUT EQUATION
C
CECCC
CECCCC
CECCCC
R
VVI
VRIV
VRIV
0
0
OUTPUT EQUATION LOAD LINE
C
CCCEQ
CCQ
C
CECCC
R
VV
RI
R
VVI
1
INDIRECT OR APPROXIMATE METHOD
• ASSUME IB ≈ 0
• VBE IS SET BY VOLTAGE DIVIDER
INPUT EQUATION
T
CCSCC
T
BESCC
CCBE
V
V
RR
RII
V
VII
VRR
RV
21
2
21
2
exp
exp
ITERATIVE METHOD FOR CONVERGENCE
SC
CTBE
T
CCSCC
T
BESCC
CC
BECCBE
I
IVV
V
V
RR
RII
V
VII
V
V
RR
RVandVChoose
ln
expexp
2
21
2
21
21
ITERATIVE METHOD FOR CONVERGENCE
• SUBSTITUTE VBE2 FOR VBE1
• CONTINUE ITERATION UNTIL VBEN+1 ≈ VBEN
VOLTAGE DIVIDER WITH EMITTER DEGENERATION
Q1
RC
VCC
RE
R1
R2
RESULTANT CIRCUIT FROM THEVENIN CONVERSION
Q1
RC
VCC
RE
RB
VBB
INPUT EQUATION
EB
BEBBB
BE
EEBEBBBB
RR
VVI
II
RIVRIV
1
1
0
COLLECTOR CURRENT DEPENDENCE
E
BEBBCBE
BEEB
BBEB
C
EB
BEBBC
R
VVIRR
VRR
VRR
I
RR
VVI
1
11
1
ITERATIVE METHOD
SC
CTBE
E
BEBBC
BECCBB
I
IVV
R
VVI
VChooseVRR
RV
ln2
1
121
2
ITERATIVE METHOD FOR CONVERGENCE
• SUBSTITUTE VBE2 FOR VBE1
• CONTINUE ITERATION UNTIL VBEN+1 ≈ VBEN
SELF-BIASED CIRCUIT
Q1
RC
VCC
RB
IB
INPUT EQUATION
βR
VVI
RβR
VVI
RβR
VVβI
RβR
VVI
VRIRIβVVRIRIV
C
BECCC
CB
BECCC
CB
BECCC
CB
BECCB
BEBBCBCCBEBBCECC
large
11
1