ECE 448 – FPGA and ASIC Design with VHDL
Lecture 19
PicoBlaze Interrupt Interface&
Assembly Code Development
2ECE 448 – FPGA and ASIC Design with VHDL
Required reading
• P. Chu, FPGA Prototyping by VHDL Examples
Chapter 17, PicoBlaze Interrupt Interface
Chapter 15, Assembly Code Development
Program Flow Control Instructions (1)
JUMP AAA
PC <= AAA
JUMP C, AAA
if C=1 then PC <= AAA else PC <= PC + 1
JUMP NC, AAA
if C=0 then PC <= AAA else PC <= PC + 1
JUMP Z, AAA
if Z=1 then PC <= AAA else PC <= PC + 1
JUMP NC, AAA
if Z=0 then PC <= AAA else PC <= PC + 1
Program Flow Control Instructions (2)
CALL AAA
TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA
CALL C | Z , AAA if C | Z =1 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1
CALL NC | NZ , AAA if C | Z =0 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1
Program Flow Control Instructions (3)
RETURN (RET)
PC <= STACK[TOS] + 1; TOS <= TOS - 1
RETURN C | Z (RET C | Z ) if C | Z =1 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1
RETURN NC | NZ (RET NC | NZ ) if C | Z =0 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1
Interrupt Related Instructions
RETURNI ENABLE (RETI ENABLE)
PC <= STACK[TOS] ; TOS <= TOS – 1;
I <= 1; C<= PRESERVED C; Z<= PRESERVED Z
RETURNI DISABLE (RETI DISABLE)
PC <= STACK[TOS] ; TOS <= TOS – 1;
I <= 0; C<= PRESERVED C; Z<= PRESERVED Z
ENABLE INTERRUPT (EINT)
I <=1;
DISABLE INTERRUPT (DINT)
I <=0;
7
Interrupt Flow
ECE 448 – FPGA and ASIC Design with VHDL
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Timing Diagram of an Interrupt Event
ECE 448 – FPGA and ASIC Design with VHDL
9ECE 448 – FPGA and ASIC Design with VHDL
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Interrupt Interface with a Single Event
ECE 448 – FPGA and ASIC Design with VHDL
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Interrupt Interface with Two Requests
ECE 448 – FPGA and ASIC Design with VHDL
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Interrupt Interface with a Timer
ECE 448 – FPGA and ASIC Design with VHDL
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Interrupt Interface with a Timer
ECE 448 – FPGA and ASIC Design with VHDL
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PicoBlaze Development Environments
ECE 448 – FPGA and ASIC Design with VHDL
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KCPSM3 Assembler Files
ECE 448 – FPGA and ASIC Design with VHDL
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Directives of Assembly Language
ECE 448 – FPGA and ASIC Design with VHDL
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Differences between Mnemonics of Instructions
ECE 448 – FPGA and ASIC Design with VHDL
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Differences between Mnemonics of Instructions
ECE 448 – FPGA and ASIC Design with VHDL
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Differences between Programs
ECE 448 – FPGA and ASIC Design with VHDL
ECE 448 – FPGA and ASIC Design with VHDL
Example ofa function in the PicoBlaze
assembly language
Unsigned Multiplication – Basic Equations
x = xi 2i
i=0
k-1
p = a x
p = a x = a xi 2i =
= x0a20 + x1a21 + x2a22 + … + xk-1a2k-1
i=0
k-1
Iterative Algorithm for Unsigned MultiplicationShift/Add Algorithm
p = a x = x0a20 + x1a21 + x2a22 + … + xk-1a2k-1
= (...((0 + x0a2k)/2 + x1a2k)/2 + ... + xk-1a2k)/2 =
k times
=
p(0) = 0
p = p(k)
p(j+1) = (p(j) + xj a 2k) / 2 j=0..k-1
Unsigned Multiplication Computations
pH pL
8 bits
p
xj a
8 bits
pH pL
pH pL0 p(j+1)
2 p(j+1)
p(j)
+ xj a 28
>> 1
PicoBlaze RegisterspH = s5 pL = s6
a = s3
x = s4
+
Unsigned Multiplication Subroutine (1)
;=========================================================; routine: mult_soft; function: 8-bit unsigned multiplier using; shift-and-add algorithm; input register:; s3: multiplicand; s4: multiplier; output register:; s5: upper byte of product; s6: lower byte of product; temp register: i;=========================================================
Unsigned Multiplication Subroutine (2)mult_soft: load s5, 00 ;clear s5 load i, 08 ;initialize loop indexmult_loop: sr0 s4 ;shift lsb to carry jump nc, shift_prod ;lsb is 0 add s5, s3 ;lsb is 1shift_prod: sra s5 ;shift upper byte right, ;carry to MSB, LSB to carry sra s6 ;shift lower byte right, ;lsb of s5 to MSB of s6 sub i, 01 ;dec loop index jump nz, mult_loop ;repeat until i=0 return
Recommended
