Embedded control
European PhD – 2009Microprocessors,
microcontrollers and DSP´sHorácio Fernandes
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PhD
Microprocessors, microcontrollers and DSP´s
• Container for a number of commonly used sub-units
• ALU• DMA• RAM• I/O
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PhD
“Obsolete” devices
• Due to high degree of integration, some high-tech devices can NOT be used on harsh environments– Space (cosmic rays)– High neutron fluency– Radioactive (gamma rays)
• “Bit” errors• Doping contaminants
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PhD
Real-time systems
• Definition of real-time
• Definition of Human time scale
• Real-time control and controllers
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PhD
The control system
Tokamak:
Sensor(Magnetics)
Sensor(Interferometry)
WaveformGenerator #1
Actuator(Power Suplies)
Actuator(Gas Puffing)
WaveformGenerator #2
DATAACQUISITION
SYSTEM
“Trial-and-error” type operation
Hard to get similar discharges, as the plasma is a multivariable complex system
Reprogram of waveforms is normally an empiric and lengthy task•Data acquired needs to be correlated manually against control waveforms
Tokamak
Sensor(Magnetics)
Actuator(PSU)
Sensor(Pressure/
Interferometry)
Actuator(Gas Puffing)
Controller #1(PID)
Controller #2(PID)
Sensor XActuator Y Controller #(PID)
Single-Input Single-Output (SISO) ANALOG controllers
Not easily Re-configurable Hard to Optimize Allows only simple control
schemes (e.g PID) Control of Plasma
Parameters are NOT coupled!
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PhD
System Components
• Sensors• Actuator
s• Control
Unit
Symposium on Plasma Physics and Technology
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PhD
Processing unit
• 8 Analog channels‣ Galvanic
isolated‣ 2
MSample/s‣ 14-bit
• 512 MB SDRAM
• DSP• FPGA• HS Serial
connections• PCI bus
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PhD
System response
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PhD
Induced displacement
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PhD
Sensors & actuators @ JET
Magnetics
R-T Signal Server
R-T Controller
plasma
CXS Ti (R)
MSE pitch (R)
Flux surfaces EQX
Confinement
VUV impurities
Shape & Current Control (PPCC)
ECE Te (R)
q profile
Neutron X-ray etc.
Interferom/Polarim
NBI
ICRH
LHCD
GAS + Pellets
PF Coils
Vis H/D/T
Vis Da, Brem, ELM
Comms network ATM, some analogue
X-ray Ti (0)
LIDAR Ne&Te(R)
Simulink codeEQX kinetic map
TAE / EFCC
Wall Load
Coil Protection
Rob Felton - RTMC Workshop
EP2 VS
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PhD
Computer Architectures
• Harvard architecture (/von Neumann)– RISC(PIC, IBM Power PC) / CISC (80x86) – Clocking, instruction pipelining, 14 bit
instruction set
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PhD
PIC architecture
• Single chip:– CPU– Memory
• RAM• PROM/
EEPROM– oscillator– timers – watchdog – I/O
• Digital• ADCs• Communications
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PhD
PICs
• Code efficiency - 8 bit /Harvard– Conventional Microcontrollers -1 internal
bus (Z80)• Safety coding
– 12, 14 or 24 bit “program memory word”– Jumps to data area impossible
• Instruction Set– 33 instruction (MID range)– Single instruction cycle (=4 clock cycles);
/CALL, GOTO, bit test (BTFSS, INCFSZ)• Speed (2x 386 SX 33MHz)
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PhD
PICs (cont.)
• Static Operation – registers are kept valid during STOP (Sleep – 1uA sink current)
• Current driver– I/O pin: sink 25mA or 100mA (total)– LEDs and triacs
• Several series options– Speed, thermal– Casing (sizes)– I/O, timers, serial comms, A/D– memory
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PhD
DSP
• 40 bit ALU• 2x40 bit accumulators• 1x40 bit bidirectional shifter• Barrel shift -15 bits right, 16
bits left• Integers vs float
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PhD
Terminology
• Microcontroller (sw relevancy) • I/O (external world)• Software (information)
– Bugs– Programming language (ASM, C)
• Hardware– Microprocessor– Memory– Interface and signal conditional circuits – Power supply (digital, analog and
programming ground and shielding)
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PhD
PIC
fam
ily
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PhD
dsPIC30F
• CPU• Data Memory• Program
Memory• DSP Engine• Interrupts
– I/O Ports– Timers– Input Capture Module– Output Compare Module– Quadrature Encoder Interface (QEI)– 10-bit A/D Converter– 12-bit A/D Converter– UART Module– SPITM Module– I2CTM Module– Data Converter Interface (DCI)
Module– CAN Module
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PhD
Harvard
• Independent Buses• Instructions are bigger than1 byte
(Program memory)• Program memory:
– Optimized– Single word instruction per cycle
• In one jump an instruction is always executed
• /von Neuman instructions with several bytes
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PhD
Harvard Architecture
• pipeline – 2 stages instruction execution
• fetch and execution in a single cycle– Each instruction is autonomous
• Every data included • No more program data access• 4 clock per instruction cycle
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PhD
Instruction format
• Word or byte-oriented• Bit-oriented• Literal• DSP operations• Control operations• OpCode
– Variable number of bits– 2^6=64 (app. 35 instructions)
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PhD
Instruction format
dsPIC30FMid-range PICs (14 bit)
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PhD
Memory organization
• Registers and static memory– Work register– Mid->dsPIC– File registers~RAM
• General Purpose Registers (GPRs)• Special Function Registers (SPRs)
– Memory banks• Limitation due to adress bits• Selection bits (avaiable trough STATUS)
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PhD
Special Function Registers
• Base Architecture• Reserved names
– INTCON, TMR0, STATUS• R/W and read only
– Some registers do not exist physically • Some registers are copied among bank
memory– STATUS, FSR, INDF– Including GPR (0x70 a 0x7F)– PORTB (Banks 0 e 2)
• Power ON/Reset
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PhD
General Purpose Registers• User defined
– Wide implementation• Indirect adress
– pointers– Easy incrementation or
decrementation– INDF (0x00) provide adress copy of
FSR• ie changing INDF data at that adress is
changed INDF(=*FSR)• de-referencing Address: 100 102 104 106
Variable: i j k ptrContent: 3 5 -1 102
int i, j, k;int *ptr;
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PhD
Example
• STATUS
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Interruptions and I/O
• Communication between microcontroller and external world– Multi-functional digital output– Communication protocol– ADCs e DACs
• Events monitoring
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PhD
I/O - Diagram port B
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PhD
I/O - Port
• TRISx: Data Direction register
• PORTx: I/O Port register
• LATx: I/O Latch register
• C options in TRISx– Quick & simple– Slow & secure
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PhD
I/O sharing
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PhD
Change Notification (CN) Pins
• Weak pull-up (current source)– Avoiding external resistores
• Originate interruptions– Change in pin states– 24 pins avaiable
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Interruptions
• vs Polling (attention)• Quick response to
events– Peripherics– Driven actions
• After taken action continues previous process
• Maskable/non-maskable
• Variable saving (PC e Stack)
• Quick execution
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PhD
Interruptions (cont.)
• INT Pin Interrupt (external interrupt)
• TMR0 Overflow Interrupt
• PORTB Change Interrupt
• Comparator Change Interrupt
• Parallel Slave Port Interrupt
• USART Interrupts• Receive and Transmit
Interrupt (CAN)
• A/D Conversion Complete Interrupt
• LVD Interrupt• Data EEPROM
Write Complete Interrupt
• Timer Overflow Interrupt
• CCP Interrupt• SSP Interrupt
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PhD
Inte
rrupt
logi
c
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PhD
Interrupt logic
High Priority Logic Block Diagram
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PhD
Interrupt logic
Low Priority Logic Block
Diagram
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PhD
Communications
• Serial – Synchronous
• I2C• SPI
– Asynchronous• RS232, RS485, RS422 (RS232 differential)
– Point to point– Point/multi-point
• USB, SSP• CAN
• Parallel
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PhD
• Start bits - Always 1 bit• Stop bits – 1, 1.5 ou 2 bits• Data bits - 7 ou 8 bits• Parity bits
– none - no error detection– odd or even - error detection required
• 1 bit added to give bit summing odd or even
• CheckSum: redundancy check– CRC (cyclic redundancy check)
Serial Communications
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PhD
HandShaking
• Data Terminal Ready
• Data Set Ready• Clear to Send• Request To
Send• Transmit Data• Receive Data• Ring• Data Carriage
Detected• Ground
Data Terminal Equipment - Data Comunication Equipment
RTS
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PhD
USART/UART
• Universal Synchronous/Asynchronous Receiver Transmiter– Shift register– SYN (0b01000010)
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PhD
I2C
• Two bidirectional “open-drain lines”– Serial Data (SDA)– Clock (SCL)
• “Pull-up” – resistor ~k• Multi-master
– Master node — clock controller– Slave node — all others
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PhD
I2C – typical circuit
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I2C
• 7-bit address space (10-bit addressing) • 16 reserved addresses (max 112
nodes)• Vel.
– Normal - 100 kbit/s (standard mode)– Low-speed mode - 10 kbit/s (até DC)– Fast - 400 kbit/s (Fast mode) or 1 Mbit/s
(Fast mode plus or Fm+), 3.4 Mbit/s High Speed mode
• Max. bus capacity - 400 pF.
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PhD
SPI
• Operation modes– 8-bit and 16-bit Data
Transmission/Reception– Master e Slave– Framed SPI Modes
• Operation: 8-bit vs. 16-bit
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PhD
SPI
• Ideal for single-master/single-slave
• Single-master bus• Do not have slave
acknowledgment !• Full duplex• 1-10Mbit• Dual-Shift register
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PhD
Oscillator
• Oscillator modes ( default clock source)– EC External Clock– ECIO External Clock with IO pin enabled– LP Low Frequency (Power) Crystal– XT Crystal/Resonator– HS High Speed Crystal/Resonator– RC External Resistor/Capacitor– RCIO External Resistor/Capacitor with IO pin
enabled– HS4 High Speed Crystal/Resonator with 4x
frequency PLL multiplier enabled
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PhD
Oscillator modes
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PhD
Oscillator Modes
• Inverter gain (mode)
• Frequency (power)
• Crystal (precision)
• Wake-up (frequency, noise, sleep wake-up)
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PhD
PLL
• Advantages PLL– EMI– SW
program.• Structure
– VCO– Divider– Comparato
r
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PhD
Timers (dsPIC)
• Timer 1
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PhD
Timers (cont.)
• Timer 1– 16 bit (32 kHz – Real-time)– 16-bit Synchronous Counter– 16-bit Asynchronous Counter
• Timer 2/3– 32 bit (ou 2 de 16 bit)– Input Capture– Output Compare/Simple PWM
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PhD
Capture/Compare/PWM
• Capture– Measurements:
• Frequency, • Periods or• Time intervals (var)
• Compare– Internal lap (time)
• PWM– Motor Control– DACs (c/filtro)– Modulated signals (Tones)
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Capture mode
• Logic Diagram– Prescaler
: Low resolution with high accuracy (Tcy).
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PhD
Comparator mode
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PWM
• CCPx pin, PWM up to 10-bit resolution
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PhD
PWM (dwell time)
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PhD
Analog to Digital convertion
• Sucessive aproximations– Bubble sort
(0..1023)• Interactive method
– Convertion speed indetermnined
– Clock dependent
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PhD
ADC dsPIC30x
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PhD
Configuring ADCs
• Configure: Analog pin, reference voltage and digital I/O
• Input channel selection (A/D), clock source and trigger
• Activate A/D module• Configure A/D interrupt (if necessary):
– Clear ADIF bit, Select A/D interrupt priority and Set ADIE bit (use ISR)
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PhD
Sampling (ADCs)• 1. Configure the A/D module:
– Configure analog pins, voltage reference and digital I/O
– Select A/D input channels– Select A/D conversion clock– Select A/D conversion trigger– Turn on A/D module
• 2. Configure A/D interrupt (if required):– Clear ADIF bit– Select A/D interrupt priority– Set ADIE bit (for ISR processing)
• 3. Start sampling.• 4. Wait the required acquisition time.• 5. Trigger acquisition end, start conversion:• 6. Wait for A/D conversion to complete, by either:
– Waiting for the A/D interrupt, or– Waiting for the DONE bit to get set.
• 7. Read A/D result buffer, clear ADIF if required
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ADCs
• Sample rate– Fixed intervals
(Period ajustment)
• Timers w/int.• Maximum SR =
(polling)• Jitter
– clock accuracy• Interrupt cycles
– Trade-off: precision
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PhD
Unions - ADC manipulation
Union Sample{
Unsigned char bytes [2]Signed short word
}
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PhD
Good practices
• Excessive time due to interruptions
• timers to generate sample rate• Check timing with scope or
frequency-meter• SLEEP mode use for ADC Clock
(T_OSC)>1MHz• UNIONs to read ADCs 12bit -> int.