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Embedded System Module 1

Synchronous communication and Iso-synchronous communication: In synchronous a byte or frame of data is txed or rxed at constant time intervals with

uniform phase differences Iso-synchronous communication is special case, where maximum time interval can be

varied Example for synchronous serial communication is frame sent over a LAN, inter-

processor communication in a multi-processor system Synchronous device port bits and the functions are:

1. Synch code bits or frame start and end signaling bits (optional): Few bits separated by a time interval as synch code for frame synchronization. Some cases flag bits are used for synchronization2. Data bits (compulsory): m frame bits or 8 bits transmit, such that each bit is at the line for time T or each frame is at the line for time mT3. Clock bits (mostly not optional): Either a separate clock line or a single line such that the clock information is also embedded with the data bits by an appropriate encoding or modulation

Two characteristics of synchronous communications are:1. Bytes maintain a constant phase difference; does not provide handshaking during the

communication interval2. A clock timing at a certain rate must always there to serially transmit the bits of all

bytes. Methods of synchronous signals:

IO devices, Serial Communication bus and protocols Page 1


Asynchronous Communications: Byte or frame is txed or rxed at variable time intervals Examples are voice data transmission over telephone line, keypad communication,

RS232C communication between the UART devices etc. Two characteristics of asynchronous communication are:

1. Bytes need not maintain a constant phase differences; need handshaking between txr and rxr.

2. A clock must tick at a certain rate to transmit bits of a single byte serially An example with serial communication in asynchronous mode is shown below:

DTE: PC, DCE: ModemDCD- Data carrier detectDSR- Data set readyDTR- Data terminal readyRTS- Request to sendCTS- Clear to sendTxD- Transmit dataRxD- Receive data

Bits and its functions:

Protocols and its applications using synchronous and asynchronous serial port devices:A protocol is a standard adopted, which tells the way in which the bits of a frame

must be sent from a device (or controller or port or processor) to another device or system.

A protocol defines how are the framebits: 1) sent – synchronously or Iso-synchronously or asynchronously and at what rate(s)?



2) preceded by the header bits? 3) How can the transmitting device address defined so that receiving device comes to know the source when receiving data from several sources? 4) How the frame-length defined so that receiving device knows the frame-size in advance? 5) Frame-content specifications –Are the sent frame bits specify the controller device configuring or command or data? 6) Are there succeeding to frame the trailing bits so that receiving device can check the errors, if any in reception before it detects end of the frame ?7) Frame bits minimum and maximum length permitted per frame 8) Line supply and impedances and line-Connectors specifications

Some Protocols are1. HDLC, Frame Relay (for synchronous communication)2. RS232C, UART, X.25, ATM, DSL and ADSL (for asynchronous transmission)3. Ethernet and token ring protocols used in LAN Networks (for networking the physical devices in telecommunication and computer networks)

Some Protocols in embedded network devices 1. Internet appliances application protocols and Web protocols HTTP (hyper text transfer protocol), HTTPS (hyper text transfer protocol Secure Socket Layer), SMTP (Simple Mail Transfer Protocol), POP3 (Post office Protocol version 3), ESMTP (Extended SMTP) (for Bridges and routers)2. File transfer, Boot Protocols in embedded devices network – TELNET (Tele network), FTP (file transfer protocol), DNS (domain network server), IMAP 4 (Internet Message Exchange Application Protocol) and Bootp (Bootstrap protocol).3. Wireless Protocols in embedded devices network – Embedded wireless appliances uses wireless protocols WLAN 802.11, 802.16, Bluetooth, ZigBee, WiFi, WiMax

RS232C/RS485 Communication: Protocol used between DTE COM port and DCE COM port is UART Handshaking signals

Rxr end voltage level is from -3 to -25V for logic 1and +3 to +25V for logic 0, Txr end voltage level is -5 to -15V for logic 1 and _5 to +15V for logic 0. General baud rates are 300, 600,1200, 4800 and 9600 bps Transmission rate is 115.2kbps up to 0.25m and 38.4kbps up to 1m



RS485 now called EIA-485, is a protocol for physical layer in case two wire full or half duplex serial connection between multiple points Transmission in RS485 is at 35Mbps up to 10m and 100kbps up to 1.2km Signals are between +12V and -7V, where logic 1 is +ve and 0 is reverse polarity

UART: Protocol used with RS232C port UART mode is as follows:

1. A line is NRZ state2. Start of serial bits is signaled by 1 to 0 transition (negative edge) for a period

equal to reciprocal of baud rate3. When sending a byte consists of a start bit, 8 data bit, optional parity bit and stop

bit, each during the interval T, thus require 10T or 11T for a byte transmission4. Data bits in certain cases can be 5 or 6or 7 instead of 85. Stop bit can be minimum interval of 1.5T or 2T instead of T in specific cases6. Parity bit is used for parity detection or error detection

UART 16550 includes a 16-byte FIFO buffer used commonly in IBM PC COM port UART communication can be full duplex or half duplex

HDLC protocol: High Level Data Link Control is an International Standard protocol for a data link

network used for synchronous serial data communication between physical devices on a network

Used for linking data from point to point and multiple points Some applications are telecommunication and computer networks Bit-oriented protocol, the total number of bits is not necessarily an integer multiple of

byte or a 32-bit integer Full duplex communication Network device port bits in an HDLC frame format and protocol are:



Sophisticated interfacing features in Devices/Ports:1. Operation voltage level expected for logic 1 is 5V and logic 0 is 0V. In built Schmitt

trigger or external chip for Schmitt trigger provide noise elimination to get the logic level from the different voltage levels

2. The ports have power management. A new technology called Data Gate, in which programmable ON/OFF switch is used for power management. The port is active only when input or output signals are passed to the port.

3. Low voltage operations are there. LVTTL, LVCMOS gates are used at the device ports for 1.5V IO. HSTL and Stub-series Terminated Logic (SSTL) standards are used for high-speed operations

4. Device and bus-impedances during IO should match, else line reflection may occur5. IO device may consist multiple gigabit (622Mbps to 3.125Gbps) transceivers 6. A device for an IO may integrate a SerDes (Serialization and De-serialization) subunit7. Multiple IO standards for IO devices8. IO device may integrate a digital Physical Coding Sublayer9. IO device may integrate an analog unit Physical Media attachment



Timer and Counting Devices: Timer:

Timer is a device, which counts the input at regular interval (δT) using clock pulses at its input.

Has an input pin (or a control bit in control register) for resetting it for all count bits = 0s. Has an output pin (or a status bit in status register) for output when all count bits = 0s

after reaching the maximum value, which also means after timeout or overflow.Counter:

The counts increment on each pulse and store in a register, called count register Output bits (in a count register or at the output pins) for the present counts. The counts multiplied by the interval δT give the time. The (present counts −initial counts) ×δT interval gives the time interval between two

instances when present count bits are read and initial counts were read or set. A device, which counts the input due to the events at irregular or regular intervals. The count gives the number of input events or pulses since it was last read. Has a register to enable read of present counts Functions as timer when counting regular interval clock pulses Has an input pin (or a control bit in control register) for resetting it for all count bits = 0s. Has an output pin (or a status bit in status register) for output when all count bits = 0s

after reaching the maximum value, which also means after timeout or overflow.Timer or Counter Interrupt:

When a timer or counter becomes 0x00or 0x0000 after 0xFF or 0xFFFF(maximum value), it can generate an ‘interrupt’, or an output ‘Time-Out‘ or set a status bit ‘TOV’

Blind counting: Free running counter device with a pre-scaler for clock input Useful to alarm or processor interrupts at preset instances or after preset intervals with

respect to another event from another source.Uses of Timer Device:

1. Real Time Clock2. Initiating an event after a preset delay time3. Initiating an event after a comparison between the preset time with counted value4. Capturing the count-value at the timer on an event5. Finding the time interval between two events6. Wait for a message from a queue or semaphore for a preset time when using an RTOS7. Watch dog timer8. Baud rate for serial communication9. Input pulse counting 10. Scheduling of various tasks11. Time slicing of various tasks12. Time division multiplexing

States of timer:



1. Reset state2. Initial load state3. Present state4. Overflow state5. Overrun state6. Running or stop state7. Finished state8. Reset enabled/disabled state9. Load enabled/disable state10. Auto reload enabled/disabled state11. Service routine execution enable/disable state

A hardware timer control and status signals are shown below:

Control signals:Timer enable, Timer start, Timer stop, Pre-scaling bits, Up-count enable, Down-count enable, Load enable, Timer interrupt enable, Time-out enable

Status flag corresponding to time-out enableForms of timer:

1. Hardware internal timer2. Software timer (SWT)3. User software controlled hardware timer4. RTOS controlled hardware timer5. Timer with periodic time-out events (auto reloading after overflow)6. One shot timer7. Up count action timer8. Down count action timer9. Timer with its overflow status bit, which auto resets after ISR starts running10. Timer with its overflow status bit, which does not auto reset



A software timer control and status flags are:

Serial Bus Communication Protocol

Common types: Inter IC (I2C) Bus Controller Area Network (CAN) Bus Universal Serial Bus (USB)

I 2 C Bus Different ICs can be interconnected by network using I2C bus Three standards:

1) Industrial 100kbps I2C2) 100kbps SM I2C3) 400kbps I2C

Developed by Philips Semiconductors Two line bus: one for serial clock (SCLK) and other is for bidirectional serial data (SDA)



I2C signals during data transfer is shown below:

I2C bus protocol:

1. Start bit2. 7 bit address of slave from master3. R/W bit 4. Acknowledgement bit 5. 8 bit data6. Negative Acknowledgement from master7. Stop bit

I2C bus signals



Disadvantages: 1. Master device take long time to analyze the slave device hardware support or not2. Less number of ICs have this protocol3. Pull-up resistor is needed for master

CAN Bus: Distributed Control Area Network Example - a network of embedded systems in automobile, medical electronics, industrial

plant controllers etc. Three standards:

1. 33kbps CAN2. 110kbps Fault Tolerant CAN3. 1Mbps High Speed CAN

Has a bidirectional serial line Have multimaster and multicast features Employs a twisted pair of max. length 40m connection of 120Ω line impedance at each

CAN controller A fundamental CAN characteristic is the opposite logic state between the bus, and the

driver input and receiver output Normally, a logic-high is associated with a one, and a logic-low is associated with a zero,

but not so on a CAN bus



Line at logic 1 is called Recessive state (differential voltage is 0) Line at logic 0 is called Dominant state (differential voltage is high voltage) Each node has a current driver b/w output and serial line, node sends a logic 0 to line in

its D-state Each node also has a buffer to receive logic from serial line

CAN Protocol: Standard CAN

1. SOF – The single dominant start of frame (SOF) bit marks the start of a message, and is used to synchronize the nodes on a bus after being idle.

2. Identifier-The Standard CAN 11-bit identifier (address of destination device) establishes the priority of the message. The lower the binary value, the higher its priority.

3. RTR – The single Remote Transmission Request (RTR) bit is dominant when information is required from another node. If RTR is 1, the packet is for device at destination address, else the packet is a request for the data from the device

4. IDE – A dominant single identifier extension (IDE) bit means that a standard CAN identifier with no extension is being transmitted.

5. r0 – Reserved bit



6. DLC – The 4-bit data length code (DLC) contains the number of bytes of data being transmitted.

7. Data – Up to 64 bits of application data may be transmitted.8. CRC – The 16-bit (15 bits plus delimiter) cyclic redundancy check (CRC) contains the

checksum (number of bits transmitted) of the preceding application data for error detection.9. ACK – Two bits, and first is ACK slot. The sender send it as 1 and rxr send back 0 when it

detectes error. Second bit is delimiter, it signals the end of ACK feild10.EOF – This end-of-frame (EOF), 7-bit field marks the end of a CAN frame (message) and

disables bit-stuffing, indicating a stuffing error 11. IFS – This 7-bit inter frame space (IFS) contains the time required by the controller to move a correctly received frame to its proper position in a message buffer area.

USB : Bus b/w host system and number of interconnected peripherals Maximum 127 devices can connect to a host Serial txn and rxn b/w host and serial devices at a rate ranges from 1.5Mbps to 480Mbps USB host includes controller for the function as bus master can connect flash, digital

cameras, printer, mice, PocketPC, video games etc Three standards:

1. USB 1.1 (a low speed 1.5Mbps 3m channel with a high speed 12Mbps, 25m channel)2. USB 2.0 (high speed 480Mbps 25m channel)3. Wireless USB (high speed 480Mbps 3m)

USB device can be ‘hot swapped’, that is the devices can be plugged and unplugged without rebooting the host or turning off the device

USB device can either be bus-powered or self-powered USB host connects to devices using USB driving software and host controller connected

to a root hub. A hub is one that connects to other nodes or hubs. It is a tree like topology

USB cable has four wires, one for +5V, two for twisted pairs and one for ground There are termination impedances at each end as per the speed of the device



EMI shielded are used for high speed USB cables NRZ data signals and clock is encoded as synch data Four types data transfer:

1. Controlled data transfer2. Bulk data transfer3. Interrupt driven data transfer4. Iso-synchronous data transfer

USB is polled bus; host controller ckt regularly polls the presence of a device as scheduled by software

Each USB transaction consists of a Token Packet : Consists field for type, direction, USB device address and device

end-point number An optional Data Packet, (Containing the payload) A status Packet (Used to acknowledge transactions and to provide a means of

error correction)Common USB Packet Fields

USB packets consist of the following fields,Sync: All packets must start with a sync field. The sync field is 8 bits long at low and full

speed or 32 bits long for high speed and is used to synchronize the clock of the receiver with that of the transmitter. The last two bits indicate where the PID fields starts.

PID: PID stands for Packet ID. This field is used to identify the type of packet that is being sent.

ADDR: The address field specifies which device the packet is designated for. Being 7 bits in length allows for 127 devices to be supported. Address 0 is not valid.

ENDP: The endpoint field is made up of 4 bits, allowing 16 possible endpoints. Low speed devices, however can only have 2 additional endpoints on top of the default pipe. (4 endpoints max)

CRC: Cyclic Redundancy Checks are performed on the data within the packet payload. All token packets have a 5 bit CRC while data packets have a 16 bit CRC.

EOP: End of packet. Signaled by a Single Ended Zero (SE0) for approximately 2 bit times
