INTERNATIONAL TECHNOLOGY ROADMAP
FOR SEMICONDUCTORS
2011 EDITION
EMERGING RESEARCH DEVICES
THE ITRS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY
COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT.
The International Technology Roadmap for Semiconductors: 2011
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The International Technology Roadmap for Semiconductors: 2011
TABLE OF CONTENTS
1. ã¹ã³ãŒã ........................................................................................................................1 2.å°é£ãªèª²é¡ .........................................................................................................................2
2.1. ã¯ããã« .........................................................................................................................2 2.2 ããã€ã¹æè¡ .........................................................................................................................4 2.3 æææè¡ .........................................................................................................................5
3. ããæ å ±åŠçã®åé¡ïŒNano-information Processing TaxonomyïŒ ..........................................5 4. æ°æ¢æ±ããã€ã¹ïŒEmerging Research DevicesïŒ ....................................................................6
4.1. ã¡ã¢ãªã®åé¡ãšããã€ã¹ïŒMemory Taxonomy and DevicesïŒ...........................................6 4.2. ããžãã¯åã³ä»£æ¿æ å ±åŠçããã€ã¹ .............................................................17 4.3. MORE-THAN-MOORE DEVICES .................................................................32
5. æ°æ¢æ±ã¢ãŒããã¯ãã£ïŒEmerging Research ArchitecturesïŒ ..................................................36 5.1. åŸæ¥æŒç®ã«ãããæ°æ¢æ±ã¡ã¢ãªã¢ãŒããã¯ãã£ïŒEmerging Memory Architectures in âConventionalâ ComputingïŒ............................................................................36 5.2. Evolved Architectures Exploiting Emerging Research Memory Devices .........................40 5.3. ã¢ãŒãã£ãã¯ã¢ãŒããã¯ãã£...........................................................................................41
6. æ°æ¢ç©¶ã¡ã¢ãªã»è«çããã€ã¹âéèŠãªè©äŸ¡..............................................................................46 6.1 ã¯ããã« .......................................................................................................................46 6.2 CMOSæè¡ã®å®éçããžãã¯ãã³ãããŒã¯ ......................................................................46 6.3 俯ç°ã«åºã¥ãBEYOND CMOSã¡ã¢ãªåã³ããžãã¯æè¡ã®ãã³ãããŒã¯ .........................51 6.4 ã¡ã¢ãªãšããžãã¯ããã€ã¹ã®æœåšçæ§èœã®è©äŸ¡ ................................................................53 6.5 éçºå éã«åããŠæ³šç®ãããã¡ã¢ãªãšããžãã¯æè¡ ..........................................................59
7.æ å ±åŠç .......................................................................................................................... 61
7.1 ã¯ããã« ..................................................................................................................... 61
7.2 å°é£ãªèª²é¡ 61
LIST OF FIGURES
Figure ERD1 Relationship among More Moore, More-than-Moore, and Beyond CMOS......2 Figure ERD2 A Taxonomy for Emerging Research Information Processing Devices (The
technology entries are representative but not comprehensive.) ......................6 Figure ERD3 Schematic layout of the excitonic field-effect transistor (ExFET)........................1 Figure ERD4 A Taxonomy for Emerging Research Information Processing Devices (The
technology entries are representative but not comprehensive.) ....................33 Figure ERD5 Median delay, energy, and area of proposed devices, normalized to ITRS 15-
nm CMOS. (Based on principal investigatorsâ data; from Rev. .....................48
The International Technology Roadmap for Semiconductors: 2011
Figure ERD6 Energy versus delay of a NAND2 gate in various post-CMOS technologies. Projections for both high-performance and low-power 15nm CMOS are included as reference. All values are a snapshot in time, and will change as work continues. (Based on principal investigatorsâ data; from Ref. ).....................49
Figure ERD7 Inverter energy and delay and interconnect delay (*characteristic of transport over 10um) for various beyond-CMOS technologies. Projections for both high-performance and low-power 15nm CMOS included as reference. Solid dots indicate the switch is intrinsically non-volatile. All values are a snapshot in time, and will change as work continues. (Based on principal investigatorsâ data) 49
Figure ERD8 Transport impact on switch delay, size, and area of control. Circle size is logarithmically proportional to physically accessible area in one delay. Projections for 15nm CMOS included as reference. (Based on principal investigatorsâ data; from Ref. )......................................................................50
Figure ERD10 a-f Technology Performance Evaluation for a) Redox Resistive Memory, b) Ferroelectric Memory, c) Nanomechanical Memory, d) Mott Memory e) Macromolecular Memory, and f) Molecular Memory. ....................................58
Figure ERD 11 a-f Technology Performance Evaluation for a) Nanowire MOSFETs, b) CNT MOSFETs, c) GaInSb and GaSbP p-channel MOSFETs, d) Ge and InP n-channel MOSFETs, e) GNR MOSFETs, and f) Tunnel MOSFETs ...............58
Figure ERD 12a-d Technology Performance Evaluation for a) I MOSFET, b) Ferroelectric Negative Cg MOSFET, c) Atomic Switch, and d) Mott Transistor. ...............................58
Figure ERD 12e-g Technology Performance Evaluation for e) Spin FET and Spin MOSFET, f) NEMS Device, and g) P/N Junction Device...................................................58
Figure ERD13a-f Technology Performance Evaluation for a) BiSFET, b) Exciton FET, c) Spin Torque Majority Gate, d) All Spin Logic Device, e) Spin Wave Device, and f) Nanomagnetic Logic Device. .........................................................................58
LIST OF TABLES
Table ERD1 Emerging Research Devices Difficult Challenges ..............................................3 Table ERD2 Memory Taxonomy.............................................................................................6 Table ERD3 Current Baseline and Prototypical Memory Technologies..................................7 Table ERD4 Transition Table for Emerging Research Memory Devices ................................7 Table ERD5 Emerging Research Memory DevicesâDemonstrated and Projected Parameters
7 Table ERD6 Experimental Demonstrations of Vertical Transistors In Memory Arrays ...........8 Table ERD7 Benchmark Select Device Parameters...............................................................8 Table ERD8 Experimentally Demonstrated 2-Terminal Select Devices .................................8 Table ERD9 Target device and System Specifications for SCM ...........................................8 Table ERD10 Potential of the Current Prototypical and Emerging Research Memory Candidates
for SCM Applications....................................................................................................................8
The International Technology Roadmap for Semiconductors: 2011
Table ERD11 Transition Table for Emerging Research Logic Devices .....................................18 Table ERD12a MOSFETS: Extending MOSFETs to the End of the Roadmap ...........................18 Table ERD12b Charge based Beyond CMOS: Non-Conventional FETs and other Charge-based
Information Carrier Devices........................................................................................................18 Table ERD12c Alternative Information Processing Devices ........................................................18 Table ERD13 Anticipated Important Properties of Emerging Memories as driven by Application
Need 40 Table ERD14 Likely desirable properties of M (Memory) type and S (Storage) type Storage
Class Memories 40 Table ERD15 Current Research Directions for Employing Emerging Research Memory Devices
to Enhance Logic........................................................................................................................40 Table ERD16 Applications and Development of Neuromorphic System ................................41 Table ERD17 Noise-Driven Neural Processing and its Possible Applications........................42 Table ERD18 Potential Evaluation for Emerging Reseach Memory Devices .........................54 Table ERD19 Potential Evaluation - Extending MOSFETS to the end of the Roadmap.........54 Table ERD20 Potential Evaluation - Non-conventional FETs and other Charge-based Devices54 Table ERD21 Potential Evaluation: Non-FET, Non-Charge-Based "Beyond CMOS" Devices54
The International Technology Roadmap for Semiconductors: 2011
Emarging Research Devices 1
æ°æ¢æ±ããã€ã¹ïŒEMERGING RESEARCH DEVICESïŒ
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The International Technology Roadmap for Semiconductors: 2011
2 Emarging Research Devices
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The International Technology Roadmap for Semiconductors: 2011
Emarging Research Devices 3
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Table ERD1 Emerging Research Devices Difficult ChallengesDifficult Challenges â 2018â 2026 Summary of Issues and opportunities
SRAM and FLASH scaling in 2D will reach definite limits within the next several years (see PIDS Difficult Challenges). These limits are driving the need for new memory technologies to replace SRAM and possibly FLASH memories by 2018.
Identify the most promising technical approach(es) to obtain electrically accessible, high-speed, high-density, low-power, (preferably) embeddable volatile and non-volatile RAM
Scale high-speed, dense, embeddable, volatile, and non-volatile memory technologies to replace SRAM and / or FLASH for manufacture by 2018.
The desired material/device properties must be maintained through and after high temperature and corrosive chemical processing. Reliability issues should be identified & addressed early in the technology development
Develop 2 nd generation new materials to replace silicon (or InGaAs, Ge) as an alternate channel and source/drain to increase the saturation velocity and to further reduce Vdd and power dissipation in MOSFETs while minimizing leakage currents for technology scaled to 2018 and beyond.
Develop means to control the variability of critical dimensions and statistical distributions (e.g., gate length, channel thickness, S/D doping concentrations, etc.)
Scale CMOS to and beyond 2018 - 2026
Accommodate the heterogeneous integration of dissimilar materials. The desired material/device properties must be maintained through and after high temperature and corrosive chemical processing
Reliability issues should be identified & addressed early in this development.
Extend ultimately scaled CMOS as a platform technology into new domains of application.
Discover and reduce to practice new device technologies and primitive-level architecture to provide special purpose optimized functional cores (e.g., accelerator functions) heterogeneously integrable with CMOS.
Invent and reduce to practice a new information processing technology eventually to replace CMOS
Ensure that a new information processing technology is compatible with the new memory technology discussed above; i.e., the logic technology must also provide the access function in a new memory technology.
A new information processing technology must also be compatible with a systems architecture that can fully utilize the new device. A new non-binary data representation and non-Boolean logic may be required to employ a new device for information processing. These requirements will drive the need for a new systems architecture.
Bridge the gap that exists between materials behaviors and device functions.
Accommodate the heterogeneous integration of dissimilar materials
Continue functional scaling of information processing technology substantially beyond that attainable by ultimately scaled CMOS.
Reliability issues should be identified & addressed early in the technology development
Invent and reduce to practice long term alternative solutions to technologies that address existing MtM ITRS topical entries currently in wireless/analog and eventually in power devices, MEMS, image sensors, etc.
The industry is now faced with the increasing importance of a new trend, âMore than Mooreâ (MtM), where added value to devices is provided by incorporating functionalities that do not necessarily scale according to "Moore's Lawâ.
Heterogeneous integration of digital and non-digital functionalities into compact systems that will be the key driver for a wide variety of application fields, such as communication, automotive, environmental control, healthcare, security and entertainment.
The International Technology Roadmap for Semiconductors: 2011
4 Emarging Research Devices
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6 Emarging Research Devices
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4. æ°æ¢æ±ããã€ã¹ïŒEMERGING RESEARCH DEVICESïŒ
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The International Technology Roadmap for Semiconductors: 2011
Emarging Research Devices 7
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8 Emarging Research Devices
Table ERD6 Experimental Demonstrations of Vertical Transistors In Memory ArraysTable ERD7 Benchmark Select Device Parameters
Table ERD8 Experimentally Demonstrated 2-Terminal Select Devices
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Emarging Research Devices 9
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Emarging Research Devices 15
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16 Emarging Research Devices
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Emarging Research Devices 17
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è°è«ããã
4.2. ããžãã¯åã³ä»£æ¿æ å ±åŠçããã€ã¹
ERD ç« ã®ç®çã®ç¬¬äžã¯ãçºå±ãããæ°ããæ å ±åŠçããã€ã¹ãã·ã¹ãã ãã¢ãŒããã¯ãã£ããé·æçãªæœ
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ããæ¬ç¯ã®äœè£ã¯ 2009 幎çãšå€ãã£ãŠããªãã2009 幎çãã 2011 幎çã®é㧠Table ERD12 ã«å ¥ã£ãŠ
ããããããã¯åºãŠè¡ã£ãæè¡ã瀺ãããé·ç§»è¡šãTable ERD11 ãããã2013 幎çã«å ¥ãã§ãããæ°ããæ
è¡ã®ä¿¯ç°ãè¡ããæ¬ç¯ã§ã¯ 18 ã®æè¡åè£ã 3 ã€ã®è¡šã«åé¡ããŠããããããã®è¡šã®è¡šé¡ã¯æ¬¡ã®éãã§ã
ããERD12a ãMOSFET: ããŒããããã®çµçã«åãã MOSFET ã®å»¶é·ããERD12b ãé»è·ããŒã¹ã®
Beyond CMOS: æ°èŠ FET ãšãã®ä»ã®é»è·ãæ å ±åªäœãšããããã€ã¹ãããã㊠ERD12c ãé»è·ãé»çå¹
æãçšããªãâBeyond CMOSâããã€ã¹ãã§ãããããã 3 ã€ã®è¡šã®è¡šé¡ã¯ããããã®å 容ãåæ ããŠããã
åã®è¡šã¯çŸç¶ã® MOSFET ã®å»¶é·ã匷åããããã®ã§ããããããã¯ãã¹ãŠé»è·ã«åºã¥ãããã€ã¹ã§ã
MOSFET ãšããŠã®æ©èœãå©çšãããã®ã§ãããERD12b ã«ã¯ãé»åã®ç§»åã䌎ããã®ã®ãéåååŠçãã³
ãã«çŸè±¡ãã¯ãŒãã³ã»ãããã±ãŒããªã©ã® MOSFET ãšã¯æ¬è³ªçã«ç°ãªã£ãã¹ã€ããã³ã°çŸè±¡ã䌎ããã®ãæ
ãããERD12c ã¯é»è·ä»¥å€ã®æ å ±åªäœã«åºã¥ããŠããŠãã¹ãã³æ³¢çžäºäœçšãç£æ°äº€æçµåå¹æãªã©ãçš
ãããã®ãæãããERD12a, ERD12b åã³ ERD12c ã®é ç®ã¯ãé²æã¯ããã©å°å ¥ãå¯èœã«ãªãææãšã
ãç¹ã§ã¯ãŸã ãŸã é ããERD12c ã®å 容ã«ã€ããŠã¯ç±³åœã® Nanoelectronics Research Initiative ã«å€§ããª
圱é¿ãåããŠãããããã¯ãèšç®ã«ãããŠé»è·ä»¥å€ã®ç¶æ å€æ°ãçšããããã€ã¹ã«çç®ããããã§ããã
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èŠã®ããã€ã¹ãéããããšãåºæ¥ãããããã¯ãã¹ãŠæ§ã ãªç¹æ®ç®çã®æ©èœã«åããŠãããããŸã çæ³ã
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The International Technology Roadmap for Semiconductors: 2011
18 Emarging Research Devices
Table ERD11 Transition Table for Emerging Research Logic Devices
Table ERD12a MOSFETS: Extending MOSFETs to the End of the Roadmap
Table ERD12b Charge based Beyond CMOS: Non-Conventional FETs and other Charge-based Information Carrier Devices
Table ERD12c Alternative Information Processing Devices
4.2.1. ããžãã¯ããã€ã¹
4.2.1.1. MOSFET: ããŒããããã®çµçã«åãã MOSFET ã®å»¶é·
4.2.1.1.1 ã«ãŒãã³ãããã¥ãŒã FET (Field Effect Transistor)
ã«ãŒãã³ãããã¥ãŒã FET(Field Effect Transistor)ã®å©ç¹ãšã㊠ãè¯ãèšåãããŠãããã®ã¯ãïŒã€ã¯é«
ããã£ãªã¢ç§»å床ã§ãããããïŒã€ã¯ãµã©ãŠã³ãã²ãŒãæ§é ã®æ¡çšã«ãããµãã¹ã¬ãã·ã§ã«ãã¹ããŒãã® å°å
ïŒããªãã¡çãã£ãã«å¹æ å°åïŒãžã®æåŸ ã§ãããããããªããããããéæããããã«ã¯ä»¥äžã®ãããª
ããã€ãã®èª²é¡ãããïŒ1)ãã³ãã®ã£ãããšãã«ã®ãŒãå¶åŸ¡ã§ããããšã2)ãããã¥ãŒããææã®äœçœ®ãæ¹å
ã«çœ®ãããšã3)ãããã¥ãŒãã®å±€æ°ãå¶åŸ¡ããããšã4)é»è·ãã£ãªã¢ã®ã¿ã€ããšæ¿åºŠãå¶åŸ¡ããããšã5)ã²ãŒã
絶çžèã®å ç©ã6)äœæµæã³ã³ã¿ã¯ãã®åœ¢æã
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ãŠãç¶æã§ããããšã瀺ãããããš92ã2)ãã£ãã«é· 15nmã®ããã€ã¹ãäœè£œããïŒãã£ãã«ãããã®ãã©ã³ã¹ã³
ã³ãã¯ã¿ã³ã¹ãšã㊠40µSãåŸãããšã3)Extrinsicåã³Intrinsicãªé®æåšæ³¢æ°(fT)ãšããŠãããã 15GHzã
80GHzã瀺ãFETãåŸãããš93ã4)ã€ãããªãŠã ãé»æ¥µãšããŠçšããŠnåFETãäœè£œãã2.06psã®ã²ãŒãé 延æ
éã®äºæ³å€ãåŸãããš94ã5)å®å šã«CMOSã«èŠªåæ§ãããææã®ã¿ã䜿ããVDD = 2Vã«ãã㊠0.67Vã®
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äžèšã«å ããããã€ãã®æ®ã課é¡ã«ã€ããŠç¶ç¶çãªé²å±ããã£ãããã®ïŒã€ã¯ååŠçææ³ã«ããå¶åŸ¡ãã
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The International Technology Roadmap for Semiconductors: 2011
Emarging Research Devices 19
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4.2.1.1.2. ã°ã©ãã§ã³ãããªãã³ FET
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å¹æã«é¢ããåããŠã®å ±å以æ¥101ãããã ïŒããã¯ïŒã²ãŒã102ããããã²ãŒã103,104,105ããã¥ã¢ã«ã²ãŒã106,107ã
ãµã€ãã²ãŒã 108ã䜿ã£ãFETãå¥é¢ã°ã©ãã§ã³ 109,110ããšãã¿ãã·ã£ã«ã°ã©ãã§ã³ 111,112,113ãCVDã°ã©ãã§ã³114,115ãçšããŠå®çŸãããŠããã
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ããå¥é¢ãããã°ã©ãã§ã³ã¯ãŸã ãé«ã移å床ã瀺ãã116,117,118ã倧éçç£ã«ã¯åããªããSiO2 ã絶çž
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The International Technology Roadmap for Semiconductors: 2011
20 Emarging Research Devices
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4.2.1.1.3. ããã¯ã€ã€ FET (Nanowire Field-Effect Transistors: NWFET)
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Emarging Research Devices 21
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Emarging Research Devices 23
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32 Emarging Research Devices
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Emarging Research Devices 33
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Table ERD13 Anticipated Important Properties of Emerging Memories as driven by Application Need
Table ERD14 Likely desirable properties of M (Memory) type and S (Storage) type Storage Class
Memories
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Table ERD15 Current Research Directions for Employing Emerging Research Memory Devices to Enhance Logic
The International Technology Roadmap for Semiconductors: 2011
Emarging Research Devices 41
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The International Technology Roadmap for Semiconductors: 2011
42 Emarging Research Devices
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The International Technology Roadmap for Semiconductors: 2011
Emarging Research Devices 49
Figure ERD6 Energy versus delay of a NAND2 gate in various post-CMOS technologies. Projections for both high-performance and low-power 15nm CMOS are included as reference. All values are a
snapshot in time, and will change as work continues. (Based on principal investigatorsâ data; from Ref. 2 )
Figure ERD7 Inverter energy and delay and interconnect delay (*characteristic of transport over 10um) for various beyond-CMOS technologies. Projections for both high-performance and low-power
15nm CMOS included as reference. Solid dots indicate the switch is intrinsically non-volatile. All
The International Technology Roadmap for Semiconductors: 2011
50 Emarging Research Devices
values are a snapshot in time, and will change as work continues. (Based on principal investigatorsâ data)
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Emarging Research Devices 51
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52 Emarging Research Devices
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The International Technology Roadmap for Semiconductors: 2011
Emarging Research Devices 53
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Relevance Criteria for each Technology Entry
Maximum Overall Potential Assessment (OPA) = 24
Minimum Overall Potential Assessment (OPA) = 8
Overall Potential Assessment for Technology Entries Potential for the Technology Entry is projected to be significantly better than silicon CMOS or baseline memory (compared using the Technology Relevance Criteria) (OPA >20)
Potential
Potential for the Technology Entry is projected to be slightly better than silicon CMOS or baseline memory (compared using the Technology Relevance Criteria) (OPA >16â20)
Potential
Potential for the Technology Entry is projected to be significantly (2x) less than silicon CMOS or baseline memory (compared using the Technology Relevance Criteria) (OPA < 16)
Potential
The International Technology Roadmap for Semiconductors: 2011
54 Emarging Research Devices
6.4.2 çµæ è¡š ERD18ãERD21 ã« ERD ã®è©äŸ¡çµæãèŠçŽããŠãããè²ã®è¡šç€ºã¯ãäžèšãæè¡å°å ¥ã®ããã®å šè¬ç
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Table ERD18 Potential Evaluation for Emerging Reseach Memory Devices
Table ERD19 Potential Evaluation - Extending MOSFETS to the end of the Roadmap
Table ERD20 Potential Evaluation - Non-conventional FETs and other Charge-based Devices
Table ERD21 Potential Evaluation: Non-FET, Non-Charge-Based "Beyond CMOS" Devices
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Emarging Research Devices 55
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The International Technology Roadmap for Semiconductors: 2011
56 Emarging Research Devices
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Emarging Research Devices 57
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58 Emarging Research Devices
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Figure ERD 12a-d Technology Performance Evaluation for a) I MOSFET, b) Ferroelectric Negative Cg MOSFET, c) Atomic Switch, and d) Mott Transistor.
Figure ERD 12e-g Technology Performance Evaluation for e) Spin FET and Spin MOSFET, f) NEMS Device, and g) P/N Junction Device.
Figure ERD13a-f Technology Performance Evaluation for a) BiSFET, b) Exciton FET, c) Spin Torque Majority Gate, d) All Spin Logic Device, e) Spin Wave Device, and f) Nanomagnetic Logic Device.
The International Technology Roadmap for Semiconductors: 2011
Emarging Research Devices 59
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The International Technology Roadmap for Semiconductors: 2011
60 Emarging Research Devices
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Emarging Research Devices 61
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The International Technology Roadmap for Semiconductors: 2011
62 Emarging Research Devices
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ç®çã®ããã«ãCMOS 以å€ã®æ°èŠããã€ã¹ã«ãå©çšã§ããã 1 K. Bernstein, R.K. Cavin, W. Porod, A. Seabaugh, and J. Welser, âDevice and Architecture Outlook for Beyond CMOS Switches,â
Proceedings of the IEEE Special Issue - Nanoelectronics Research: Beyond CMOS Information Processing, Volume 98, Issue 12, Dec
2010, pp. 2169-2184. 2 J. Welser and K. Bernstein, âChallenges for Post-CMOS Devices & Architectures,â IEEE Device Research Conference Technical Digest,
Santa Barbara, CA, Jun 2011, pp. 183-186. 3 K. Bernstein, R.K. Cavin, W. Porod, A. Seabaugh, and J. Welser, âDevice and Architecture Outlook for Beyond CMOS Switches,â
Proceedings of the IEEE Special Issue - Nanoelectronics Research: Beyond CMOS Information Processing, Volume 98, Issue 12, Dec
2010, pp. 2169-2184.
The International Technology Roadmap for Semiconductors: 2011