Embedded Design with FPGAs and ARM Cortex-M1Dominic Pajak, ARMJean Labrosse, MicriumMike Thompson, Actel
April 2008 – Embedded Systems Conference
© 2008 Actel 2April 2008Embedded Design in FPGA with Cortex-M1
AgendaARM Cortex-M1
Dominic Pajak
Micrium uC/OS-IIJean Labrosse
Using Cortex-M1 in FPGAMike Thompson
© 2008 Actel 3April 2008Embedded Design in FPGA with Cortex-M1
Embedded systems in FPGAFPGAs are available at increasingly low-costRapid development of time-to-market critical designsInitial product runs, design entry, prototypingLong-life applications – no risk of obsolescenceNetworking, Consumer, Industrial/Auto, Aero, Portable apps
Reduce risk, costs and time-to-market combined with ARMARM Cortex-M1 optimised for FPGA implementationARM proven in billions of ARM Powered devices Familiar, high-quality development tools and OS supportMigration path to ASIC through software compatibility
Available in Actel Fusion, Igloo, and ProASIC3 devices
ARM in FPGA
© 2008 Actel 4April 2008Embedded Design in FPGA with Cortex-M1
Common architecture across the performance spectrum
Thumb®-2 blended 16/32-bit ISA Performance and efficiency
ARM Cortex A Series - Applications CPUs focused on the execution of complex OS and user applications
ARM Cortex R Series - Deeply embedded processors focused on real-timeenvironments
ARM Cortex M Series - Microcontrollercores focused on very area sensitive, deterministic, interrupt driven environmentsCortex-M1 is upward compatible with Cortex family
ARM Cortex processor family
Cortex-M3
Cortex-R4
Cortex™-A8
Cortex-R4F
Cortex-M1
© 2008 Actel 5April 2008Embedded Design in FPGA with Cortex-M1
ARM Cortex-M1 is easy to useA standard processor architecture for all FPGAs
Enabling code and tool reuseDramatically lowers the cost of migrating across FPGAsUsers can seamlessly migrate to leading edge FPGA device
Designed to simplify software development Familiar, high-quality development tools and OS
e.g. RealView, Keil, GNU….Everything can be written in C
No need for assembler for vector table or interrupt handlers
Compatibility roadmap to ASIC/ASSP and MCUObject code upwards compatibility with Cortex processors in ASICCompatible with legacy Thumb code from ARM7TDMI onwards
© 2008 Actel 6April 2008Embedded Design in FPGA with Cortex-M1
ARM Cortex-M1 processor featuresA 3-stage, 32-bit RISC processor
Highly configurable to enable design trade-offsRetains the same programmers model for software simplicity
Tightly Coupled MemoriesInternal FPGA block RAM used as single-cycle access memoryITCM, DTCM configurable from 0k to 1024kBytes
Configurable debugJTAG or reduced pin-count SWD interfaceFull – 2 watchpoints, 4 breakpointsSmall – 1 watchpoint, 2 breakpointsNone – removable for cost reduction and security
© 2008 Actel 7April 2008Embedded Design in FPGA with Cortex-M1
ARM Cortex-M1 processor features (2)
Integrated Interrupt ControllerFast interrupt responseConfigurable 1, 8, 16, 32Software programmed priority levels (1-4)Non-Maskable Interrupt
AMBA AHB-lite 32-bit bus interfaceConnection to external memory and peripherals
Big or little endianSynthesis time configurable
© 2008 Actel 8April 2008Embedded Design in FPGA with Cortex-M1
ARM Cortex-M1 implements a lightweight Thumb-2 profileProcessor executes blended 16-bit, 32-bit in one execution mode
Can execute existing Thumb codeFor example Thumb code from ARM7TDMI, ARM926EJ-S onwardsMost microcontroller applications use predominately Thumb codeUpwards compatible with Cortex processors
Migration to ASIC/ASSP & MCU at all performance points
ARM Cortex-M1 compatibility
Thumb®
ARM7TDMI ARM926EJ-S ARM1176EJ-S Cortex-A8Cortex-R4Cortex-M3Cortex-M1
Thumb-2
Instruction set compatibility
© 2008 Actel 9April 2008Embedded Design in FPGA with Cortex-M1
Cortex-M1 instruction setBringing 32-bit performance, with advantages of 16-bit code density
More software can be squeezed into on-chip FPGA RAMCan allow a drop in FPGA size or remove the need for additional off-chip RAMReduces cost, improves performance
Simple Instruction Set ArchitectureBased on 16-bit Thumb, plus 32-bit Thumb-2 system instructions
DMB
DSB
ISB
MRS
MSR
32-bit
ADC ADD ADR AND ASR
B BIC BKPT BLX BX
CMN CMP CPS CPY EOR
LDM LDR LDRB LDRH LDRSB
LDRSH LSL LSR MOV MUL
MVN NEG NOP ORR POP
PUSH REV REV16 REVSH ROR
RSB SBC SEV STM STR
STRB STRH SUB SVC SXTB
SXTH TST UXTB UXTH WFE
WFI YIELD
BL
16-bit
© 2008 Actel 10April 2008Embedded Design in FPGA with Cortex-M1
Cortex-M1 is very easy to program
Vector Table Interrupt entry/exit stubs
Optimized compiler
Initialization codeException Handler
High quality tools
© 2008 Actel 11April 2008Embedded Design in FPGA with Cortex-M1
Other processors
Exception tableFetch instruction to branch
Top-level handler Routine handles re-entrancy
IRQVECTOR
LDR PC, IRQHandler
IRQHandler PROC
STMFD sp!,{r0-r4,r12,lr}
MOV r4,#0x80000000
LDR r0,[r4,#0]
SUB sp,sp,#4
CMP r0,#1
BLEQ C_int_handler
MOV r0,#0
STR r0,[r4,#4]
ADD sp,sp,#4
LDMFD sp!,{r0-r4,r12,lr}
SUBS pc,lr,#4
ENDP
Interrupt handling is fast and simple
ARM Cortex-M1
Core automatically handlesSaving corruptible registersException prioritizationException nesting
No need for assembly, just C
Pointer to C routine at vectorISR is a C function
Faster interrupt responseWith less software effort
© 2008 Actel 12April 2008Embedded Design in FPGA with Cortex-M1
Cortex-M1 supported first by ARM RealView toolsHigh-quality, intuitive software development toolsFully exploits performance and code density advantage of Cortex-M1
RealView Compiler Tools v3.1 feature MicroLibC libraries for embedded and memory constrained applications
Optimized for embedded appsTo get the most out of Cortex-M1
02000400060008000
100001200014000160001800020000
Library Totals RO Totals
RealView Tools support
64%599616452Library Total (bytes)
Thumb-2Cortex-M1
9016
MicroLib
19472
Standard
RO Total (bytes) 54%
% savingObjectProcessor
Dhrystone 2.1 Benchmark
© 2008 Actel 13April 2008Embedded Design in FPGA with Cortex-M1
ARM Cortex-M1 SummaryCortex-M1 and tools available as a free download from Actel
Encrypted version of ARM Cortex-M1 ProcessorSupporting Actel Fusion, ProASIC3 and Igloo deviceswww.actel.com
Complete solutionARM Cortex-M1PeripheralsHardware DesignSoftware DesignSynthesisDevelopment Boards
© 2008 Actel 14April 2008Embedded Design in FPGA with Cortex-M1
AgendaARM Cortex-M1
Dominic Pajak
Micrium uC/OS-IIJean Labrosse
Using Cortex-M1 in FPGAMike Thompson
© 2008 Actel 15April 2008Embedded Design in FPGA with Cortex-M1
Who is Micriµm?
Florida CorporationStarted in 1999Satellite office in Montreal, CanadaWorldwide distributors
Provider of: High Quality Embedded Software ComponentsSome products are FAA/FDA certifiedOutstanding support and documentation
Code provided in source formCleanest Source Code in the Industry!
© 2008 Actel 16April 2008Embedded Design in FPGA with Cortex-M1
MicriµmEmbedded Software Components (Middleware)
µC/OS-IIEmbedded RTOSµC/OS-MMUµC/OS-MPU
µC/FSEmbedded File System
µC/GUIEmbedded Graphical User Interface
µC/BuildingBlocksSoftware time-of-day clock (µC/CLK)Character-based LCD (µC/LCD)Shell (µC/Shell)CRC Calculation (µC/CRC)
µC/ProbeRun-Time Data Monitor
µC/TCP-IPEmbedded TCP/IP v4 stackDHCPc, DNSc, FTP, HTTPs, POP3c, SMTPc, SNTPc, etc.
µC/USB-DeviceBulk-device stackMass-Storage Class
µC/USB-HostHIDCDCMass-Storage Class
µC/ModbusMaster and/or SlaveRS-232C or RS-485ASCII and/or RTU
µC/CANCAN Framework
© 2008 Actel 17April 2008Embedded Design in FPGA with Cortex-M1
Micriµm2004 to 2006 Embedded Systems Bulletin (VDC)
#2 Commercial RTOS
Legend: 2004 Survey, 2005 Survey, 2006 Survey
© 2008 Actel 18April 2008Embedded Design in FPGA with Cortex-M1
MicriµmLicensing
Components are Royalty-Free
Licensed on a ‘per-end-product’ basisPerpetual use on that end-productUnlimited number of units
Each ‘different’ product that embeds our software requires a license
Other licensing schemes are available:Product Line (i.e. Family)Per-CPU type (ARM, Cortex, etc.)Site
© 2008 Actel 19April 2008Embedded Design in FPGA with Cortex-M1
µC/OS-IIThe Real-Time Kernel
Preemptive Multitasking
Supports up to 255 tasks and 255 priorities
Written in ANSI C
Highly portablePorted to over 45 different CPU architectures
Scalable and ROMable5K to 20K bytes code, 1K to 3K bytes data (Cortex-M1)
Provides standard ‘services’ to the applicationSemaphores, Mutexes, Queues, Task, Time, etc.
High Performance
© 2008 Actel 20April 2008Embedded Design in FPGA with Cortex-M1
µC/OS-IIThe Real-Time Kernel
Used in 1000s of products all over the world
Book describing internals
Adopted by 100s of Colleges & Universities
Supports most of the MISRA C rules
Third Party CertifiedFAA - DO178B Level AFDA - 510(k)IEC - 61508
© 2008 Actel 21April 2008Embedded Design in FPGA with Cortex-M1
µC/TCP-IPThe Embedded TCP/IP Stack
Cleanroom designBased on RFCsANSI C
Easy to Port Works with any RTOS (but needs an RTOS)Works with most 32 bit CPUsWorks with any NIC
© 2008 Actel 22April 2008Embedded Design in FPGA with Cortex-M1
µC/TCP-IPFootprint/Performance
Small Footprint (Scalable: 75 to 120 Kbytes)
Critical sections kept to a minimum
Zero copy
Small and Large packet buffersEfficient use of memorySmall and Large buffer size adjustable at compile time
© 2008 Actel 23April 2008Embedded Design in FPGA with Cortex-M1
µC/ProbeRun-Time Data Monitor
A universal embedded system monitoring tool
Windows app. that collects and displays target data at run-time:Any variableAny memory locationAny I/O port
Works with ANY processor8-, 16-, 32-, 64-bit or DSP
Works with ANY compilerCompiler/linker needs to generate a .ELF file
Works with any interfaceRS-232C, TCP/IP, USB, J-Tag, etc.
© 2008 Actel 24April 2008Embedded Design in FPGA with Cortex-M1
µC/ProbeRun-Time Data Monitor
‘Visualize’ a live embedded system using:Gauges and MetersNumeric indicatorsGraphs and PlotsBarchartsTablesVirtual LEDsEtc.
Change variables in the target usingSlidersDialsSwitchesButtonsEtc.
© 2008 Actel 25April 2008Embedded Design in FPGA with Cortex-M1
AgendaARM Cortex-M1
Dominic Pajak
Micrium uC/OS-IIJean Labrosse
Using Cortex-M1 in FPGAMike Thompson
© 2008 Actel 26April 2008Embedded Design in FPGA with Cortex-M1
Actel Cortex-M1 Design Flow
Priceless
CoreCoreConsoleConsole
• Select Processor
• Choose Peripherals
• Add Optional User Custom IP
• Auto Stitch to Build System
•• Select ProcessorSelect Processor
•• Choose PeripheralsChoose Peripherals
•• Add Optional User Custom IPAdd Optional User Custom IP
•• Auto Stitch to Build SystemAuto Stitch to Build System
• Combine System with Non-Processor Code
• Synthesis, Simulation, andLayout
• Optional Timing/PowerAnalysis
• Easy to use GUI
•• Combine System with Combine System with NNonon--Processor CodeProcessor Code
•• Synthesis, Simulation, andSynthesis, Simulation, andLayoutLayout
•• Optional Timing/PowerOptional Timing/PowerAnalysisAnalysis
•• Easy to use GUIEasy to use GUI
Libero IDELibero IDE
HARDWARE HARDWARE DEVELOPMENT FLOWDEVELOPMENT FLOW
SoftSoftConsoleConsole•• EclipseEclipse--Base IDEBase IDE
•• GNU CGNU C--CompilerCompiler
•• GNU DebuggerGNU Debugger
•• Memory Map and PeripheralMemory Map and PeripheralCore Driver File ImportCore Driver File Import
Industry Standard SupportIndustry Standard Support
•• Compilers Compilers –– RealView, Keil, IAR, GNURealView, Keil, IAR, GNU
•• RTOS RTOS –– uCuC/OS II, uClinux, Nucleus/OS II, uClinux, Nucleus
•• APIs, Drivers APIs, Drivers –– JungoJungo, GAO Research, GAO Research
•• Debuggers Debuggers –– RealView, GDB, IARRealView, GDB, IAR
OROR
SOFTWARE DEVELOPMENT FLOWSOFTWARE DEVELOPMENT FLOW
© 2008 Actel 27April 2008Embedded Design in FPGA with Cortex-M1
Priceless
CoreCoreConsoleConsole
• Select Processor
• Choose Peripherals
• Add Optional User Custom IP
• Auto Stitch to Build System
•• Select ProcessorSelect Processor
•• Choose PeripheralsChoose Peripherals
•• Add Optional User Custom IPAdd Optional User Custom IP
•• Auto Stitch to Build SystemAuto Stitch to Build System
• Combine System with Non-Processor Code
• Synthesis, Simulation, andLayout
• Optional Timing/PowerAnalysis
• Easy to use GUI
•• Combine System with Combine System with NNonon--Processor CodeProcessor Code
•• Synthesis, Simulation, andSynthesis, Simulation, andLayoutLayout
•• Optional Timing/PowerOptional Timing/PowerAnalysisAnalysis
•• Easy to use GUIEasy to use GUI
Libero IDELibero IDE
HARDWARE HARDWARE DEVELOPMENT FLOWDEVELOPMENT FLOW
SoftSoftConsoleConsole•• EclipseEclipse--Base IDEBase IDE
•• GNU CGNU C--CompilerCompiler
•• GNU DebuggerGNU Debugger
•• Memory Map and PeripheralMemory Map and PeripheralCore Driver File ImportCore Driver File Import
Industry Standard SupportIndustry Standard Support
•• Compilers Compilers –– RealView, Keil, IAR, GNURealView, Keil, IAR, GNU
•• RTOS RTOS –– uCuC/OS II, uClinux, Nucleus/OS II, uClinux, Nucleus
•• APIs, Drivers APIs, Drivers –– JungoJungo, GAO Research, GAO Research
•• Debuggers Debuggers –– RealView, GDB, IARRealView, GDB, IAR
OROR
SOFTWARE DEVELOPMENT FLOWSOFTWARE DEVELOPMENT FLOW
Actel Cortex-M1 Design Flow
© 2008 Actel 28April 2008Embedded Design in FPGA with Cortex-M1
CoreConsole - HW Development Tools
SOC Builder and IP Deployment Fast assembly and configuration of user designsEasy-to-use graphical user interfaceWide range of AMBA peripheral IP
CoreConsole v1.4Can be downloaded from www.actel.com
System output as configured RTLAllows easy system setup and configurationCortex-M1 output as a blackbox
Automatic IP vault web updateFull support for Cortex-M1 Seamless integration with Libero IDE
© 2008 Actel 29April 2008Embedded Design in FPGA with Cortex-M1
System-on-Chip - Cortex-M1
Processor SystemProcessorBus FabricComponents
ComponentsCortex-M1AMBA IP Cores
CoreConsole Automatically Creates Basic System
… OR … User Can Create System Manually
© 2008 Actel 30April 2008Embedded Design in FPGA with Cortex-M1
IP Cores Available in CoreConsole
ProcessorsCortex-M1, CoreMP7 Core8051s, CoreABC
AMBA Interfaces CoreAHB, CoreAHBLiteCoreAPB, CoreAPB3 CoreAHB2APB
Other Interfaces Core10/100, Core429, CorePCIFCore1553BRT, Core1553BRM
Subsystem Cores CoreAHBNvmCoreAHBSramCoreAICoreCFICoreDDRCoreFMEECoreFROMCoreGPIOCoreI2CCoreInterruptCoreMemCtrlCorePWMCoreRemapCoreSDRCoreSMBusCoreTimerCoreUART, CoreUARTapbCoreWatchdog
© 2008 Actel 31April 2008Embedded Design in FPGA with Cortex-M1
Building an SoC with CoreConsole
Decide on components needed to meet system requirements.
Add busses and bridge as necessary
Add components
Connect to busses
Configure components and memory map placement.
Generate system
Test and Verify the system
© 2008 Actel 32April 2008Embedded Design in FPGA with Cortex-M1
Cortex-M1 - CoreConsole Configuration
Select Debug InterfaceNone (Default)RealView JTAGFlashPro3
Select DieM1AFS600 (Default)M1A3P1000Future Project-Wide Setting
Other Options Inactive
© 2008 Actel 33April 2008Embedded Design in FPGA with Cortex-M1
Stitching an SOC TogetherCoreConsole enables components to be stitched to the AHB and APB busses
Components ‘advertise’ the interfaces they have available
Auto-Stitching supportedto accelerate this task
User can add and remove individual connections
Ad-Hoc connections are selected from drop down configuration boxes
© 2008 Actel 34April 2008Embedded Design in FPGA with Cortex-M1
Adhoc Signal Connections To connect
Right Click on component and click configure Or click
Label the connectionSelect ‘From’ component and pinSelect ‘To’ component and pinClick connectObserve the connection label added to schematic
© 2008 Actel 35April 2008Embedded Design in FPGA with Cortex-M1
Rapid SOC GenerationItems to be Generated are Selected in This Tab
Output Folder Tree is C:\CoreConsole\LiberoExport\<MyDesign>
Details of the Files Output are Communicated to Libero in an XML File
Libero uses this to import a design
All the Files Generated by CoreConsole Can Be Located on the Disk And Manually Edited
© 2008 Actel 36April 2008Embedded Design in FPGA with Cortex-M1
Priceless
CoreCoreConsoleConsole
• Select Processor
• Choose Peripherals
• Add Optional User Custom IP
• Auto Stitch to Build System
•• Select ProcessorSelect Processor
•• Choose PeripheralsChoose Peripherals
•• Add Optional User Custom IPAdd Optional User Custom IP
•• Auto Stitch to Build SystemAuto Stitch to Build System
• Combine System with Non-Processor Code
• Synthesis, Simulation, andLayout
• Optional Timing/PowerAnalysis
• Easy to use GUI
•• Combine System with Combine System with NNonon--Processor CodeProcessor Code
•• Synthesis, Simulation, andSynthesis, Simulation, andLayoutLayout
•• Optional Timing/PowerOptional Timing/PowerAnalysisAnalysis
•• Easy to use GUIEasy to use GUI
Libero IDELibero IDE
HARDWARE HARDWARE DEVELOPMENT FLOWDEVELOPMENT FLOW
SoftSoftConsoleConsole•• EclipseEclipse--Base IDEBase IDE
•• GNU CGNU C--CompilerCompiler
•• GNU DebuggerGNU Debugger
•• Memory Map and PeripheralMemory Map and PeripheralCore Driver File ImportCore Driver File Import
Industry Standard SupportIndustry Standard Support
•• Compilers Compilers –– RealView, Keil, IAR, GNURealView, Keil, IAR, GNU
•• RTOS RTOS –– uCuC/OS II, uClinux, Nucleus/OS II, uClinux, Nucleus
•• APIs, Drivers APIs, Drivers –– JungoJungo, GAO Research, GAO Research
•• Debuggers Debuggers –– RealView, GDB, IARRealView, GDB, IAR
OROR
SOFTWARE DEVELOPMENT FLOWSOFTWARE DEVELOPMENT FLOW
Actel Cortex-M1 Design Flow
© 2008 Actel 37April 2008Embedded Design in FPGA with Cortex-M1
Libero IDELibero Project Manager
Manages design flow and files
Design Creation/VerificationHDL, SmartGen Cores, SchematicOptimizationTest BenchVerification
Design ImplementationFloor planning & physical constraints Place & RouteTiming constraints & analysisPower analysisProgram file generation
Programming and Debug FlashPro3 supports Programming for all Fusion devices
© 2008 Actel 38April 2008Embedded Design in FPGA with Cortex-M1
Libero IDE
Design Hierarchy
View
Catalog:- Configurable Cores- HDL Templates- Macros- Bus Interfaces
Interactive Design Flow
Management Tools
Log File
Design Entry Tools
© 2008 Actel 39April 2008Embedded Design in FPGA with Cortex-M1
Libero IDE - Project Manager
File Manager
View
Catalog:- HDL Templates
- Simple click to insert into HDL code
- Proven/tested
© 2008 Actel 40April 2008Embedded Design in FPGA with Cortex-M1
Synthesize with Synplicity’s Synplify AE
Synplify AELeading edge synthesis from the market leaderClose OEM partnership provides optimal benefit to Actel users Integration with Libero IDE ensures seamless operation Optimized performance and area utilization for all Actel FPGAsAvailable in Free Libero Gold
© 2008 Actel 41April 2008Embedded Design in FPGA with Cortex-M1
Mentor Graphics ModelSim HDL Simulator
HDL simulation in VHDL or VerilogPre-synthesis simulationPost-synthesis simulationPost-layout simulation
Simulate
© 2008 Actel 42April 2008Embedded Design in FPGA with Cortex-M1
Libero IDE - Designer User Interface
Physical Implementation
Tools
Constraint & Analysis Tools
Log & Device Information
© 2008 Actel 43April 2008Embedded Design in FPGA with Cortex-M1
Libero IDE- “Designer” Physical Implementation
Designer FunctionsImport Netlist, Compile, and Design Rule CheckFloor planning and physical constraintsTiming driven Place and RouteBack annotated timing for full timing simulationSmartTime setup of Timing Constraints and Timing AnalysisSmartPower analysis of power consumption Generate bitstream or STAPL programming filesComprehensive log file and reports
© 2008 Actel 44April 2008Embedded Design in FPGA with Cortex-M1
Device Programming and DebugProgramming Software
FlashProIn System Programming (ISP) for Actel Flash devices
Supports all FlashPro hardware programmersIncludes ChainBuilder
Generates a merged STAPL file for programming Actel FLASH devices in a mixed IC environment
Silicon SculptorSupports all Actel devices
Use with Silicon Sculptor hardware programmers Launch from Libero Project Manager or stand alone
Device DebuggingSynplicity Identify Debugger
© 2008 Actel 45April 2008Embedded Design in FPGA with Cortex-M1
Priceless
CoreCoreConsoleConsole
• Select Processor
• Choose Peripherals
• Add Optional User Custom IP
• Auto Stitch to Build System
•• Select ProcessorSelect Processor
•• Choose PeripheralsChoose Peripherals
•• Add Optional User Custom IPAdd Optional User Custom IP
•• Auto Stitch to Build SystemAuto Stitch to Build System
• Combine System with Non-Processor Code
• Synthesis, Simulation, andLayout
• Optional Timing/PowerAnalysis
• Easy to use GUI
•• Combine System with Combine System with NNonon--Processor CodeProcessor Code
•• Synthesis, Simulation, andSynthesis, Simulation, andLayoutLayout
•• Optional Timing/PowerOptional Timing/PowerAnalysisAnalysis
•• Easy to use GUIEasy to use GUI
Libero IDELibero IDE
HARDWARE HARDWARE DEVELOPMENT FLOWDEVELOPMENT FLOW
SoftSoftConsoleConsole•• EclipseEclipse--Base IDEBase IDE
•• GNU CGNU C--CompilerCompiler
•• GNU DebuggerGNU Debugger
•• Memory Map and PeripheralMemory Map and PeripheralCore Driver File ImportCore Driver File Import
Industry Standard SupportIndustry Standard Support
•• Compilers Compilers –– RealView, Keil, IAR, GNURealView, Keil, IAR, GNU
•• RTOS RTOS –– uCuC/OS II, uClinux, Nucleus/OS II, uClinux, Nucleus
•• APIs, Drivers APIs, Drivers –– JungoJungo, GAO Research, GAO Research
•• Debuggers Debuggers –– RealView, GDB, IARRealView, GDB, IAR
OROR
SOFTWARE DEVELOPMENT FLOWSOFTWARE DEVELOPMENT FLOW
Actel Cortex-M1 Design Flow
© 2008 Actel 46April 2008Embedded Design in FPGA with Cortex-M1
SoftConsole - Processor SW Development
Software development environment Eclipse-based IDE - easy user interfaceSupports Cortex-M1, CoreMP7, Core8051/sCan be downloaded from www.actel.com
C/C++ programming and debugCodeSourcery G++ ARM toolsSDCC 8051 compilerProgramming and debug with Actel’s FlashPro3
Can import existing codeOpen platform for application development
Support for RTOS and stacksuC/OC, uClinuxTCP/IP, USB, IPMI
© 2008 Actel 47April 2008Embedded Design in FPGA with Cortex-M1
SoftConsole GNU C/C++ Compiler
Extensive intelligent ARM optimizationBuilt from CodeSourcery G++ GNU/GDB
Includes many features useful for embedded systems
Powerful inline assembly syntaxComprehensive linker script language permitting exact placement of code and data
Large developer base results in tool stability
ISO C and C++ language supportComplete runtime librariesAggressive code usage analysis and syntax warningsSupports ARM EABI for better portability
© 2008 Actel 48April 2008Embedded Design in FPGA with Cortex-M1
SoftConsole GDB Debugger
Support for source- and assembly-level debugging
Live debugging of new codeIn an FPGA or in the GDB ARM simulator
Breakpoints can occur when certain conditions are met
Intelligent access to hardwareRegister banks and memory rangesHover over a variable to read its current value Changes in value are obvious for any variable, memory or registerCurrent stack frame displayed while debugging
Evaluation of expressions at runtime
© 2008 Actel 49April 2008Embedded Design in FPGA with Cortex-M1
Priceless
CoreCoreConsoleConsole
• Select Processor
• Choose Peripherals
• Add Optional User Custom IP
• Auto Stitch to Build System
•• Select ProcessorSelect Processor
•• Choose PeripheralsChoose Peripherals
•• Add Optional User Custom IPAdd Optional User Custom IP
•• Auto Stitch to Build SystemAuto Stitch to Build System
• Combine System with Non-Processor Code
• Synthesis, Simulation, andLayout
• Optional Timing/PowerAnalysis
• Easy to use GUI
•• Combine System with Combine System with NNonon--Processor CodeProcessor Code
•• Synthesis, Simulation, andSynthesis, Simulation, andLayoutLayout
•• Optional Timing/PowerOptional Timing/PowerAnalysisAnalysis
•• Easy to use GUIEasy to use GUI
Libero IDELibero IDE
HARDWARE HARDWARE DEVELOPMENT FLOWDEVELOPMENT FLOW
SoftSoftConsoleConsole•• EclipseEclipse--Base IDEBase IDE
•• GNU CGNU C--CompilerCompiler
•• GNU DebuggerGNU Debugger
•• Memory Map and PeripheralMemory Map and PeripheralCore Driver File ImportCore Driver File Import
Industry Standard SupportIndustry Standard Support
•• Compilers Compilers –– RealView, Keil, IAR, GNURealView, Keil, IAR, GNU
•• RTOS RTOS –– uCuC/OS II, uClinux, Nucleus/OS II, uClinux, Nucleus
•• APIs, Drivers APIs, Drivers –– JungoJungo, GAO Research, GAO Research
•• Debuggers Debuggers –– RealView, GDB, IARRealView, GDB, IAR
OROR
SOFTWARE DEVELOPMENT FLOWSOFTWARE DEVELOPMENT FLOW
Actel Cortex-M1 Design Flow
© 2008 Actel 50April 2008Embedded Design in FPGA with Cortex-M1
On-Chip Debugging via FlashPro3Download and debug executable programs to development boards using FlashPro3
Can program and debug processor memory and FPGA fabric with FlashPro3Reduces pin-count – Utilizes dedicated FPGA JTAG pins via UJTAG versus GPIO RVI-ME configuration (10-pins)
Full debugging of code on remote targetView internal registers, memory locations, variables, etc.
Uses the same interface as Instruction Set Simulator
Only one tool to learn
© 2008 Actel 51April 2008Embedded Design in FPGA with Cortex-M1
Actel M1 Development Boards M1-SYSMGMT-DEV-KIT
M1AFS600 deviceSystem Mgmt GUI Demonstration designsFull PCI interfaceAlso available with FP3
M1 SOC BoardsPowered by USB or wall supply1M SRAM, 4M Flash memoryFP3 programmer built into boardExpansion connectors
M1A3P-DEV-KIT-SCSM1A3P1000 device
M1AFS-DEV-KIT-SCSM1AFS600 device
M1AGL-DEV-KIT-SCS M1AGL600 device
M1A3P1000
© 2008 Actel 52April 2008Embedded Design in FPGA with Cortex-M1
Cortex-M1 ATCA Design
© 2008 Actel 53April 2008Embedded Design in FPGA with Cortex-M1
Cortex-M1 in Fusion FPGAATCA IPMC/carrierIPMCATCA Blade and ATCA AMC Carrier reference designs using Cortex-M1
IPMC Blade and AMC Carrier (carrier-IPMC) designs running on benchtop development board using ARM Cortex-M1 processorSerial-over-LAN support for Intel 82575/1, Broadcom BCM5714C network controllers in all four modes (NC-SI, DE, SPT, PT)Firmware proven in high reliability applications
Firmware in C and built with GCC and GNU tools in SoftConsole Firmware upload over IPMB-0 or the serial port is implemented
Supports all mandatory and a wide range of optional IPMI commands
In development nowFusion AMC carrier needs 1/3 less board area than H8S design (1,167mm2 vs 1,748mm2)
Available Q3 2008
© 2008 Actel 54April 2008Embedded Design in FPGA with Cortex-M1
Where to Go for More Information Cortex-M1 on the Web
http://www.arm.com/products/CPUs/ARM_Cortex-M1.htmlhttp://www.micrium.com/products/rtos/kernel/rtos.htmlhttp://www.actel.com/products/mpu/CortexM1/
Key DocumentsCortex-M1 Handbook (Actel)ARMv6-M Architecture Reference Manual (ARM)Cortex-M1 Technical Reference Manual (ARM)uC/OS-II Datasheet (Micrium)
© 2008 Actel 55April 2008Embedded Design in FPGA with Cortex-M1
Summary Cortex-M1 allows designers to benefit from hassle-free, industry-standard ARM architecture
Optimized for use in M1 devices (ProASIC3, IGLOO, Fusion)
A huge number of tools are available like Micrium’s uC/OS-II RTOS to simplify design
Actel FPGA tools offer seamless development flowCoreConsole, Libero, dev kit hardware development toolsSoftConsole with GNU software development toolsM1 development boards
Brings flexibility and fast time to market to system-level designs