Workshop ESSCIRC
Low-Power Data Acquisition System For Very Small Signals At Low Frequencies With12-Bit-SAR-ADC
Christof Dohmen
17. September 2010
2
Outline
System Overview
Analog-Front-End• Chopper-Amplifier
• Anti-Aliasing-Filter
• Measurement Results
Charge Scaling SAR-ADC• ADC-Concept
• Measurement Results
System Summary
ULTRAsponder Sep-10 © IMST GmbH - All rights reserved
3 ULTRAsponder Sep-10 © IMST GmbH - All rights reserved
Data Acquisition System Overview
Purpose: sensor frontend of the Ultrasponder-implant
Problems with biomedical signals:
- at very low frequencies 1/f noise dominates in amplifiers and overlays very small signals
- dc-offsets in amplifiers at very high gain distort or even destroy these signals
living tissue electrodes “low frequency” amplifier anti-aliasing
low pass
12-bit SAR-ADC
digital IO
4
Solution: use a chopping amplifier
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Input Signal below expected 1/f-noise floor
modulation of input signal up to higher frequency by a square-wave→ “chopping”
amplification => high band-width required due to square-wave spectrum
demodulation by the same square-wave
output signal contains the amplified input and undesired signals at high frequencies => low-pass filtering required!
f
V
f
V
f
V
VinVout
non-overlapping pulse clock, fCH=4kHz
A=40dBGBW=10MHz
fC,LP=70Hz, 80dB/dec
f
V
f
V
5
Realization of Chopper-Elements
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TMG
TMG
TMG
TMG
phi 2
phi 1
phi 2
phi 1
phi 1
phi 2
clk in
Non-overlapping clock generator
Modulator / Demodulator
6
Active LP- Filter – Fully Differential Multiple Feedback
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Anti-Aliasing-Low-Pass-Filter Requirements
- 20dB gain in pass-region
- cut-off-frequency fC,3dB=70Hz => large external passive elements required
- filter suppression of 72.24dB at least required for 12 bit resolution in ADC
A=10dB A=10dB
3.57MΩ
3.57MΩ
10MΩ
10MΩ 10.7MΩ
10.7MΩ7.5MΩ
7.5MΩ
36.25MΩ
36.25MΩ 7.5MΩ
7.5MΩ
56pF
56pF27pF
27pF
500pF265pFVin Vout
cap. load of ADC-input
noisy signal from chopper-amplifier
7
Anti-Aliasing-Filter: frequency plot from lab-results
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y = -34,608Ln(x) + 166,44
-70
-60
-50
-40
-30
-20
-10
0
10
20
30
1 10 100 1000
Freq. [Hz]
Gai
n [d
B]
SE Gain [dB]TrendLogarithmisch (Trend)
Verification of parameters by measurement
- 20dB Gain in pass-region
- cut-off-frequency fC,3dB=70Hz
- cut-off-steepness 80dB/decade due to 4th filter order
ext. filter-elements on testboard
8
Chopping in time domain: lab results
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1) pulse-clock source 2) chopped & amplified sine-signal
3) demodulated amplified sine-signal 4) filtered amplified sine-signal
9
Outline
System Overview
Analog-Front-End• Chopper-Amplifier
• Anti-Aliasing-Filter
• Measurement Results
Charge Scaling SAR-ADC• ADC-Concept
• Measurement Results
System Summary
ULTRAsponder Sep-10 © IMST GmbH - All rights reserved
10
Overview of ADC-Concepts: Speed vs Resolution
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- Very fast (one step conversion)- Low resolution- High power consumption - Still one-step converter
- Improvements to save space and power, to increase resolution but also maintaining speed => ‘fast low power ADC’
- Very high resolution at low noise due to oversampling (fast clock required!)
- ‘low power ADC for high resolution’
Sou
rce:
San
sen,
Ana
log
Des
ign
Ess
entia
ls, p
. 209
→ optimum properties for ultra low power at medium speed/medium resolution
→ charge-scaling ADC
- can be very accurate but very slow
Targeted: 12bit, fS<50kS/s, Vref=1.5V, fclk=1MHz
11
Successive-Approximation-Register-ADC (SAR)
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S&HComp
SAR-logic
DAC
b0 b1 bN-1……
Vin
Vref
fS
fclk=N*fS
+
-
fSoutput B
VDAC=B*Vref
Vin
General SAR-structure
Sou
rce:
Joh
ns/M
artin
, Ana
log
Inte
grat
ed C
ircui
t Des
ign
10 0.25 0.5axis normalized to Vref/2
Example: find 0.4 Vref
General SAR-algorithm
→ here the DAC is realized as a charge-scaling capacitor-array
→ advantage: DAC also acts as S&H, very low power
12
MSB
MSB
SAR-ADC with Charge Scaling DAC (1)
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Sou
rce:
San
sen,
Ana
log
Des
ign
Ess
entia
ls
1. Sample Mode
2. Hold Mode
13
Vcomp
SAR-ADC with Charge Scaling DAC (2)
Cycling principle:
If Vx>Vref/2i: bi = 1⇒ leave Cbi to Vref
if Vx<Vref/2i: bi = 0⇒ leave Cbi to GND
MSB Sou
rce:
San
sen,
Ana
log
Des
ign
Ess
entia
ls3. Bit Cycling
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Vin=0V
results in
B=‘0000000000’
14 ULTRAsponder Sep-10 © IMST GmbH - All rights reserved
Vin=1.8V
results in
B=‘1111111111’
SAR-ADC with Charge Scaling DAC (3)
Vin=1.0V
results in
B=‘1000111000’
15 ULTRAsponder Sep-10 © IMST GmbH - All rights reserved
Design Improvements of the ADC for Ultrasponder
regenerative amplifiers and latch in comparator: reduces power
differential input: better CMRR
SAR control
Vin,p
Vrefp
Vrefn
Vin,p
Vrefp
Vrefn
Vin,n
Vrefp
Vrefn
Vin,n
Vrefp
Vrefn
auto-zeroing: increases accuracy
AZ
6 bit
Digital Output
Sleep
Comp.out
CS
CS
Main-DAC
Main-DAC
Sub-DAC
Sub-DAC
separation into 2 nearly identical Main- and Sub-DACs: better accuracy
6 bit
use topplates as floating nodes: less parasitics
clk start
size of single capacitor not too small due to mismatch
16
Design of the Comparator with Autozero
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- single-stage preamplifiers increase Vin-sensitivity to 180uV (= VLSB/2) @ settling-time tsettle< 500ns (maximum system-clock fclk=1MHz)
Vin Vout,comp
AZ
purge
purge
preamp preamp preamp
latch
resetsleep
AZ
purge
purge
AZ
purge
purge
A 4-step autozero-cycle is preceding every conversion:
1. Each preamp is shorted at its input. A short closing of the purge-switches discharges the autozero-capacitors
2/3/4. On opening the AZ-switches from back to front the autozero-capacitors store offset from preamplifiers
17
ADC Lab-Results: Time-Domain-Signal
Test signal for ADC-performance-check:• clean sine (negligible distortion & noise) • perfect full-scale amplitude• long conversion period to acquire enough data
→ time domain signal (blue) with Sine Wave Fitting (red) from 512kSamples, fS=20kS/s
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18
ADC Lab-Results: FFT
Calculated parameters:
Frq.: 39,9399HzA: 0,99976SINAD: 51,2632 dBENOB: 9,1009SNR: 51,2905 dBTHD: -53,2483 dBSFDR: 53,2557 dB @ 2
FFT (512k Samples, 20kS/s)
Performance parameters can be calculated from the FFT of the conversion data:
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19
ADC Lab-Results: Differential Nonlinearity (DNL)
DNL of the ADC (512k Samples)
DNL: deviation in step sizes differing from ideal +1 LSB step
here: 6 LSBs → costs 3 bits of resolution → undesirableReason:
mandatory metal-fill-structures on chip increases capacitance of the single elements (Cnom=104fF) → the scaling capacitor of the Sub-DAC is too small
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single capacitor element with fill structure
20
ADC Lab-Results: Integral Nonlinearity (INL)
INL of the ADC (512k Samples)
INL: deviation from the ideal step value
here: 6 LSBs in either direction → costs 4 bits of resolution → possibly worse than in reality due to measurement errors
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21
ADC-Performance Comparison: Figure of Merit (FOM)
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Sou
rce:
IEE
E, I
SS
CC
200
6, s
essi
on 1
2.5
FOM for the Ultrasponder-ADC:
Relation of power, resolution and input frequency:
22 ULTRAsponder Sep-10 © IMST GmbH - All rights reserved
Summary: Ultrasponder Data‐Acquisition‐Chip
- process technology 130nm
23
Performance summary
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Questions?