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Logic Gates ลอจกิเกต
INVERTER
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ตารางความจรงิของ INVERTER
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INVERTER TIMING DIAGRAM
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Inverter operation with a pulse input.
The inverter complements an input variable.
INVERTER TIMING DIAGRAM
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AND GATE
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FIGURE 3--9 ALL POSSIBLE LOGIC LEVELS FOR A 2-INPUT AND GATE.
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AND Gate Operation
AND GATE TRUTH TABLE
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Boolean expressions for AND gates
with two, three, and four inputs.
ตารางความจรงิของ AND GATE
แบบสามอนิพตุ
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AND GATE TIMING DIAGRAM
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Example of pulsed AND gate operation with a timing
diagram showing input and output relationships.
AND GATE TIMING DIAGRAM
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All must be
high for the
output to be
high
AN AND GATE PERFORMING AN ENABLE/INHIBIT
FUNCTION FOR A FREQUENCY COUNTER.
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AND Gate Application Example
OR GATE
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ALL POSSIBLE LOGIC LEVELS
FOR A 2-INPUT OR GATE
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OR Gate Operation
OR GATE TRUTH TABLE
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Boolean expressions for OR gates
with two, three, and four inputs.
OR GATE TIMING DIAGRAM
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Example of pulsed OR gate operation with a timing diagram
showing input and output time relationships.
OR GATE TIMING DIAGRAM
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All must be low for
the output to below
OR GATE APPLICATION EXAMPLE
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A simplified intrusion detection system
using an OR gate.
NAND GATE
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OPERATION OF A 2-INPUT NAND GATE.
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NAND Gate Operation
NAND GATE TRUTH TABLE
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NAND GATE TIMING DIAGRAM
ABX
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FIGURE 3--29 STANDARD SYMBOLS REPRESENTING THE TWO
EQUIVALENT OPERATIONS OF A NAND GATE.
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NOR GATE
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OPERATION OF A 2-INPUT NOR GATE.
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NOR Gate Operation
NOR GATE TRUTH TABLE
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NOR GATE TIMING DIAGRAM
BAX
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STANDARD SYMBOLS REPRESENTING
THE TWO EQUIVALENT OPERATIONS
OF A NOR GATE.
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XOR GATE
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ALL POSSIBLE LOGIC LEVELS
FOR AN EXCLUSIVE-OR GATE
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XOR Gate Operation
XOR GATE TRUTH TABLE
BAX
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XOR GATE APPLICATION EXAMPLE
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An XOR gate used to add two bits.
XNOR GATE
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ALL POSSIBLE LOGIC LEVELS
FOR AN EXCLUSIVE-NOR GATE.
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XNOR Gate Operation
XNOR GATE TRUTH TABLE
BAX
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FIXED-FUNCTION LOGIC
: IC GATES
CMOS (Complementary Metal-Oxide
Semiconductor)
TTL (Transistor-Transistor Logic)
CMOS – lower power dissipation
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TYPICAL DUAL IN-LINE (DIP) AND SMALL-
OUTLINE (SOIC) PACKAGES SHOWING PIN
NUMBERS AND BASIC DIMENSIONS.
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PIN CONFIGURATION DIAGRAMS FOR SOME COMMON
FIXED-FUNCTION IC GATE CONFIGURATIONS. 38
LOGIC SYMBOLS FOR HEX INVERTER (04 SUFFIX) AND
QUAD 2-INPUT NAND (00 SUFFIX). THE SYMBOL APPLIES
TO THE SAME DEVICE IN ANY CMOS OR TTL SERIES.
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PERFORMANCE CHARACTERISTICS
AND PARAMETERS
Propagation delay Time
DC Supply Voltage (VCC)
Power Dissipation
Input and Output Logic Levels
Speed-Power product
Fan-Out and Loading
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PROPAGATION DELAY
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THE LS TTL NAND GATE OUTPUT FANS OUT
TO A MAXIMUM OF 20 LS TTL GATE INPUTS.
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Higher fan-out = gate can be connected to more gate inputs.
THE PARTIAL DATA SHEET FOR A 74LS00. 43
THE EFFECT OF AN OPEN INPUT
ON A NAND GATE.
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Troubleshooting
TROUBLESHOOTING A NAND GATE FOR
AN OPEN INPUT WITH A LOGIC PULSER AND PROBE.
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PROGRAMMABLE LOGIC Programmable Arrays
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Figure 3--65 An example of a basic programmable OR array.
AN EXAMPLE OF A BASIC
PROGRAMMABLE AND ARRAY.
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BLOCK DIAGRAM OF A PROM
(PROGRAMMABLE READ-ONLY MEMORY).
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4 Types of SPLDs
BLOCK DIAGRAM OF A PLA
(PROGRAMMABLE LOGIC ARRAY).
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BLOCK DIAGRAM OF A PAL
(PROGRAMMABLE ARRAY LOGIC).
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BLOCK DIAGRAM OF A GAL
(GENERIC ARRAY LOGIC)
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LOGIC GATE SUMMARY
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