()Programmable Logic Devices -1 -2 - - -
-2 -: )1 ( )Boolean Arithmetic ( )Boolean Arithmetic (
)And,Or,Not . ()2 Bit Half Adder )Sum = (x AND NOT y) OR (NOT x AND
y )Carry =(x AND y )2 2 ( )Flip Flop ( )Register ) ( ) :
()Synchronous )1 1 ()Clocked (:)Asynchronous )2 2 ()Non-Clocked )
)1 1 )(Analog )2 2
Formatted: Bullets and Numbering
Formatted: Bullets and Numbering Formatted: Bullets and
Numbering
Formatted: Bullets and Numbering
Formatted: Bullets and Numbering
-3 ( )Integrated Circuits ()Chips ) ( ))LSI(Large Scale
Integration ) ()AND, OR, NOT ( ) LSI ()Multiplier( )Adder( )Decoder
) ()Very Large Scale Integration( )VLSI ( )LSI ()CPU( )Processor )
()PLD( )Programmable Logic Devices Formatted: Bullets and
Numbering
( )PLD ( )ROM ( )PAL ( )PLAs ( )PLD ( )PLD ()PAL
( : )1 ()PAL ) ()ASIC -: ) 1 )2 ) )(CPLD ) (PLD ( ) PLD ( )PAL (
(CPLD ) )FPGA( Field Programmable Gate Arrays ( ) CPLD ( ) FPGA (
)Flip-Flop ()CPLD
( : )2 ()FPGA
-4 ( FPGA) ( F P G )A ( )LOGIC CELLS ) (Flip-Flop ) (Vendor)
(Family )(FPGA FPGA ) (Logic Block)(Logic Element ) ) (Logic Cells)
LUT (Look up Tables )(ROMs FPGA SRAM)(Dual Port Memory )(CAM ) (HDL
schematic entry ) (Routing Resources )(FPGA ) ) (FPGA Memory, LUT
& Logic Cells ) pins ) (PINs )(FPGA )(TTL) (CMOS) (PCI ) (AGP .
) (FPGA ) pins ()PLL( )Clock ) (FPGA ( )Reset( )Clock ( )FPGA )
)PLL( (Clock ()Divider( )ClockMultiplier
Xilinx's Virtex Slice)3(
Altera's Apex Logic Element )4(
-6 ()FPGA ( )FPGA . ) (Demo . ) (Applications -: (External . (
)FPGA ) Headers . ( )Interface Chips ()FPGAFormatted: Bullets and
Numbering
Formatted: Bullets and Numbering
-11 . ( )FPGA ()FPGA ( )FPGA ()ASIC .Formatted: Bullets and
Numbering
- 12 - 13 ( )FPGA ( )FPGA ( )FPGA ( )FPGA ( )FPGA ( )FPGA (
)FPGA
()FPGA - 14 ( )FPGA ()FPGA ( )HDL ( )HDL (FPGA . -7 ( )FPGA -: -
- )1 ( ) ) (schematic Entry . )2 ( )HDL ( )HDL VHDL & Verilog
VHDL.. . . . - ()Simulation - )(Synthesis
( )HDL schematic Entry - )(Place and route FPGA . ) (pins -
()Bit Stream ( )Bit Stream ( )Programming File ( )FPGA ( .)FPGA . (
)Bit Stream ( )Hardware Design (HDL ( )AND,OR,NOT ( )Loops,Case,If
( ) ( )HDL ()AHDL( )VHDL( )Verilog CPLD )LSI (Large Scale
Integration CPLD )(Complex Programmable Logic Device ( ). CPLD FPGA
IC . : 0077 NAND 0070 NOT . CPLD
. XC9500 XILINIX
PLCC(Plastic Leaded Chip Carrier) . XC9500 PLCC : Plastic Leaded
Chip Carrier FB: Function Block FB 2 . Gates: . Macrocells: full
adder registers. Pin: . CPLD flash memory . XC9500 11111. . XC9500
. : XC9572 1611 84 $ 75 (12.5
FPGA: FPGA
1 " " coarse-grained : .
2- " " fine-grained:
.
FPGA: 1 : frame ASIC . FPGA .
2 : FPGA . .
FPGA: FPGA soft ware hard ware ) . NAND FILP_FLOP AND FPGA AND
AND IC 4066
VHDL Very high speed integrated circuits Hardware Description
Language ( ) ( ) (application-specific integrated circuits ( ASIC .
graphics VGA . VHDL ( ) Header-1 Interface (Entity)-2
Functions(Architecture)-3 Header :
;LIBRARY library_name ;USE library_name.package_name.ALL :
;LIBRARY ieee ;USE ieee.std_logic_1164.ALL IEEE std_logic_1164 .
. : Interface (Entity) :
ENTITY entity_name IS PORT (in1,in2, :attribute data_type
;out1,out2,.:attribute data_ty ;)pe ; END entity_name , In1,in2,
Attribute .. VHDL IN OUT INOUT BUFFER ( ) Data_type: VHDL!!
1-std_logic ( ) (on-off)1-1 2-std_logic_vector: )(bus 1-1 )(on-off
3-integer: ) (bus . bit std_logic :
ENTITY my_first IS ; PORT ( x1,x2,x3 : IN STD_LOGIC ;)y: OUT
STD_LOGIC_VECTOR (1 TO 5 ;)c:BUFFER INTEGER RANGE 0 TO 4 ; END
my_first x1,x2,x3 ) (and-or-not- y 1 (y1,y2,y3,y4,y5) 5 C 4 3 (4
=100) . : VHDL .
Half adder )VHDL( - 11LIBRARY ieee; USE ieee.std_logic_1164.ALL;
ENTITY Adder_ent IS PORT ( Op1 : IN std_logic; op2 : IN std_logic;
carry : OUT std_logic; Result : OUT std_logic); END Adder_ent;
ARCHITECTURE behavior OF Adder_ent IS BEGIN -- behavior Result
