Hipex is an accurate and fast full-chip hierarchical extraction software that performs extraction of parasitic capacitances and resistances from hierarchical layouts. Hipex is tightly integrated with the Expert Layout Editor for complete design flow of DRC/LVS and RC parasitic extraction.

Key Features

Hipex NET Device Extraction

HipexFull-Chip Parasitic Extraction

• User-programmablenetlistextractionprovidescustomsetofextracted parameters (e.g. Well Proximity, STI stress effects)

• Multipleparasiticextractionmodels,includinglumpedRC,Conly,Ronly,coupledCandfullydistributedRC

• SelectednetextractionforfastRCextractionofcriticalpathnets in SoCs and large memories

• EfficientnetworkreductionfordistributedparasiticRCnetworks

• OutputparasiticnetlistfilesinSPICE,DSPF,SPEF,andP2Pformats

• Automatedbackannotationenablesaccuratepost-layoutsimulation and analysis

• Fieldsolvermodeprovidesaccurateparasiticresistance/capacitance calculation

• Rapidrule-basedapproachconsistingofusingbuilt-inandcustom equations for parasitic extraction

• Differentmodesofparasiticextractionandtheircombinationsprovidevarioussolutionsintermsoftrade-offbetweenaccuracyandproductivity

• IntegratedintoExpertLayoutEditor

• Supportscustomtechnologies(i.e.LCD,analog,mixed)andindustry-standard PDKs

• Extractshierarchicalnetlistpreservingoriginallayouthierarchy for easy analysis

• ExtractsMOSFET,MESFET,BJT,JFET,diode,capacitor,resistor,andparameterizeduser-defineddevices

• Performselectricalrulechecking(ERC)forshorts,opens,dangles

• Providesfullcustomizationforasetofextractedparameters

• Accuratedeviceextractionfornon-45andnon-90degreesdevices

• Efficientmemoryusageforhandlinglargedesigns

• Maintainsnetlistdatabaseforback-annotationanddevice/netprobing

Hipex Parasitic Capacitance Extraction• Drivenbyrule-basedtechnologyfile

• OffersFieldSolversbasedapproachforveryaccurateparasitic capacitance extraction

• Back-annotatestheschematicnetlistwithparasiticcapacitors

• Stripingalgorithmandstripedatabaseenablesefficientparallelization for multi-processor machines

• Supportsblack-boxingforintegrationwithroutingtools

• Extractsparasiticcouplingcapacitorsforfullchipandselected nets

• Offersuser-definedorbuilt-incapacitancemodels

• SupportsexternalcapacitancerulefilesgeneratedbyExact for 3D accurate mode

• Createsincrementalcapacitancedatabaseonanet-by-netbasis

• ExtractsselectednetsforfastparasiticCcomputationofcritical paths

• Offersnon-shielded(multilateral)capacitancemodelfordisplay designs

• Providescustomcornerandoverlapmodelsformoreaccurate capacitance calculation

Exact3D Field Solver

Process Data

Cell Data

Design Data

Command Data

Cell Netlists

GDS II

Technology File

Hipex NET

Hipex

Databases(Devices, Nets

and Parasitics)

SPICE, DSPF, SPEF, P2P

Netlist

Hipex Full-Chip Parasitic Extractor Product Design Flow.

SPICE Netlists with Parasitic RC

DSPF, SPEF, P2P Netlist

Hipex Parasitic Resistance Extraction Hipex Parasitic Network Distribution

Hipex-CRC Network Reduction Tool

• Drivenbyrule-basedtechnologyfile

• Back-annotatestheschematicnetlistwithparasiticresistors

• SupportsDistance/Widthprocessdeviations

• ProcessesL,T,Cross,andBendresistorshapes

• Acceptsuser-definedscriptsforcustomcomputingofresistance

• Usescontactover-sizingandclusteringtosimplifyresistorshapes

• Extractsnetlistwithparasiticresistorshierarchicallyforfullchip or selected nodes

• Createsincrementalresistancedatabaseonanet-by-netbasis

• Multipleextractionmodelsandequationsolversareusedforarbitraryshaperesistors

• SplitslongconductingtracksformoreaccurateRCdistribution

• Providesfield-solvermodetoobtainpreciseresistancefordifficult areas (such as regions with numerous contacts andmulti-layerbuses)

• Combinesextractednodeswithparasiticresistanceandparasitic capacitance

• Distributesbothcouplingandgroundcapacitors

• User-definedthresholdforminimumresistanceandcapacitance

• Distributescapacitorsoverparasiticresistorbodiesaccurately using stored locations

• UsesthriftyanddetailedmodelsforRCnetwork

• ResultsareoutputtoSPICE,DSPF,SPEF,P2Pnetlists

• Back-annotatesextractednetlistwithschematicnodenames

• SupportsP2Pformattopresentpernetcapacitanceandpoint-to-point resistance

• Significantlyreducesruntimeofpost-layoutandpost-routesimulations

• PerformsreductionusingTimeDomainandScattering-Parameter-BasedMacromodelingmethods

• EliminatesdanglingRCelementsandelementsboundedbyuser specified threshold; performs parallel/series merging

• Performsnetworksreductioninlineartime

• HandlesRCnetworkswithloops

• PreservestheaccuracyofsimulationforreducedRCnetworks

• SupportsSPICE,DSPF,orSPEFformats

• Customreductionbyvariationofsettings

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Hipex RC database provides visualization of parasitic elements on Expert layout view.

Hipex supports SPICE, DSPF, or SPEF formats.

HipexInputs/Outputs

Layout Files (GDSII, ELD, OA)

Technology Files (Extraction rules)

Schematic and Pre-extracted Netlists