ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
Hardware Description LanguageHardware Description Language
Presenter: Wein-Tsung ShenDate: 2005/5/20
Graduate Institute of Electronics Engineering, NTU
Outline Outline vMemory generationvImproving Timing, Area, and Power
Graduate Institute of Electronics Engineering, NTU
Process LibraryProcess Library
Announcement 94.4.1
# New version Cadence LDV tool(5.1) is available.
# New version Synopsys tool is available.
# Please use SSH to connect. Telnet is not supported.
# Cell library is at /home/raid1_1/cic/:0.18um: /home/raid1_1/cic/CBDK018_UMC_Artisan
/home/raid1_1/cic/CBDK018_TSMC_Artisan0.25um: /home/raid1_1/cic/CIC_CBDK25_V10.35um: /home/raid1_1/cic/CIC_CBDK35_V3
# For detailed CAD tools and workstations lists,please refer to http://cad.ee.ntu.edu.tw
#########################################################11:04pm up 28 day(s), 23:47, 4 users, load average: 1.07, 1.04, 1.04
Graduate Institute of Electronics Engineering, NTU
Memory generation (i)Memory generation (i)v Unix%/home/raid1_1/cic/CBDK
018_UMC_Artisan/CIC/Memory/ra1sh_1/bin/ra1sh &
Module name
words
Bit width
Operating freq.
After change, update is needed
Graduate Institute of Electronics Engineering, NTU
Memory generation (ii)Memory generation (ii)v Press Utilities->generation
menuv Just select
v Postscript Datasheetv Verilog modelv Synopsys model
v Then press generate
RA1SH.pdfRA1SH.vRA1SH_slow_syn.libRA1SH_typical_syn.libRA1SH_fast_syn.lib
Graduate Institute of Electronics Engineering, NTU
Include memory in DVInclude memory in DVvIn order to use memory model in design
vision, the library file must be transfer to synopsys database file.
v Unix%dc_shellv dc_shell> read_lib NAME.libv dc_shell> write_lib USERLIB –output
OUTPUT_FILE_NAME
Graduate Institute of Electronics Engineering, NTU
How to use memory How to use memory modelmodelvRTL/Gate level simulation: RA1SH.vvSynthesis: vDon’t include RA1SH.vvUse RA1SH_slow_syn.db instead
vModify .synopsys_dc.setupset search_path = “ . /where/ram/model/placed search_path” ;set link_library = “RA1SH_slow_syn.db $link_library” ;set target_library = “RA1SH_slow_syn.db $target_library” ;
Graduate Institute of Electronics Engineering, NTU
Outline Outline vMemory generationvImproving Timing, Area, and Power
Graduate Institute of Electronics Engineering, NTU
IntroductionIntroductionvWhen design in RTL, the designer need to be
aware of timing, power and area issues.vMeeting timing is the most critical goal in
design. Only optimize for power / area after timing is met.vSynthesis tools operate in gate level, and
cannot resolve all timing / power / area issues.
Graduate Institute of Electronics Engineering, NTU
Timing issuesTiming issuesvPerformance vLatency – How long does it take to complete
a particular operation?vThroughput – How many operations can be
completed per second?vThroughput = clock frequency / cycles per
operation
Graduate Institute of Electronics Engineering, NTU
Timing requirementTiming requirementvSynthesis tool reports timing in terms of clock
cycle times. To meet timing, the resulting throughput need to be greater than the system specification.vIn IC design industry, the design must meet
timing with margin, and using worst-case library model.
Graduate Institute of Electronics Engineering, NTU
How to improve timing in DesignHow to improve timing in DesignvPipelining : Trade off latency to improve
throughputvParallelism : Execute tasks concurrently to
improve throughput
Graduate Institute of Electronics Engineering, NTU
PipeliningPipeliningvPipelining improved timing by inserting
pipeline registers to partition tasks into sub-tasks to shorten the logic delay, thus increase the clock rate.vPipelining the data path must maintain
coherency of the data.
Graduate Institute of Electronics Engineering, NTU
fpipeline < 2 / Tmax
data_in CombLogic
CombLogic
fclock < 1/Tmax
data_inOutput
RegistersMulti-level Logicdata_out
InputRegisters
InputRegisters
PipelineRegister
OutputRegisters
data_out
Tmax
Tmax/ 2
Graduate Institute of Electronics Engineering, NTU
Graduate Institute of Electronics Engineering, NTU
Graduate Institute of Electronics Engineering, NTU
CutsetCutset based placement of pipelining based placement of pipelining registersregisters
Pipelinecutset
Not apipelinecutset
Pipelineregister
Graduate Institute of Electronics Engineering, NTU
Pipelined AddersPipelined Adders
c_outsum
b ac_inc_out
sum
b ac_in
sum[7:0]sum[15:8]
c_out c_in
b[15:8] a[15:8] b[7:0] a[7:0]
b15 a15 b8 a8 b7 a7 b0 a0
cincout
s15 s8 s7 s0
Cutset
Graduate Institute of Electronics Engineering, NTU
Choose Choose cutsetscutsets to balance to balance performance between stagesperformance between stages
b15 a15 b8 a8
b7 a7 b0 a0
cincout
s15 s8 s7 s0
Graduate Institute of Electronics Engineering, NTU
Pipelined 16Pipelined 16--bit Adder Structurebit Adder Structure
c_outsum
b ac_in
PR[15:0]
c_inb[15:0] a[15:0]
c_outsum
b ac_in
sum[7:0]
IR[24:17]
sum[15:0]c_out
clock
b[7:0] a[7:0]b[15:8]
IR[32:25]
IR[16:9] IR[8:1] IR[0]
Input Register: IR[32:0]
Pipeline Register: PR[7:0]
Output Register: OR[16:0]
PR[16:9]PR[24:17]PR[8]
a[15:8]
Graduate Institute of Electronics Engineering, NTU
Timing diagram for pipelined adderTiming diagram for pipelined adder
(4)clock
x
aLaR(1)x
bLbR(1)
aLaR(2)
bLbR(2)
aLaR(3)
bLbR(3)
x aLaRbLbR(1) aLaRbLbR(2) aLaRbLbR(3)
(1) (2) (3)
x aLbL(3) sumR(3)aLbL(2) sumR(2)aLbL(1) sumR(1)
x sumL(3) sumR(3)sumL(2) sumR(2)sumL(1) sumR(1)
(5)
IR
PR
OR
a
b
Graduate Institute of Electronics Engineering, NTU
Simulation ResultSimulation Result
Graduate Institute of Electronics Engineering, NTU
module add_16_pipe (c_out, sum, a, b, c_in, clock);parameter size = 16;parameter half = size / 2;parameter double = 2 * size;parameter triple = 3 * half;parameter size1 = half -1; // 7parameter size2 = size -1; // 15parameter size3 = half + 1; // 9parameter R1 = 1; // 1parameter L1 = half;parameter R2 = size3;parameter L2 = size;parameter R3 = size + 1;parameter L3 = size + half;parameter R4 = double - half +1;parameter L4 = double;input [size2: 0] a, b;input c_in, clock;output [size2: 0] sum;output c_out;
reg [double: 0] IR;reg [triple: 0] PR;reg [size: 0] OR;assign {c_out, sum} = OR;always @ (posedge clock) begin// Load input registerIR[0] <= c_in;IR[L1:R1] <= a[size1: 0];IR[L2:R2] <= b[size1: 0];IR[L3:R3] <= a[size2: half];IR[L4:R4] <= b[size2: half];
// Load pipeline registerPR[L3: R3] <=IR[L4: R4];PR[L2: R2] <=IR[L3: R3];PR[half: 0] <= IR[L2:R2] + IR[L1:R1] + IR[0];OR <= {{1'b0,PR[L3: R3]} + {1'b0,PR[L2: R2]} + PR[half], PR[size1: 0]};
endendmodule
Graduate Institute of Electronics Engineering, NTU
ParallelismParallelism
Graduate Institute of Electronics Engineering, NTU
Parallelism (cont.)Parallelism (cont.)
ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
Low Power DesignLow Power Design
Low power design is more and more important in today’s chip design due to
heat dissipation, packaging, and portability needs.
Graduate Institute of Electronics Engineering, NTU
Power consumption in CMOSPower consumption in CMOSvNnode is the switching activityvfclock is the clock frequencyvCL is the node capacitancevVdd is the power supply voltage
clockddLnode fVCNP *** 2∑=
Graduate Institute of Electronics Engineering, NTU
Strategy for Low Power DesignStrategy for Low Power DesignvVdd is usually determined by the chip
technology.vCL can only be minimized by back-end.vOptimize fclock and Nnode are the most practical
power reduction techniques.
Graduate Institute of Electronics Engineering, NTU
Reducing Clock FrequencyReducing Clock FrequencyvDesign with clock rate that is ‘just right’vClock GatingvSlow down clock in power saving mode
Graduate Institute of Electronics Engineering, NTU
Reducing switching activityReducing switching activityvAvoid unnecessary circuit switchingvReducing switching activity at I/O pinsvUse simple hardware if it get the job done
Graduate Institute of Electronics Engineering, NTU
Graduate Institute of Electronics Engineering, NTU
Graduate Institute of Electronics Engineering, NTU
Area Issues in DesignArea Issues in DesignvArea = Cost.vDuring the design process, the designer
should be “area aware”.
Graduate Institute of Electronics Engineering, NTU