Introduction Structure and Types
Fabrication of Tri-Gate Transistor
References
Tri-Gate Transistors:
Tri-gate transistors (i.e., fully depleted silicon-on-
insulator & integrated transistor consisting of three gates)
are basically novel advanced MOS devices which are
developed for prolonging the functionality of CMOS
technology (transparency & flexibility) and for current
down-scaling trend.
Todays’ technology is altering very swiftly to maintain
stride with Moore’s law for which the dimension of cell
is further minimized and additional scaling of transistor
is being done for better packaging on a given chip.Name of the company: Global Foundries
Location: Albany, NY
Interviewee: Mr. Rajesh Asnani
Designation: Member of Technical Staff, TD
Integration Engineering
In order to improve the short channel resistance and
stability, a tri-gate transistor is required. The
configuration of tri-gate transistor is designed in a way
that they are fully depleted due to which even before
reaching the threshold point; the complete Silicon present
under the gate electrode is depleted of carriers.
Tri-gate transistors have shown expressively developed
electrostatics in terms of sub-threshold slope, drain
induced barrier lowering & better scalability as compared
to planar single gate transistors.
The tri-gate transistor structure employs low aspect
channel ratio to deliver conventional conduit for CMOS
scaling to the end of roadway [1] & [2]. This structure
provides the benefits of tri-gate transistor with the
advantages of planar MOSFET. The magnitudes of tri-
gate transistor design are very flexible in comparison
with single gate transistors and double gate transistors. It
also plays a vital role in defining the V-I characteristics
[3] & [4].
There are hundreds of chips inside every wafer of
Silicon. Every transistor comprises of two sections- drain
and source. In fact, every chip consists of millions of
transistors.
There are conducting conduits on the three verges of the
vertical fin in a tri-gate transistor. It consists of a single
gate electrode on the top and two gate electrodes on the
verges. Due to this structure, the control of the gate
improves in such a way that even in the “ON” state
current flows through it as much as possible.
Also in the “OFF” state, the current flow is practically
zero. This phenomenon increases the switching rate
between the two states, which outcomes in an enhanced
performance for the transistor [7].
Adding to it, the performance benefit can be provided by
the control of the nominal width of the conducting
conduit [8]. This width is higher in tri-gate transistor
because it increases in the 3D structure. This is the major
variance between 2D/ Planar and 3D/ tri-gate transistors.
But the overall footprint of the transistor remains
constant which is illustrated in Figure 1.
What kind of Tri gate transistors are manufactured
in your industry and what are their applications in
appliances?
Answer: FinFET and UTB (Ultra-Thin Body) FET are
the most common multi-gate transistors manufactured
by semiconductor foundries. These devices show
enhanced gate control due to inherent better
electrostatic compared to conventional planner FETs.
FinFETs are 3-D devices with gate wrapped on three
sides of the channel, which provides higher drive
currents in the same footprint. This is the reason
FinFETs are mostly used in high-performance chips
like GPU (Graphical-Processing-Unit) for smartphones
and high-frequency data serializers chip used in data
centers. On the other hand, UTBFETs provide
flexibility to tune threshold voltage using back gate
bias, enabling transistor to operate in low leakage
mode, which is essential for low-power IoT (Internet-
of-Things) applications.
Moreover, UTBFETs are promising candidates for
integrated RF & SoC applications because of its lower
parasitics (like fringe capacitance and gate resistance)
and non-volatile memory integration.
How reliable and efficient are these Tri gate
transistors? What kind of problems are you facing
with these transistors? How do you mitigate these
problems?
Answer: FinFETs and UTBFETs show very efficient
and reliable operation in their respective field of
applications. However, for SoC (System on Chip)
applications, the industry needs to integrate Logic,
Analog, RF, Memories (Volatile and non-volatile)
components on the same chip. FinFET suffers from
high parasitic capacitance and gate resistance, which
makes it less attractive for RF applications. On the
other hand, UTBFETs suffers from parasitic leakages
(like GIDL, Gate Leakage, Impact Ionization) and
high variability due to very thin silicon channel and
mechanical stress. Moreover, reducing cost is
challenging for both technologies, FinFETs require
higher mask counts, whereas UTBFETs need
expensive SOI wafer.
The industry is still exploring ways to mitigate these
issues. Further scaling of these transistors poses more
challenges in reducing parasitics and controlling
variability.
Are the current transistors being replaced by an tri-gate
transistor which is more reliable and efficient than the
present ones you are using?
Answer: Tri-gate transistors have successfully replaced
conventional planner transistors for high-performance
mobility applications and low-power IoT applications. GAA
(Gate-All-Around), nanowire, pillar FETs are Tri-gate
transistors which are being considered as future
replacements.
What would be the future of tri gate transistors in terms
of application?
Answer: Tri-gate transistor will continue to improve its
performance and cost with the introduction of new
technologies (like Extreme-ultra-violate (EUV)
lithography) and circuit techniques (like dynamic
performance tuning).
Also, increase the level of integration will help these
transistors to proliferate into the wider range of applications
like automotive sensors, augmented reality, virtual reality
and IoTs.
The fabrication development for tri-gate MOSFET and
2D/ planar MOSFET are analogous in general. The
fabrication procedure for tri-gate transistor is shown
below in Figure 3. Usually the process is started by
configuring SOI in order to minimize the parasitic
capacitance. For electronic devices containing RF
compels, SOS (Silicon on Sapphire) is applied.
As we can see in the Figure 3 from step (a) to step (d),
firstly a layer of insulator is applied at the start of process.
We begin with SOI which is the most considered step
used for tri-gate MOSFET.
Then, coating process takes place using a positive photo
resist layer. After that ultraviolet (UV) light illumination is
done followed by chemical removal of solvable regions as
a result of UV radiance -lithography.
Subsequently, one more chemical solvent is applied
towards the surface of wafer to etch the regions which are
not covered by photoresist followed by etching the
remaining photoresist. This is shown in Figure 3 (e).
Next, coating of previous configuration with polysilicon is
done in order to develop a gate electrode, transiting via
planarization phase and then it terminates with what
which is showed in Figure 3 (f).
Afterwards, a layer of photoresist is applied. Followed by
it, masking via lithography is done on top of it and then
removal of solvent by a chemical reactant is done which
reacts only with vulnerable region of gate electrode. Here
we obtain a tri-gate MOSFET (SOI).
[[1] Xin Sun, Qiang Lu, V. Moroz, H. Takeuchi, G. Gebara,
and J. Wetzel, “Tri-gate bulk MOSFET design for CMOS
scaling to the end of the roadmap,” IEEE Electron Device
Letters, vol. 29, no. 5, pp. 491-493, May 2008.
[2] F. Lime, and B. Guillaumot, “Investigation of electron
and hole mobilities in MOSFETs with TiN/HfO2/SiO2 gate
stack,” Proc. of 33rd Int. Conf. on European Solid State
Device Research, 16-18 Sept. 2003, pp. 247-250.
[3] S. Kubicek, J. Chen, A. Ragnarsson, R. J. Carter, V.
Kaushik, and K. De Meyer, “Investigation of poly-
Si/HfO/sub 2/gate stacks in a self-aligned 70 nm MOS
process flow,” Proc. of 33rd Int. Conf. on European Solid-
State Device Research, 16-18 Sept. 2003, pp. 251-254.
[4] B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland,
B. Jin, J. Kavalieros, T. Linton, R. Rios, and R. Chau, “Tri-
gate fully-depleted CMOS transistors: fabrication, design
and layout,” Proc. of Symp. on VLSI Technology, Digest of
Technical Papers, 10-12 June 2003, pp. 133-134.
[5] M. Saitoh, Y. Nakabayashi, K. Ota, K. Uchida, and T.
Numata, “Performance improvement by stress
memorization technique in trigate silicon nanowire
MOSFETs,” IEEE Electron Device Letters, vol. 33, no. 3,
pp. 8-10, Jan. 2012.
[6] Nader Shehata, Abdel-Rahman Gaber, Ahmed Naguib,
Ayman E. Selmy, Hossam Hassan, Ibrahim Shoeer, Omar
Ahmadien and Rewan Nabeel, “3D Mutli-gate Transistors:
Concept, Operation, and Fabrication,” Journal of Electrical
Engineering 3 (2015) 1-14.
[7] Ferain, I., Colinge, C. A., and Colinge, J. P. 2011.
“Multigate Transistors as the Future of Classical Metal-
Oxide-Semiconductor Field-Effect Transistors.” Nature
479 (7373): 310-6.
[8] Colinge, J. P. 2013. “3D Transistors.” Presented at 2013
International Symposium on VLSI Technology, Systems,
and Applications (VLSI-TSA), Hsinchu, Taiwan.
Figure 4: Fabrication Practice of Tri-Gate Transistor [6]
Interview with the Company
The interview took place as follows:
Interview with the Company
Structure and Types
Usually tri-gate transistors can also be fabricated on Silicon
on Insulator (SOI) which is also called as a standard bulk
substrate. Figure 2 explains several means by which the gate
electrode can be enveloped across the channel area of a
transistor:
Figure 2: Effective Channel width for both transistors [6]
(a) Dual-gate SOI MOSFET: Here we can clearly observe the
hard mask. It is a dense dielectric that inhibits the creation of
an inversion channel over the top of the silicon (fin). The
controllability of the gate is applied on the conduit from the
edges of the device.
(b) Tri-gate SOI MOSFET: The control of the gate is applied
on the conduit from all three edges of the device (left, right
and top).
(c) Gate SOI MOSFET: The control of the gate is advanced
over tri-gate MOSFET which is shown in (b) because the
electric field across the edges of gate applies some control on
the bottommost edge of the channel.
(d) Gate SOI MOSFET: The control of the gate on the
bottommost edge of the channel is much better than –gate
MOSFET. The shape of the gate is represented by names like
(–gate and –name).
(e) SOI MOSFET (gate all around). The control of the gate is
applied on the conduit from all four edges of the device. In
this scenario, under the channel of silicon; no submerged
oxide exists.
Fabrication of Tri-Gate Transistor
After that, we do more etching to remove the regions
that are not covered by the unsolvable photoresist after
UV illumination and then residual photoresist
covering the gate region is etched out. The finished
structure is shown in Figure 3 (g) to (h).
Lastly process of doping occurs to profile the fins of
source and drain as illustrated in figure 3 (i).
Structure and Types
(e) SOI MOSFET (gate all around). The control of the
gate is applied on the conduit from all four edges of the
device. In this scenario, under the channel of silicon; no
submerged oxide exists.
Overall, in all above cases we see that the devices are
manufactured by using SOI substrate. This substrate
consists of thin single silicon crystal deposit on the
upper part of insulator i.e., silicon dioxide. Tri-gate
MOSFETs are designed using wafer of silicon instead of
SOI. This is shown in Figure 2 (f) where the channel is
linked to silicon substrate without any insulator between
them.
Figure 3: Different Forms of Tri-Gate Transistors [6]
Figure 1: Tri-Gate Transistors [6]