Steve Worm – LCFI DESY PRC - May 10, 2007
LCFI Collaboration Status Report
Steve WormRutherford Appleton Laboratory
for the Linear Collider Flavour Identification (LCFI) Collaboration
Steve Worm – LCFI DESY PRC - May 10, 2007
Outline
o LCFI activities– Vertex software package– Column-parallel CCDs: CPC2– Clock drive and CPC-T test structures– Readout chip development– ISIS developments and results– Mechanical studies
Steve Worm – LCFI DESY PRC - May 10, 2007
Vertex Package - Overview
o Goals– Develop tools for the evaluation and optimisation of the vertex detector– Study benchmark processes; optimise the vertex detector
o Package design overview– Vertex package interfaces to MarlinReco framework– Framework consists of software processors, enabled and configured via
XML– Input: LCIO events– Processors:
1. Track selection cuts for ZVTOP, flavour tag, vertex charge
2. IP fit processor3. ZVRES4. ZVKIN
– Output: dedicated vertex class in LCIO format, with vertex information, flavour tag inputs, NN flavour tag output and vertex charge
Big step towards full MC simulation and reconstruction (MOKKA+MarlinReco)
5. Jet flavour MC truth information6. Calculation of NN input variables7. Training NN for flavour tag8. NN outputs from trained nets9. PlotProcessor for standard plots
Steve Worm – LCFI DESY PRC - May 10, 2007
Vertex Package - Comparisons
o Example plots: Purity vs. Efficiency– Compares well with SLD/Fortran algorithm– Analysis at Z-peak energy with fast MC (left) and full Geant4 MC (right)– Excellent agreement with fast MC (identical inputs)– Very good agreement also with full MC (dependant on tracking input
chosen)
Filled: LCFI (c++, MARLIN, fast MC)
Open: previous (Fortran, fast MC)
c
c (b-bkgr)
b
Filled: LCFI (c++, MARLIN, MOKKA full MC)
Open: previous (Fortran, Brahms full MC)
E. Devetak, M. Grimes, S. Hillert, B. Jeffery
Steve Worm – LCFI DESY PRC - May 10, 2007
Vertex Package - Comparisons
o Joint probability and PT-corrected vertex mass– Shown are the two most important flavour tag inputs– Excellent agreement between LCFI code and Fortran result– Details in recent LC Note
LCFI code
FORTRAN
LCFI code
FORTRAN
Steve Worm – LCFI DESY PRC - May 10, 2007
Vertex Package - Verification and Status
o Verification Procedures and Results– Stage 1: Comparisons between SGV and MARLIN using identical inputs– Stage 2: Same events passed through full MC simulation in MOKKA
– Grid sample creation and MarlinReco debug in collab with MPI Munich, DESY – Compare MARLIN (MOKKA input), MARLIN (SGV input), and BRAHMS (TESLA
TDR)– Profiling with Valgrind to check for memory leaks, improve performance– Preliminary results: MARLIN (c++) slightly outperforms SGV (Fortran)
o Status– Fully functional, ~20,000 lines of c++ code– Released ~two weeks ago; available from the ILC software portal– Considered a ‘highlight’ of the ILC Software Workshop (2-4 May)
o After release– Tutorials for new users (starting soon)– Move to full tracking (currently use simplified tracking “cheaters”)– Move to more realistic vertex detector geometry (ladders, not cylinders)– Further optimisation of cuts, parameters and algorithms
Huge effort, and now available for use!
Steve Worm – LCFI DESY PRC - May 10, 2007
ILC Vertex Detector Requirements
o Excellent point resolution– Small pixels: ie 20 μm x 20 μm– Close to the IP: inner radius ~1.5 cm
o Fast (low ocupancy) readout– Column-parallel CCD: readout during 1 ms beam at 50 MHz (inner layer)– In-situ Storage Image Sensor (ISIS): storage of data for readout in long
(~200 ms) inter-train gapso Extremely small material budget
– ~0.1% X0 per layer --> low power dissipation
o Overall detector geometry – Sensor+layout concept actively being developed– Pixels in 5 layers, ~109 channels
Steve Worm – LCFI DESY PRC - May 10, 2007
Column-Parallel CCDs
o Fast Column-parallel CCDs (CPCCD)– CCD technology proven at SLD,
but ILC sensors must be faster, more rad-hard
– Readout in parallel addresses speed concerns
– CPCCD’s feature small pixels, can be thinned, large area, and are fast
– CPC1: two-phase, 400 (V) x 750 (H) pixels, each 20 20 μm2
CPCCD1
“Classic CCD”Readout time
NM/Fout
N
M
N
Column Parallel CCD
Readout time = N/Fout
Bump-BondedCPCCD + Readout
Steve Worm – LCFI DESY PRC - May 10, 2007
Column-Parallel CCDs: CPC1 results and CPC2 design
o First-generation tests (CPC1):– Noise ~100 e (60 e after filter).– Minimum clock potential ~1.9 V.– Max clock frequency above 25
MHz (design 1 MHz).– Limitation caused by clock skew
o Next generation now available (CPC2):– Busline free design (two-level metal) – Large area ‘stitched’ sensor, choice
of epi layers for varying depletion depth
– Range of device sizes for test of clock propagation (up to 50 MHz)
– Large chips are nearly the right size
Level 1 metal
Polyimide
Level 2 metal
Φ2 Φ1
Top & Bottom termination
PIXELS
OAT & test field
2 x ISIS + top termination
Top & Bottom termination
PIXELSPIXELS
PIXELS
PIXELS
PIXELS
2 x ISIS + top termination
OAT & test field
PIXELS
PIXELS
PIXELS
PIXELS
PIXELS
PIXELS
PIXELS
PIXELS
PIXELS
PIXELS
PIXELS
PIXELS
PIXELS
PIXELS
PIXELS
PIXELS
Top & Bottom termination
Top & Bottom termination
Top & Bottom termination
Top & Bottom termination
Top & Bottom termination
Top & Bottom termination
Top & Bottom termination
Top & Bottom termination
OAT & test field
OAT & test field2 x ISIS + top
termination
2 x ISIS + top termination
2 x ISIS + top termination
2 x ISIS + top termination
2 x ISIS + top termination
PIXELS PIXELS
Top & Bottom termination
Top & Bottom termination
Top & Bottom termination
2 x ISIS + top termination
Top & Bottom termination
2 x ISIS + top termination
2 x ISIS + top termination
Available fields
Active Device
CPC2 Wafer
CPC2-709.2 cm
Steve Worm – LCFI DESY PRC - May 10, 2007
CPC2: Next generation CCD
o CPC2: second generation Column-parallel CCD– Single-metal: (100 Ωcm @ 25 µm and 1.5 kΩcm @ 50 µm) – 2 more wafers received with 2-level
metal (busline-free) – Busline-free variant designed for
50 MHz operation– Another 10 wafers in pipeline
Busline-free design a big step!
CPC2-70
CPC2-40
CPC2-10
ISIS teststructures
Busline-free CPC2
Steve Worm – LCFI DESY PRC - May 10, 2007
Busline-Free CPC2 - First Results
o First test results from high-speed, double-metal CPC2-10– Clear X-ray hits at up to 45 MHz despite significant clock feed-through– Transformer drive (shown) is challenging due to numerous parasitics
Major result for LCFI (but that’s not all)…
55Fe source removed
X-ray hits
CCD output (2-stage source follower), ~2 Vpk-pk clocks
Steve Worm – LCFI DESY PRC - May 10, 2007
Busline-Free CPC2 - First Results
o Works at very low clock amplitude– Clock amplitude for plot below is only 0.4 Vpk-pk
– Significant noise induced from clock – Low clock due to very low dose inter-gate implant (not a resonance
effect)– Further tests to use CMOS-based drive chip (CPD1)
Steve Worm – LCFI DESY PRC - May 10, 2007
CPC2+CPR2 Hybrid Assemblies
o Tests on bump-bonded assemblies have started– Two wafers-worth of bonded assemblies
received– First response to X-rays observed (below)– Not all has gone smoothly… 31
0
5
10
15
20
25
Time700200 225 250 275 300 325 350 375 400 425 450 475 500 525 550 575 600 625 650 675
ADC outputADC output
55Fe signal
T. Woolliscroft
Steve Worm – LCFI DESY PRC - May 10, 2007
Cig
Cs
Cs
2Cig
Cs
Cs
2Cig
Phase1
Phase2
Phase1
Phase2
Capacitance Reduction Ideas for CCDs
o High capacitance CCD is challenging to drive– 40 nF and ~2V clocks @ 50 MHz… >20 amps!
o Working to reduce capacitance (and drive voltage)– Inter-gate capacitance (Cig) is dominant; depends on gate and overlap
sizes– New sensor designs (open phase, pedestal gate, and shaped channel)
can reduce Cig by factor of ~4?
New test structure to test these designs - production starting at e2v
Open phase CCD
Steve Worm – LCFI DESY PRC - May 10, 2007
Clock drive for CPC2
o Transformer-based driver– Designed for 2 Vpeak-to-peak at
50 MHz and 40 nF (ie for CPC2-40)– Planar air-core transformers on 10
layer PCB, 1 cm2
– Parasitic capacitance and inductance of bond wires a major effect
– Works with “busline-free” CPC2
o CPD1 driver ASIC– Designed for either large or small
sensors: 40 nF/phase at 50 MHz or 127 nF/phase at 25 MHz
– One chip drives both phases with 3.3V clock swing, 21 amps/phase
– 0.35m CMOS process, 3x8 mm2
Transformers
CPD1
Steve Worm – LCFI DESY PRC - May 10, 2007
CPD1 Driver ASIC
CPD1 works well!
o Features– Three separate modes for operation
over a wide range of frequencies – Bias circuitry, local decoupling
capacitance, control logic – Designed to provide >2V peak-to-peak
at up to 50MHz
o Testing results – Control circuitry works fine– Integrated capacitive load works well– Tested in package (inductance limited)– Full testing started in dedicated board;
internal (2 nF) and external (40 nF) loads
Slew rate in slow mode Rise time: 50ns, 2s, 4s
PH1
PH2
PH1-Ph2
2nF load, Fast Mode, 25 MHz
Steve Worm – LCFI DESY PRC - May 10, 2007
Readout Electronics: CPR2 Readout Chip
o Designed to match the Column Parallel CCD (CPC2) – 20µm pitch, maximum rate of 50MHz– 5-bit flash ADC, on-chip cluster
finding – Charge and voltage inputs
o Features for the CPR2 include– Cluster Finding logic, Sparse read-
out– Better uniformity and linearity – Reduced sensitivity to clock timing – Digital and analogue test I/O– Variety of test modes possible– 9.5 mm x 6 mm die size, IBM 0.25µm
Major piece needed for a full module
Steve Worm – LCFI DESY PRC - May 10, 2007
CPR2a Readout ASIC
o CPR2 Readout ASIC: Works, but deadtime and some data loss for large clusters
o CPR2a Readout ASIC: – Pad-compatible, but with significant changes to digital – Implemented features: Increased front-end memory depth, clustering
now 4x6, compact layout, no repetition of time stamp, per-column threshold
– Next steps: Flag for corrupt or lost data, more digital outputs, optimisation of analogue stages
Steve Worm – LCFI DESY PRC - May 10, 2007
In-Situ Storage Image Sensor
o ISIS Sensor details:– CCD-like charge storage cells in each pixel, CMOS or CCD technology– p+ shielding implant (or epi) forms reflective barrier
o Operational Principles:– Charge collected at photogate, transferred to storage pixel during bunch train– 20 transfers per 1 ms bunch train– Readout during 200 ms quiet period after bunch train
p+ shielding implant
n+buried channel (n)
Charge collection
p+ well
reflected charge
reflected chargeHigh resistivity epitaxial layer (p)
storage pixel #1
sense node (n+)
row select
reset gate
Source follower
VDDphotogate
transfer gate
Reset transistor Row select transistor
outputgate
to column load
storage pixel #20
substrate (p+)
Steve Worm – LCFI DESY PRC - May 10, 2007
ISIS Properties and Status
o ISIS advantages:– Low frequency clock -> easy to
drive– 20 kHz during capture, 1MHz
readout– ≈100 times more radiation hard
(fewer charge transfers)– More robust to beam-induced RF
pickup
o Process and Status:– Combines CCD and active pixel
technologies – Deep implant or custom epi needed– Investigating CMOS and CCD
vendors
Proof of principle device (ISIS1) manufactured
RG RD OD RSEL
Column transistor
On-
chip
logi
c
On-
chip
sw
itche
s
Global Photogate and Transfer gate
ROW 1: CCD clocks
ROW 2: CCD clocks
ROW 3: CCD clocks
ROW 1: RSEL
Global RG, RD, OD
5 μm
Steve Worm – LCFI DESY PRC - May 10, 2007
The ISIS1 Cell
o Array and Cell details– 16x16 array of ISIS cells with 5-pixel
buried channel CCD storage register– Cell pitch 40 µm x 160 µm– No edge logic (pure CCD)– Chip size 6.5 mm x 6.5 mm
Output and reset transistors
Photogate aperture (8 μm square)
CCD (5x6.75 μm pixels)
OG RG OD RSEL
OUT
Column transistor
Steve Worm – LCFI DESY PRC - May 10, 2007
o Simulation of Charge Transfer– Full 2D simulation in ISE-TCAD– Count signal e- trapped in pixel– CPU-intensive and time
consuming– Simple analytical model gives
similar results– Window of low charge transfer
inefficiency (CTI) between -40 °C and 0 °C for 50 MHz
Very important for operation… must confirm with data!
-0.44eV trap
-0.17eV trap
Radiation Damage Effects in CCDs
Steve Worm – LCFI DESY PRC - May 10, 2007
Ladder Prototyping
o Ultra-low mass ladders a significant challenge– 0.1% X0 per layer: active silicon sensor
thickness and not much else!– Low power, low flow rate gas cooling only
o Foam structures being investigated– Low mass, good rigidity– Silicon+foam or Si+foam+Si sandwich– Good thermal match for SiC and RVC
o Silicon Carbide (SiC)– SiC as ladder support looks promising
– Built 8% SiC on 25 μm Si 0.16 X0
– 0.1 X0 possible with ~5% foam
– Ladder profiles with small T steps look good (see plots at right)
o Reticulated Vitreous Carbon (RVC)– RVC ladder currently under test
– ~3% foam and 2x25μm Si ~0.1 X0
– Sandwiched structure for rigidity
Steve Worm – LCFI DESY PRC - May 10, 2007
Cooling Studieso Goals
– Develop design capability- a predictive tool, not for layout optimisationo Gas cooling test stand
– Major update with Perspex (insulating) ladders and end plates now complete
– Data collection underway with upgraded softwareo Simulation of test stand
– Upgraded software, computing power– New CFD model includes solid domain– Still optimising inlets, heater elements
heaterelements
coolinginlets
Steve Worm – LCFI DESY PRC - May 10, 2007
Conclusions
o Physics Studies– Vertex package released and available for public– Important for ILC vertex-related physics studies
o Column-parallel CCD– Second generation high speed CCD: CPC2 working at 45 MHz– Active programme of capacitance and clock amplitude reduction– Clock driver under development (CMOS and transformer)– Third-generation readout ASIC available, new one under design
o In-situ Storage Image Sensor– Proof of principle device works– Design of small-pixel ISIS2 in progress
o Mechanical Studies– Active programme of ladder mechanical prototyping– Cooling test stand and simulation work converging
LCFI making excellent progress towards meeting the challenges of the ILC