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Motivation: MOSFET scaling will end
ideal long-channel ID(VG) makes MOSFET a perfect
switch
subthreshold slope S > 2.3kT/q ~ 60 mV/decade
MOSFET degraded by short-channel effects:
degraded S, DIBL
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Downscaling difficulties
ultimate scaled planar transistors [Doris et al, 2002]
ID
(A/m)
VD= 1.2 V
VD= 0.05 V
EOT= 1.2 nmLG= 6 nmtSi= 48 nm
VG (V)
short channel effects, degraded subthreshold slope S
reduced current drive due to series resistance
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Can tunneling help?
S/D leakage
gate leakage
annoyance in standard MOSFETs
BUT
not apriori constrained by S= 60 mV/decade
can provide highly nonlinear characteristics
FET
log J
VG
TT (tunneling
transistor)
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INTERBAND TUNNELING DEVICES
Esaki tunnel diode (heavily-doped pnjunction) [Esaki, 1958]
p+
n+
current ITUN ~ strong (exponential) function of electric field F
note the same tunneling mechanism in reverse bias
norigorous expression for ITUNin indirect materials (e.g. Si)
reverse
bias
forward
bias
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INDIRECT TUNNELING
direct tunneling conserves energy Eand momentum k
analytically tractable for a known barrier shape U(z)
simulators (e.g. Silvaco) use empirical expressions
quantitatively unreliable !!
Indirect material
(like Si !!)
means
!k"0E
k
EC
EV
E
k
Can interband tunneling be useful in end of roadmapdevices?
E
T(E) ~ e2#[2m*(U(z)E)/h2]1/2 dz
U(z)
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VE2
IE
IB
IC
VC
MULTIEMITTER BIASING
forward bias
injectionreverse bias
tunneling
note that tunneling base current is indirect (Si/SiGe)
so no quantitative evaluation is possible
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output current level
for a given emitter V
(with V = 0, grounded)
VEB
schematic
backwarddiode I(V )
IB
-IB
VE2
EB
E2
E1
forwardturn-onvoltage
GAIN AND TRANSCONDUCTANCE
VE2
IE
IB
IC
VC
IC= IE
VE2splits between forward and reverse bias on EB junctions
small tunneling current IBcontrols IE1~ IC= $IBoutput current
gain $depends on emitter-base parameters (large bin HBTs)
transconductance IC(VE2) depends on emitter-base I(VEB)
if VE1= VE2no currentflows (floating base transistor)
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FIRST IMPLEMENTATION
Emitter-base I(VEB)
n-Si ~ 3x1018
p-SiGe ~ 4x1019
Transistor characteristics
IB= 010 A
$~ 400
floating base
multiemitter biasing indistinguishablefrom standard HBT
floating second
emitter
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DEVICE OPTIMIZATION
(a) Heavier E-B doping
IC(IB,VC) curves
IB= 05 A
~ 1300
IC(VE2,VC) curves
VE2= 0.61 V
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ADDED LOGIC FUNCTIONALITY
0
2
4
TIME
4.23 mA4.31 mA
0.14 A 0
IC
(mA)
VE2
VE1
1
0
1
0
(a)
0
2
4
6
IC
(mA)
TIME
(b)VE1
VE2
VE3 10
10
10
0
6.425.65
5.22
2.24 2.362.90
60 dB at room temperature)
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VLSI COMPATIBILITY
BiCMOS industry process (Agere Systems) withselective SiGe base epitaxy
Comparable multiemitter HBT process
p-SiGe base
collector
collector
KEY PROBLEM:
no predictive device model for circuit designer
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IDEAL TUNNELING DIODE STRUCTURE
surface-controlled avalanche transistor [Schockley, 1964]
lateral interband tunneling transistor on thin SOI[Zaslavsky and Luryi, 1999]
thin Si channel (< 50 nm, low CSD); ultra-short gate (low CG)
different scaling rules (no channel!) implications unknown
complicated electrostatic problem for F(VG, VD)
in reverse bias (no minority carrier injection,
low capacitance) high-speed analog applications
n++
-Si p+
-Si
VG
BOX
VD
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n p
VG
ninv
COMPETING MOSFET-BASED
STRUCTURE
n-MOSFET with p-type drain [Koga and Toriumi, 1996-99]
VG control of IDreported in forward bias to maintainnegative differential resistance (NDR)
channel not needed, but requires area and adds CG
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n++(p+)-Si p+-Si
VG2
VG1
FIRST DEVICE RUN (LETI-Grenoble)
simplest possible process, no additional masks
junction obtains by counterdoping, with the drain
protected by a shifted active area mask
gate much wider than the junction depletion region
gate overlaps junction, source and drain
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shifted lithography
counterdoping of n-Si source, P = 8 keV, 5x1014cm-2
deposited gate oxide, tox= 4.6 nm, followed by in-situ
doped poly-Si gate, standard subsequent processing
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reverse bias tunneling IDshows VGcontrol
(either VGpolarity, VG> 0 more effective)
soft reverse bias IDturn-on
(insufficient junction doping!)
no dependence on gate length LG (as expected)
T= 300 K
LG= 0.35 m
TRANSISTOR CHARACTERISTICS
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REVERSE-BIAS TUNNELING ID(VD) vs. VG
heaviest doping (np 1020:6x1019)
VGcontrol of IDexists, but requires large VG
REVERSE BIAS VD (V)
TU
NNELING
ID
A
REVERSE BIAS VD (V)
TUNNELING
ID
A
0.0 0.4 0.8 1.2 1.6 2.0
0.0
0.2
0.4
0.6
0.8
1.0 5V
4.8V
4.6V
4.4V
4.2V
4V
3.5V
VG= 0
0.0 0.4 0.8 1.2 1.6 2.0
0.00
0.05
0.10
0.15
0.20
0.25
VG
= -3.5 V
-5V
-4.8V
-4.6V
-4.4V
-4V
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SIMULATIONS FOR ABRUPT pnJUNCTION
2.0x106
4-2 0 2-4
3.0x106
4.0x106
5.0x106
VG(V)
MAX
(V/
cm)
real double-implanted pnjunction
ideal abrupt 4x1019pnjunctionin 10 nm S i channel
subthreshold S< 60 mV/decade for low VD
taking empirical ITUN(VD,VG) at face value:
Q. Zhang et al, IEEE EDL 27, 297 (2006)
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MULTIEMITTER TUNNELING HBT
- works well, enhanced logic
- requires BiCMOS process
GATED INTERBAND TUNNELING DIODE
- works in principle
- becoming popular in industry Infineon is publishing counterdoped FET designs
INTERBAND TUNNELING MODEL ***key issue
- better modeling/simulation needed
Recommended