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MOS InvertersDigital Electronics - INEL 4207
Prof. Manuel Jimnez
With contributions by:Rafael A. Arce Nazario
Objectives: Introduce MOS Inverter Styles
Resistor LoadEnhancement Load Saturated / LinearDepletionComplementary (CMOS)
Perform DC analysis of the circuits
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Operation regions(Enhancement) VGSVT ,VDS>VGS-VT: saturation
VGS>VT ,VDS
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Operation regions
VGSVT ,VDSVT ,VDS>(VGS-VT): saturation
MOS Devices
0DI
2)(2
TGSD VVk
I =
[ ]2)(22
DSDSTGSD VVVVk
I =
)1()(
2
2DSTGSD VVV
kI +=
K=device transconductance = channel-length modulation
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VOH=VDD
VM
VOL
VT VM VOH=VDD
Vout
Vin
Vout=Vin
Vout=Vin-VT
VIL VIH
MOS Inverter - Resistor Load
IN
OUT
VDD
RL
|VGS| VT device conducts with resistance RON
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MOS Inverter - Resistor Load : Parameters - VIL
( ) ( )
( )
LTIL
LTin
D
out
in
D
in
out
L
L
outDD
outout
D
D
out
TinTin
inin
D
D
out
in
D
in
out
kRVV
RVVkdI
dV
dV
dI
dV
dV
RR
VV
dV
d
dV
dI
dI
dV
VVkVVk
dV
d
dV
dI
dI
dV
dV
dI
dV
dV
1
1
2
1
11
2
+=
===
=
=
=
==
==
( )
1
2
2
=
=
in
out
L
outDDTGS
dV
dV
R
VVVV
k
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[ ]( )
2
0.1
0.1
Tinout
DSTGS
DS
D
DS
GS
D
in
out
D
out
in
D
in
out
VVV
VVVk
kV
dI
dV
dV
dI
dV
dV
dI
dV
dV
dI
dV
dV
=
===
==
( )[ ]L
outDDoutoutoutTIH
R
VVVVVVV
k =
22
2
( )L
TIH
L
DDTIHTIHTIH
R
VV
R
VVVVVVVk
222
1
2
2
=
solve quadratic expression by VIH
MOS Inverter - Resistor Load : Parameters - VIH
substitute in (1)
(1)
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VM
( )
( )
( ) ( )
L
TDDT
L
TDDL
TM
L
DDT
L
TMM
MDD
TM
DSDDRTGSDS
kR
VVV
kR
VVkRVV
kR
VV
kR
VVV
R
VVVV
k
RVVIVVkI
+
++=
=
+
=
===
2121
021
2
2
2
22
2
2
MOS Inverter - Resistor Load : Parameters - VM
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Effect of RL on VTC
As RL increases
Butputting a larger resistance would also mean: larger resistor length
greater switching delays
main disadvantage of resistor load:
occupies to much chip area (10s or 100s times the area of a singletransistor!)
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Using enhancement transistors as load devices
Justification: Since VLSI resistors occupy to much chip spaceuse transistor in either saturation or linear region instead of
resistor
VDD
Vin
Vout
VDD
VinVOUT
VGG
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VDD
Vin
Vout
Enhancement NMOS with VGS = VDS
while VOUT < VDD VTthe transistor will be in saturationbecause VGS > VT & VDS > VGS-VT
If VOUT tries to go above VDD-VT ,transistor goes cutoff(because VGS < VT)
Saturated enhancement load
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INV
OUTV
= VT
VIL VIH
VOH
VOL
Slope = -1
Slope=
=VDD
- VT(V
OH)
RK
load
inverterR
LWLWK
)/()/(=
VDD
Vin
Vou
Saturated enhancement load - VTC
FFSBTT VVV 220 ++=
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Enhancement NMOS with VGG > VDD+VT
since VDS = VDD-VOUTand VGS = VGG-VOUT > VDD+VTVOUT VDS< VGS- VT
since VGS > VT :the load is always on linear region
VDD
VinVOUT
VGG
Linear enhancement load
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Pro: VOH = VDD
Disadvantage: Additional voltage source KR must be even largerthan for saturated load for
decent slope
Linear enhancement load - VTC
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VDD
Vin
Vout
Depletion NMOS with VGS = 0
VGS > VT : always conducting
Depletion load
Good: VOH
= VDDno additional V source
Bad: addit. fab. process steps
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Complementary MOSFET inverter
Features:
Complementary MOS (CMOS) Inverter
analysis makes use of both NMOS andPMOS transistors in the same logic gate.
+ All static parameters of CMOS invertersare superior to those of NMOS inverters
+ CMOS is the most widely used digitalcircuit technology in comparison to otherlogic families.
lowest power dissipation highest packing density
-Increased process complexity (to provide
isolated transistors of both polarity types)
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Complementary MOSFET (CMOS) inverter
S
D
S
D
Intuitively:VIN
0NMOS open ckt. (VGSn VTp) VOUT = VDD
VOH = VDD (Good!)
VIN
VDD
NMOS conductingPMOS open ckt.VOUT = 0
VOL = 0 (Great!)
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1. PMOS linear, NMOS off
2. PMOS linear, NMOS sat
3. PMOS, NMOS both sat
4. PMOS sat, NMOS linear
5. PMOS off, NMOS linear
CMOS inverter - VTC
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1
2
VOH=VDD
VM
VTn VM VOH=VDDVOL=0
Vout
-VTp
3
4
5
VDD-VTp
VIN
=VTn
+
2
PMOS linear, NMOS saturation
RegionCMOS inverter Region 2
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NMOS linear, PMOS saturation
CMOS inverter Param. Calculation Example
Calculate VIH
2|)||(|2
TpGSp
p
Dp VVk
I =
[ ]2)(22
OUTOUTTnIHn
Dn VVVVk
I =
)/(1
|)|)(/(2
1)(
)(
1
np
TPDDnpTnOUT
IH
TnOUTIHn
TpIHDDpOUTn
in
out
DnDp
out
in
DnDp
in
out
kk
VVkkVVV
VVVk
VVVkVk
dV
dV
dIdIdV
dVdIdI
dVdV
+
++=
=
+
=
=
=
Substitute in (1), then solve for VOUT, finally obtain VIH
(1)
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NMOS & PMOS saturation
CMOS inverter Param. Calculation Example
Calculate VM
22
2
2
|)|(2
|)||(|2
|)||(|2
|)||(|2
TpMDD
p
TnMn
TpGSp
p
Dp
TnGSn
n
Dn
VVVk
VVk
VVk
I
VV
k
I
=
=
=
.. Solve for VM
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Summary
CMOS inverter most used, smallest, lowest powerdissipation, best inverter characteristics.base for more complex logic gates
Calculation of static parameters: VIH,VIL, VOH, VOL, VM.
Important: Deduce the region ofoperation of the transistors (verifylater) V
IH
, VIL
slope = -1, use chainrule to simplify calculations VTC affected by R, KR
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Recordatorio
Buscar copias de Dr. Jimenez en Reproducciones ($1-$2) Digital circuits using MOS transisitors