MonolithIC 3D Inc. , Patents Pending
MonolithIC 3D ICs
RCAT Flow
1MonolithIC 3D Inc. , Patents Pending
Monolithic 3D ICs
Using SmartCut technology - the ion cutting process that Soitec uses to make SOI wafers for AMD and IBM (million of wafers had utilized the process over the last 20 years) - to stack up consecutive layers of active silicon (bond first and then cut). Soitec’s Smart Cut Patented* Flow (access the link for video).
MonolithIC 3D Inc. , Patents Pending 2
*Soitec’s fundamental patent US 5,374,564 expired Sep. 15, 2012
Monolithic 3D ICs
Ion cutting: the key idea is that if you implant a thin layer of H+ ions into a single crystal of silicon, the ions will weaken the bonds between the neighboring silicon atoms, creating a fracture plane (Figure 3). Judicious force will then precisely break the wafer at the plane of the H+ implant, allowing you to in effect peel off very thin layer. This technique is currently being used to produce the most advanced transistors (Fully Depleted SOI, UTBB transistors – Ultra Thin Body and BOX), forming monocrystalline silicon layers that are less than 10nm thick.
MonolithIC 3D Inc. , Patents Pending 3
Figure 3Using ion-cutting to place a thin layer of monocrystalline silicon
above a processed (transistors and metallization) base wafer
MonolithIC 3D Inc. , Patents Pending 4
p- Si
Oxide
p- Si
OxideH
Top layer
Bottom layer
Oxide
Hydrogen implant
of top layerFlip top layer and
bond to bottom layer
Oxide
p- Si
Oxide
H
Cleave using <400oC
anneal or sideways
mechanical force.
CMP.
OxideOxide
Similar process (bulk-to-bulk) used for manufacturing all SOI wafers today
p- Si
MonolithIC 3D – The RCAT path
The Recessed Channel Array Transistor (RCAT) fits very nicely into the hot-cold process flow partitionRCAT is the transistor used in commercial DRAM as its 3D channel overcomes the short channel effect
Used in DRAM production @ 90nm, 60nm, 50nm nodesHigher capacitance, but less leakage, same drive current
The following slides present the flow to process an RCAT without exceeding the 400ºC temperature limit
MonolithIC 3D Inc. , Patents Pending 5
RCAT – a monolithic process flow
MonolithIC 3D Inc. , Patents Pending 6
Wafer, ~700µm
~100nm
P-
N+P-
Using a new wafer, construct dopant regions in top ~100nm and activate at ~1000º C
Oxide
MonolithIC 3D Inc. Patents Pending 7
~100nm
P-
N+P-
Oxide
Implant Hydrogen for Ion-Cut
H+
Wafer, ~700µm
MonolithIC 3D Inc. Patents Pending 8
~100nm
P-
N+P-
~10nm H+
Oxide
Hydrogen cleave plane for Ion-Cut formed in donor wafer
Wafer, ~700µm
MonolithIC 3D Inc. Patents Pending 9
~100nm N+P-
Oxide
1µ Top Portion ofBase Wafer
H+
Flip over and bond the donor wafer to the base (acceptor) wafer
Base Wafer, ~700µm
Donor Wafer, ~700µm
MonolithIC 3D Inc. Patents Pending
10
~100nm N+P-
Oxide
1µ Top Portion ofBase Wafer
Perform Ion-Cut Cleave
Base Wafer ~700µm
11
~100nm N+P-
Oxide
1µ Top Portion ofBase Wafer
MonolithIC 3D Inc. Patents Pending
Complete Ion-Cut
Base Wafer ~700µm
12
~100nm N+P-
Oxide
1µ Top Portion ofBase Wafer
MonolithIC 3D Inc. Patents Pending
Etch Isolation regions as the first step to define RCAT transistors
Base Wafer ~700µm
13
~100nm N+P-
Oxide
1µ Top Portion ofBase Wafer
MonolithIC 3D Inc. Patents Pending
Fill isolation regions (STI-Shallow Trench Isolation) with Oxide, and CMP
Base Wafer ~700µm
14
~100nm N+P-
Oxide
1µ Top Portion ofBase Wafer
MonolithIC 3D Inc. Patents Pending
Etch RCAT Gate Regions
Base Wafer ~700µm
Gate region
15
~100nm N+P-
Oxide
1µ Top Portion ofBase Wafer
MonolithIC 3D Inc. Patents Pending
Form Gate Oxide
Base Wafer ~700µm
16
~100nm N+P-
Oxide
1µ Top Portion ofBase Wafer
MonolithIC 3D Inc. Patents Pending
Form Gate Electrode
Base Wafer ~700µm
17
~100nm N+P-
Oxide
1µ Top Portion ofBase Wafer
MonolithIC 3D Inc. Patents Pending
Add Dielectric and CMP
Base Wafer ~700µm
18
~100nm N+P-
Oxide
1µ Top Portion ofBase Wafer
MonolithIC 3D Inc. Patents Pending
Etch Thru-Layer-Via and RCAT Transistor Contacts
Base Wafer ~700µm
19
~100nm N+P-
Oxide
1µ Top Portion ofBase Wafer
MonolithIC 3D Inc. Patents Pending
Fill in Copper
Base Wafer ~700µm
20
~100nm N+P-
Oxide1µ Top Portion of
Base (acceptor) Wafer
MonolithIC 3D Inc. Patents Pending
Add more layers monolithically
Base Wafer ~700µm
Oxide
~100nm N+P-