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Fault models
Stuck-at-00
1 Stuck-at-1
Reset coupling 0 0 Set coupling
10
1 1
Inversion coupling 0 1
10
Transition /0 0 1 Transition /1
ADR
0 0 Inversion coupling
1 1
01
AND bridging 0 1
0 01 0 OR bridging
1 1Neighborhood
pattern sensitive
faults (active)
0
1 0 1
1
01
Neighborhood
pattern sensitive
faults (passive)
1
1 10
0
0
Address decoder
faults ADR ADR ADR ADR
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C - algorithm
Number of steps: 10n
Fault coverage: AFs, SAFs, TFs, CFins , CFids
(w0) (r1,w0)
1
1
1
11
1
11
(r0,w1)
0
0
0
00
0
00
0
0
0
00
0
00
0 1
0 1
0 1
0 10 1
0 1
01
0 1
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
(r0,w1)
0
0
0
00
0
00
1 0
1 0
1 0
1 0
1 0
1 0
1 0
1 0
(r1,w0)
1
1
1
11
1
11
0 1
0 1
0 1
0 10 1
0 1
01
0 1
(r0)
0
0
0
00
0
00
0
0
0
00
0
00
0
0
0
00
0
00
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Checkerboard test and data retention
Designed to test refreshoperations of DRAMs
Maximizes leakage current
and detects leakage faults
Used as data retention test To be effective it must
consider address
scrambling and layout
1 0 1 0
0 1 0 1
0 1 0 1
1 0 1 0
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Data backgrounds for word memories
Multiple data backgrounds to detect coupling and
bridging faults between cells of the same word
For every pair of cells all four combinations are
checked
2 (log2w + 1) backgrounds
16 backgrounds for
128-bit wide memory
Normal and inverse
D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1
1 1 1 1 0 0 0 0
0 0 1 1 0 0 1 11 1 0 0 1 1 0 0
0 1 0 1 0 1 0 1
1 0 1 0 1 0 1 0
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Parallel memory BIST
BIST
mode
Clock System logic
Address generator
F
S
M
Data generator
Control generator
Start
Hold
Done
Fail
Memory
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Serial memory BIST
System logic
Data output
Serial outputSerial input
Address M
0 0 0 0r0 0 0 0 0
w1 1 0 0 0
r0 1 0 0 0
w1 1 1 0 0
r0 1 1 0 0
w1 1 1 1 0
r0 1 1 1 0
w1 1 1 1 1
r1 1 1 1 1
Minimal logic and routing
Longer test time
Memory
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Memory BIST collar
+
Memory BISTcontroller
To / FromTAP controller
Embedded memory BIST collar
mux address / control bus and data lines
local comparator with singlepass/fail local data generator to reduce routing
area and timing problems local address validation
Memory controller at the top level
TAP controller as test engine
Memoryarray
Functional logic
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Shared controller and parallel test
Insert collars
Connect them
through memory
test bus to memory BIST
controller
to TAP
+
Memory BISTcontroller
To / FromTAP controller
Memoryarray
+
Memoryarray
Functional logic
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Parallel memory BIST collar
Memory array
Data inAddress Data outCtrl
MBIST mode
Sin
Sout
Clock
= ?
Functional address
BIST address
Functional data
BIST data
Pass / Fail
BISTcontrol
Functionalcont
rol
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Diagnostics
Detect failing location/data during test
Should diagnose speed related defects
Two types - Hold and resume, Hold and restart
How it works?
BIST controller stops after 1 (or 2) failures Fail data is scanned out
BIST session resumes from where it stops (Hold and
resume)
BIST session restarts after fail data is scanned out(Hold and restart)
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Full-speed diagnostics
+
Memoryarray
MBIST
controller
ATERestart Diagnostic monitor
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Yield improvement with memory redundancy
Memory percentage, defect rate, and redundancy
amount affect yield
Source: Zorian, Rodgers, DATE 2002
Redundancy Yield Improvement
0
10
20
30
40
50
6070
80
90
100
0 10 20 30 40 50 60 70 80 90 100
Chip Memory Percentage
MemoryYield
Optimal
Level 3Redundancy
Level 2Redundancy
Level 1Redundancy
No Redundancy
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+
Memory BISTcontroller
Memory
Array
Redundancy and repair
Extra columns, rows, or rowsand columns
At the end of test - good,
repairable, or non-repairable
Repair data scanned out at
the end of test
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Full-Chip memory BIST integration
Assign memories to
controller
(BIST Scheduling)
Memory BIST Generation
(Generate Controller/Collars)
BISTGENERATION
Read in SOC netlist
Identify memories
Insert controllers in the design
Stitch controllers to top-level
BIST INSERTION
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Full Chip Memory BIST Control
BlockBIST Block
BIST Block
BIST
Controller
Memory 1
Memory 2
SOC
TDO
MBIST DataRegister
TDI
CLK
TM S
TCK
TRST
TAP Controller
rst_l
test_h
test_done
fail_h
Boundary Scan Register
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Programmable algorithms
Selection of algorithms
March1, March2, March3, Unique Address, Checkerboard, address jumping
Synthesizable algorithms
user defined prior to synthesis
simple language number of sequences, backgrounds, sequence elements etc.,
Programmable algorithms
defect mechanisms may not be known before fabrication
memory BIST controller implements a class of algorithms
field programmable parameters define active elements of test
sequences
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Summary
Key components of a BIST controller
algorithm controller
data background generator
address generator
comparator
Very high quality test of embedded arrays BIST controller shared across a number of memory
arrays to reduce area
BIST diagnostics helps in gathering failure
information
Built-in repair results in yield improvement
Recommended