Partial Analog Equalization and ADC Requirements in
Wired Communications
by
Amir Hadji-Abdolhamid
A thesis submitted in conformity with the requirements
for the degree of Doctor of Philosophy
Graduate Department of Electrical and Computer Engineering
University of Toronto
Copyright by Amir Hadji-Abdolhamid, 2004
I
Partial Analog Equalization and ADC Requirements in
Wired Communications
Amir Hadji-Abdolhamid
Department of Electrical and Computer Engineering
University of Toronto
Degree of Doctor of Philosophy, 2004
ABSTRACT
High-speedhigh-resolutionanalog-to-digitalconverters(ADC) are one of the major
bottlenecksin digital communicationsystems.Everyextrabit requirementin ahigh-speed
flashADC roughly doublesthe silicon areaandpower consumptionof the chip andfur-
thermore, complicates ADC design.
This thesisinvestigatesthe ADC requirementsfor wired communicationapplications
andpresentsan efficient partial analogequalization(PAE) approachto reducethe front-
endADC resolutionrequirement.Thecontributionsof this thesisincludetwo majorcom-
ponents.First,ananalyticalstudyelaboratesthebenefitof partialequalizationin termsof
ADC bit requirements.Second,animplementationof ahigh-speedPAE / ADC, combined
on a single1.8-V CMOSchip, is demonstratedandthebenefitof 2-3 bits improvementis
verified,experimentally. Moreover, theoptimizationof PAE coefficientsandthesimilarity
of 2-tapPAE to an analogfirst-orderdecorrelatoris investigated.The analyticaldiscus-
sionsincludestudyingthebenefitof PAE in basebandsystemswith bothfeedforwardand
decisionfeedbackequalizers.Similar benefitsof PAE in a passbandmodulationsystemis
also discussed as an appendix for future research direction.
Thetargetapplicationfor this thesisis 622Mb/s over a 300-mcoaxialcablefor serial
digital video data transmissions.The proposedPAE along with a 6-bit 400-MHz flash
ADC wasdesignedandfabricatedin a 0.18-µm CMOSprocess.Thefabricatedchip con-
sumes106mW of power with 34-dBSNDRat 250MHz samplingclock.For a 400-Mb/s
datatransmissionovera240-mcoaxialchannel,experimentalresultsshowedanerrorper-
formance improvement equivalent to an 8-bit-ADC system.
III
Table of Contents
CHAPTER 1 Introduction ...............................................................................................1
1.1 Motivation and Introduction .............................................................................................1
1.2 Thesis Outline ...................................................................................................................3
CHAPTER2 Background ................................................................................................7
2.1 Introduction .......................................................................................................................7
2.2 Wired Data Communication Overview ............................................................................7
2.2.1 Twisted Pairs ........................................................................................................ 7
2.2.2 Coaxial Cables...................................................................................................... 8
2.3 Digital Communication Systems ......................................................................................9
2.4 Equalization ....................................................................................................................12
2.5 Adaptive Filtering Overview ..........................................................................................15
2.5.1 Adaptation of Cascaded FIR Filters ................................................................... 16
2.6 Coaxial Cable Modeling .................................................................................................17
2.7 Summary .........................................................................................................................19
CHAPTER 3 ADC Requirements and Partial Equalization ......................................21
3.1 Introduction .....................................................................................................................21
3.1.1 Analog to Digital Conversion in Digital Communication Receivers................. 21
3.2 Quantization Noise ..........................................................................................................23
3.3 ADC Input Characterization ...........................................................................................25
3.4 ADC Resolution Requirement .......................................................................................29
3.4.1 Example and Comparison to Simulation Results ............................................... 32
3.5 ADC Bit Requirement Reduction Techniques and Partial Analog Equalization ...........33
3.6 Partial Equalizer Design .................................................................................................36
3.6.1 Optimizing the PAE Independently for Maximal equalization.......................... 37
3.6.2 Splitting an Optimum Equalizer into Analog and Digital Filters....................... 38
3.6.3 Global Optimization Using Genetic and/or Gradient Search............................. 39
3.6.4 Simulation Results and Comparisons................................................................. 41
3.7 Two-tap PAE: An Efficient Choice ................................................................................42
3.7.1 Using Decorrelation Concept for a 2-tap PAE Design ...................................... 45
3.7.2 Using the PAE Inverse in the Digital Domain ................................................... 47
3.7.3 Comparison with predictive coding systems (ADPCM).................................... 49
3.7.4 PAE Usage in FFE and FFE/DFE Architectures and Comparisons................... 52
3.8 Simulation Results ..........................................................................................................55
3.8.1 Quantization Noise Reduction Demonstration................................................... 55
3.8.2 Using 2-tap PAE in Coaxial Channel Application............................................. 56
3.9 Summary .........................................................................................................................57
IV
CHAPTER 4 Circuit Implementation ..........................................................................59
4.1 Introduction .....................................................................................................................59
4.2 Partial Analog Equalizer Design .....................................................................................59
4.2.1 Delay Line Generation Techniques.................................................................... 60
4.2.2 PAE Topology Choices ...................................................................................... 61
4.2.3 Sample-and-Hold design .................................................................................... 65
4.2.4 Non-overlapping Triple Phase Clock Generation and Digital Controls ............ 71
4.2.5 The Design of Transconductors ......................................................................... 73
4.2.6 Current amplifier and I/V converter and voltage buffer .................................... 79
4.2.7 Overall Performance and Simulation results...................................................... 81
4.3 ADC Flash Architecture .................................................................................................83
4.3.1 Comparator Design ............................................................................................ 84
4.3.2 Autozeroing Techniques .................................................................................... 90
4.3.3 ADC Reference Voltages ................................................................................... 94
4.3.4 Digital Back-end ............................................................................................... 95
4.3.5 Layout................................................................................................................. 96
4.4 Bias Circuit .....................................................................................................................97
4.5 Summary .........................................................................................................................98
CHAPTER 5 Experimental Results ............................................................................101
5.1 Introduction ...................................................................................................................101
5.2 Test Set-up and Functional Testing ..............................................................................101
5.3 Dynamic Test and SNDR Measurement .......................................................................107
5.4 Code Density Measurement and INL/DNL ..................................................................110
5.5 Experiment in a 400-Mb/s 240-m Coaxial Cable System ............................................114
5.5.1 Test Set-up........................................................................................................ 114
5.5.2 Special Considerations ..................................................................................... 119
5.6 Channel Emulator Using Arbitrary Waveform Generator ............................................123
5.7 Summary .......................................................................................................................125
CHAPTER 6 Summary and Future Research ...........................................................127
6.1 Summary and Conclusions ...........................................................................................127
6.2 Suggestions for Future Work ........................................................................................128
APPENDIX A Transconductor Circuit Analysis ........................................................131
A.1 Transconductor feedback loop analysis and lead compensation .................................131
A.1.1 No Compensation ............................................................................................ 135
A.1.2 Lead Compensation......................................................................................... 136
A.2 Transconductance Gain Expression and the Effect of the Feedback Loop .................139
APPENDIX B Global Gradient Search for PAE Optimization ..................................143
V
APPENDIX C Reduction of ADC Requirements in CAP/QAM Receivers .............147
C.1 Introduction ..................................................................................................................147
C.2 CAP/QAM Modulation ................................................................................................148
C.3 Conventional CAP Receiver ........................................................................................149
C.3.1 Front-end ADC Requirements......................................................................... 150
C.4 The Proposed Architecture ...........................................................................................152
C.5 Simulation Results .......................................................................................................153
C.6 Summary ......................................................................................................................156
REFERENCES.....................................................................................................................157
VI
VII
List of Abbreviations
ADC Analog-to-digital Converter
BER Bit error rate
CAP Carrierless amplitude and phase (modulation)
CLK Clock
DFE Decision feedback equalizer
FFE Feedforward equalizer
FFT fast fourier transform
FIR Finite impulse response (filter)
IIR Infinite impulse response
ISI Intersymbol interference
KCL Kirchhoff’s current law
KVL Kirchhoff’s voltage law
MSE Mean square error
MUX Multiplexer
NRZ Non-return to zero
PAE Partial analog equalizer
PAM Pulse amplitude modulation
PSD Power spectral density
QAM Quadrature amplitude modulation
RMS Root mean square error
RRMSE Relative root mean square error
S/H Sample and hold
SER Symbol error rate
SNDR Signal-to-noise and distortion ratio
SNR Signal-to-noise ratio
VGA Variable gain amplifier
1
CHAPTER
1.1 Motivation and Introduction
Datacommunicationsplaysamajorrole in themodernworld from theindustriesto the
everyday life. The advancementof this role in recenttimes has createdan increasing
demandfor higherdatatransmissionrates,over longerpathsandfor the lowestcost for
differentapplications.Thesecommunicationpathsvary from large distancessuchasthe
onesin wide or local areanetworks (WAN / LAN) to just a few inches,asseenin high
speed links on a printed circuit board between two chips.
The limitations of datatransferratesover differentwirelessandwired channelsare
causedby theimperfectionsof thechannels(suchascableattenuation,dispersionin fiber
optics,crosstalk andfading)andthe practicallimitations in transceiver building blocks
(suchaslinearity, noiseandclock jitter). The achievablesignal-to-noiseratio within the
availablebandwidthcanbeusedto find thetheoreticalupperlimit of thedatarateaccord-
ing to the Shannon Theorem [1].
The meansof achieving higher dataratesover band-limitedchannelsinclude using
multi-level signallinganddigital processingincludingdigital equalizationwith theaid of
an appropriatefront-end analog-to-digitalconverter (ADC). The designof high-speed
high resolutionADCs is a majorchallengein receiver design.Every extra bit requirement
in ahigh-speedflashADC, roughlydoublesthesiliconareaandpowerconsumptionof the
chip and furthermore,complicatesthe designat high speedwith regard to the effective
number of bits [2][3][4].
Introduction1
2
Communicationchannelswith largeattenuationcauselarge inter-symbolinterference
(ISI). Equalizersareresponsiblefor minimizing theISI errorby compensatingfor channel
attenuation.In thecaseof digital equalization,asISI increases,moreresolutionis needed
for the front-endADC beforetheequalizer. Using full-analogequalizersto eliminatethe
demandfor accurateADC and digital equalizationis an approachusedin many wired
communicationapplications[5][6][7][8][9]. However, therearemany practicaldifficulties
in thedesignof highspeedadaptiveanalogfilterswith largeorders,suchasdcoffset[10],
mismatcheffect [11][12] and nonlineardistortions.Thesedifficulties are aggravatedin
short channelCMOS technologiesat higherspeedsand longercablechannels.Alterna-
tively, adaptivedigital receiverswith a front-endADC offer many advantagessuchasreli-
ability andflexibility [7]. For example,digital decision-feedbackequalizers(DFE)with no
channelnoiseenhancement,digital pulseshapinganddigital clockrecoveryarefeasiblein
a systemwith anADC. Moreover, thebenefitof shrinkingCMOStechnologylies mainly
in favour of digital circuitries.Therefore,low orderpartial-analogequalizers,ratherthan
full-analogonesareexcellentcandidatesfor relaxingtheADC anddigital circuit require-
ments.
Few partial analogequalizers(PAE) have beenreported[13][14][15]. However, the
trade-off betweenthe orderof partial preprocessingand their actualeffect on the ADC
performanceenhancementhasnot beenelaborated.In this thesis,we discusstheeffect of
the numberof ADC bits or quantizationnoisein a digital communicationsystem,and
introducepossibleanalogpreprocessingasa meansto reducethe effect of quantization
noise.In low-noisechannelssuchascoaxialcables,andin high speedsystemswherelow
resolutionADCsareused,thequantizationerroris of greaterimportance.In this thesis,by
studyingtheADC requirementsandpartialequalizationeffect,anefficient two-tappartial
analogequalizeris shown to significantlyrelaxtheADC requirements.This is particularly
true for thecommunicationsystemswith channellossesgreaterthanabout20 dB at half
the baud-rate.
Thetwo-tappartialanalogequalizationapproachcanbeviewedasa first orderdecorr-
elatorwhichby reducingtheADC inputsamplescorrelationreducesthecrestfactorof the
ADC input [16]. Furthermore,thequantizationnoisein the reconstructedsignalafter the
ADC will be convertedto a lowpassshape.This lowpassshapednoiseis not enhanced
muchby theexistingequalizeraftertheADC. To considerall practicalaspectsof thiseffi-
Chapter 1:Introduction 3
cientPAE approach,a 400-MHz6-bit ADC with a flasharchitecturealongwith anadap-
tive 2-tapPAE is implementedin 0.18-µm CMOS technology[17]. Experimentalresults
demonstratethatthecombinationof partialanalogequalizationwith a6-bit ADC achieves
betterperformancethanan8-bit ADC systemfor our targetapplication.Theextra power
andareaconsumedby thePAE is 12%and17%,respectively. A varietyof circuit design
issuesthatexist in thedesignof theproposedanalogpreprocessorandthehighspeedana-
log-to-digital converter are also addressed in this thesis.
Thetargetapplicationin this thesisis 622-Mb/sdatatransmissionovera300-mcoaxial
cablewith a 4-level non-return-to-zeropulseamplitudemodulation(NRZ PAM) scheme.
Coaxialcablesarea commonphysical mediumin wired communications,applicablein
digital video transmissionandalsoasthe backboneof many networking applications.A
300-mcoaxial cablechannelcausesa considerableamountof ISI andhasa magnitude
lossof about32 dB at 155.5MHz[18]. The622Mb/s rateis compatiblewith theSTS-12
OC12standard,originally developedfor fiberopticchannels.Althoughthemajorapplica-
tion addressedhereis digital serialvideoapplicationsovercoaxialcables,theconceptand
thedesignwithin this thesiscanbeextendedto otherwired applicationsandvariousdigi-
tal serialapplicationswith large channellossand ISI. This would include readchannel
applications, high speed links on PCBs and flat panel cables.
1.2 Thesis Outline
In Chapter2, the applicationsandtheoreticalbackgroundfor this work arereviewed.
This includesan overview of wired communications,coaxial cablechannelsand serial
digital videoapplicationsandstandards.A block diagramof a digital communicationsys-
tem, comparisonof NRZ line codewith others,the variouskinds of adaptive equaliza-
tions,adaptive filtering andcoaxialcablemodelingandtheir characteristicsarethetopics
briefly discussed in the background chapter.
Chapter3 startswith a review of theeffect of ADC resolutionon theperformanceof a
basebandcommunicationreceiver. This is doneprimarily by studyingquantizationnoise
and ADC input signal characterizing.Next, a formula is developedthat determinesthe
requiredADC resolutionin agivencommunicationsystemwith adesirederrorrate.Using
theseresults,ADC bit requirementreductiontechniquesare discussed.Systemsimula-
4
tions in this part suggestthat a partial analog equalizationapproachis an efficient
approach.Consideringthe partial equalizeras splitting a digital equalizerinto separate
analogand digital filters, the optimizationof this splitting, regarding the ADC require-
mentreductionfor a givenerrorrate,is discussedandcompared.Systemlevel simulation
resultsshow thata2-tappartialanalogequalizer(PAE) is anefficient choice,comparedto
a slight improvementfor higherorderPAEs for thepurposesof ADC requirementreduc-
tion. A 2-tapPAE techniqueis comparedwith thefirst orderfeedforwarddecorrelatorand
it is shown that thecorrelationof theADC input samplesfor determiningthesinglezero
of the2-tapPAE canbeused.A performancecomparisonof a2-tapPAE in FFEandFFE/
DFE systems is presented. System-level simulation results concludes Chapter 3.
Chapter4 discussesthe issuesinvolved in the circuit implementationof the proposed
front-endfor our targetapplication.This front-endconsistsof a 2-tapPAE followedby a
6-bit 400-MHz ADC. In the beginning, several candidatetopologiesfor PAE designare
comparedfrom a circuit designpoint of view. Thechosentopologyusestwo setsof triple
interleavedsample-and-holds(S/H) followedby two variable-gain transconductors,a cur-
rentto voltageconverter, anda voltagebuffer for driving theADC input. In eachpart,the
backgroundcircuit issuesarereviewedandthedesigndecisionsandcontributionsarejus-
tified. In additionto thecontributionsinvolvedwithin thedesignof themainarchitecture
andcircuit blocks,thereexist somedesigntechniquecontributionswithin the peripheral
circuit blocks.Theseincludeanon-overlaptriple clockgenerator, usingamasterclock for
interleavedS/H andplacingadaptive leadcompensationsin thetransconductors.Theoret-
ical details for the latter one are discussed in Appendix A.
A flasharchitecturewaschosenfor the6-bit 400-MHzADC design.Thespecifications
of theADC werechosenslightly higherthanwhatwasneededfor thetargetapplication.A
brief backgroundfor differentADC architectures,anda comparisonbetweenthem,is dis-
cussedin thebeginningof theADC sectionin Chapter3. Comparatordesign,autozeroing
techniquesandoffsetcancellations,digital back-endandcontrolcircuitsarethemaincir-
cuit issuesdiscussedin the secondhalf of Chapter4. The relevant simulationresultsin
eachpart arepresented.Finally, layout issuesmany of which areparticularlycritical for
the ADC implementation conclude this chapter.
Chapter 1:Introduction 5
Chapter5 presentsthe experimental results for the fabricatedchip. Theseresults
includefunctionaltests,signalto noiseanddistortionratio analysis,integral nonlinearity,
differentialnonlinearitycharacteristicsanda performanceevaluationof PAE/ADC front-
end in an experimental240-mcoaxialcabletestsetup.This communication-systemtest
setupincludedan off-chip adaptive digital equalizer. For othercommunicationchannels
specifications,anotherexperimentwith anarbitraryfunctiongeneratorwasperformed.At
theendof this chapterthecharacteristicsof thechip aresummarizedandthechip is com-
paredto otherstate-of-the-artADCs.Accordingto theexperimentalresults,thecombined
PAE/ADC consumes106 mW of power with 34 dB SNDR at 250 MHz samplingfre-
quency. UsingtheproposedPAE, theADC performancewasshown to beimprovedby 2-
3 bits at a cost of 12% extra area and 17% extra power.
Chapter6 presentsconcludingremarksalongwith suggestionsfor continuationof this
work and future research.
Appendix A presentsthe theoreticalanalysisof the transconductorscircuits in PAE
with regard to its feedback loop, and adaptive compensation.
AppendixB presentstheglobalgradientsearchalgorithmfor PAE coefficient optimi-
zation in detail. This optimizationconsidersboth ADC resolutionrequirements,ISI and
channel noise reduction, simultaneously.
AppendixC presentsthepreliminarysimulationresultsfor oneof thefuturedirections
mentionedin Chapter6. This includesthe ADC resolutionrequirementfor a carrierless
amplitudephasemodulation/quadratureamplitudemodulation(CAP/QAM) communica-
tion system,asopposedto basebandsystems.First, theCAP/QAM systemis briefly intro-
duced.Then a new architecture,using partial analog equalizationand demodulation
techniqueis presented.Accordingto simulationresults,for anapplicationof 1.2Gb/sover
a 200-mcoaxialcable,theproposedtopologywith two 300-MHz6-bit ADCs,alongwith
two 3 to 5-tapanalogFIR partial equalizerfilters, givesthesameerrorperformanceasa
conventionalsystemwith a 900-MHz8-bit front-endADC. The implementationandcir-
cuit design issues of the purposed architecture is a suggested topic for future research.
6
7
CHAPTER
2.1 Introduction
In this chapter, applicationsandtheoreticalbackgroundfor this thesisandfuture dis-
cussions throughout the following chapters are reviewed.
2.2 Wired Data Communication Overview
Wired channelsarea major physical mediumin the telecommunicationsindustry. In
wired communications,thereare trade-offs betweenthe speed,length and price and/or
qualityof thecablesused.Coaxialcablesandtwistedpairs,shown in Fig. 2.1,arethemost
commonlyusedcopperwired channelsfor relatively shortdistances.Optical fiber cables
are used for longer distances, up to tens of kilo metres.
2.2.1 Twisted Pairs
Unshieldedtwistedpair (UTP) cablesarewidely usedin local areanetwork applica-
tions. UTP cablesare categorized basedon their quality: CAT1 to CAT5/5e and the
Figure 2.1: (a) Coaxial cable. (b) Unshielded twisted pair (UTP).
(a) (b)
Background2
8
recently-introducedCAT6. For example,1000Base-T(IEEE802.3)uses4 pairs of UTP
cat5with 256 Mb/s on eachpair. The maximumUTP cablelengthfor Ethernetapplica-
tions is 100 m. [19].
Transmittingdataoverexisting telephonelinesontopof theplainold telephoneservice
(POTS) at frequenciesabove 20 kHz is known asxDSL (digital subscribeloop) [20]. In
xDSL standardsupstreamanddownstreamdataratescanbesymmetricor non-symmetric.
Differentversionsof the xDSL standardexist. Their speedsandmaximumcablelengths
aresummarizedin Table2.1.VDSL is thehighest-rateDSL technologyrunningat speeds
of up to 52 Mbpsover 1 kft (300m) of twistedpair over a frequency bandof 200kHz to
30 MHz.
2.2.2 Coaxial Cables
Coaxialcablesconsistof onesolidwire in thecenterof ameshjacket,asshown in Fig.
2.1.Differenttypesof coaxialcables,known asRGn1, exist andarecategorizedbasedon
their impedanceandquality. For example50-Ω RG8cableis usedin backbonenetworking
ata rateof 10Mb/s for up to 500m. Table2.2showsasummaryof commonlyusedcoax-
ial cable types, with some example applications.
Table 2.1: xDSL Standard types
DSL Type Symmetric /
Asymmetric
Loop
Range (kft)
Downstream
(Mbps)
Upstream
(Mbps)
IDSL symmetric 18 0.128 0.128
SDSL symmetric 10 1.544 1.544
HDSL (2 pairs) symmetric 12 1.544 1.544
ADSL G.lite asymmetric 18 1.5 0.256
ADSL asymmetric 12 6 0.640
VDSL asymmetric 3 / 1 26 / 52 3 / 6
VDSL symmetric 3 / 1 13 / 26 13 / 26
1. RG comes from the word “Radio Group” referring to the traditional usage of coaxial cables in militaryapplications [22].
Chapter 2:Background 9
Serial Digital Video Applications
Oneof themajorapplicationsof coaxialcablesis serialdigital videotransmission.For
example,in studios,videodatafrom videocamerasis transferredto editingequipmentin
serial digital format. Generally, different componentsof video signalsare digitized by
about10 bits resolutionandcombinedandmultiplexed into onestreamof digital serial
data.
Table2.3showsthecommonlyuseddigital videostandardsfor transmissionovercoax-
ial cables,as defined by the Society of Motion Pictures and Television Engineers
(SMPTE).The maximumlengthfor Belden-8281cable,which is a 75-Ω RG-59Utype,
for eachstandardis alsoshown in theTable2.3 [21]. Thesemaximumlengthsarebased
onthemaximumallowedlossat thehalf of theclockfrequency suggestedby thestandard.
2.3 Digital Communication Systems
Fig. 2.2shows a digital communicationsystemblock diagramconsistingof a transmit-
ter anda digital receiver. In this system,bit streamsareencodedto a sequenceof Ak sym-
bols and transmittedto the channelthrough a transmit filter . The modulationof
Table 2.2: Coaxial cable types and example applications
Application / Standard Coaxial Cable Type Impedance
Thicknet Ethernet
(e.g. 500m cable 10Base5)
RG8 or RG11 50 Ohm
Thinnet Ethernet (e.g. 185m 10Base2) RG58 50 Ohm
Digital Video, CATV RG59 75 Ohm
Table 2.3: Different SMOPTE standards
SMPTE
259M
SMPTE
259M
SMPTE
259M
SMPTE
344M
SMPTE
252M
Data rate 143 Mb/s 270 Mb/s 360 Mb/s 540 Mb/s 1.5 Gb/s
Application Composite
NTSC
Component
video
Component
Wide screen
Component
Wide screen
HDTV
Maximum Belden
8281 length (m)
436 305 262 213 79
g t( )
10
symbols by thepulseshapeof is known asa pulseamplitudemodulation(PAM)
scheme.If thepulse is abasebandfunction,themodulationis calledbasebandPAM.
PhaseShift Keying (PSK)andQuadratureAmplitudeModulation(QAM) areotherpopu-
lar modulation schemes [7].
Bandwidthefficiency can be improved by using multi-level techniquesand spectral
shapingof thetransmitfilter [23]. Moreover, multilevel signallingreducestheclockspeed
of the system,which is an importantpracticalpoint in a receiver front-enddesignfor a
specificdatarate.However, this benefitcomesasa costof extra complexity andhigher
signalto noiserequirements.In multilevel signallingevery n-bit bockis mappedontoone
symbolwith a level among2n levels.4-level PAM is a popularchoice,becauseby adding
two extra levels, symbol rate and bandwidth are halved.
Theshapeof thetransmitfilter is alsoknown asa line code.Somebasicline codesare
comparedin Fig. 2.3.Bandwidthefficiency, zerodccomponent,implementationcomplex-
ity andhaving enoughtransitionsfor analogclock recovery areall importantconcernsin
choosingappropriateline codes.Bandwidthefficiency is an interpretationof therequired
bandwidthfor transmittinga certainnumberof symbolsper secondand its theoretical
maximumis 2 (Symbol/sec.)/Hz.For example,in Fig. 2.3., if we considerthe first fre-
quency domainnotchastherequiredbandwidth,it is seenthat theBiphaseline codehas
thelowestbandwidthefficiency, i.e.0.5(Symbol/sec)/Hz.However, its advantageis thatit
guarantiesonetransitionpercycle andhasno dc component.TheNyquistpulsegivesthe
Ak g t( )
g t( )
Receive Filter
ADC Equalizer
Clock
Slicer
+
Transmit Filter
Detected
Symbols-
Channel
Error
+
Noise
recovery
Coderbit stream
Figure 2.2: Block diagram of a digital communications system.
Decoder
bit stream
bnˆ
bn
Chapter 2:Background 11
maximumbandwidthefficiency, but it requiresahighorderpulseshapingfilter or anaccu-
rate D/A in the transmitter, which is costly at high speeds.
NRZ (non-returnto zero)pulseis commonlyusedbecauseof it simplicity andreason-
ablebandwidthefficiency. Practically, in the presenceof an adaptive digital equalizer, a
lowpassfilter aftertheNRZ shapingfilter cancontrolthebandwidthusagein thechannel.
If thebandwidthis notamajorissuein anapplicationthis lowpassfilter or partof it canbe
placedafterthechannelat theinput of thereceiver in orderto limit theout of bandnoise.
Excessive limitation of thebandwidthincreasessensitivity to the front-endsamplerjitter.
Therefore,a reasonablechoicefor lowpassfilter bandwidthcanbe 0.6Fs whereFs is the
symbol rate frequency. A 0.6Fs has20% excessbandwidthcomparedto the minimum
requiredNyquistbandwidth,which is 0.5Fs. In caseof low noisechannels,a largerexcess
bandwidthis preferred.Another issuewith an NRZ line codeis that in ac-coupledsys-
tems,its dc componentvanishes;andthus,a low frequency drift occursin thesignal.This
effect, which is calledbaselinewander, is usuallycorrectedby extra circuitry. Thedigital
baselinewandercorrectionusedin this thesisis discussedin the experimentalresults
chapter.
1/T1/2T
PAM with
2 (Symbol/sec)/Hz f
g(t)G(f)
-T T 2T -1/2T
1/T
1/2T
T/2
g(t)
G(f)g(t)
G(f)
1/2T
T/2
-T/2
-T/2
Figure 2.3: A comparison of basic line codes.
Nyquist Pulse (Ideal case)
Biphase:
0.5 (Symbol/sec)/Hz
No DC
NRZ:
1 (Symbol/sec)/Hz
DC Exists
12
2.4 Equalization
The convolution of the symbols sequenceAk, by the equivalent channel impulse
response,composedof transmit,channelandreceive filters, producesinter-symbolinter-
ference(ISI). Theequivalentdiscretetime channelimpulseresponsefor a 300-mcoaxial
cablesampledat symbolrateis shown in Fig. 2.4.Themorecableattenuation,thelonger
thechannelimpulseandthemoreISI componentsexist. Thepartof thechannelimpulse
that affects the next symbolsis calledpost-cursorISI and the part that affectsprevious
symbolsis calledpre-cursorISI, asshown in Fig. 2.4. In reality, the channelimpulseis
causal.However, by assumingthesymbolsaredelayedby thetime locationof thechannel
impulse maximum location, the above definition is sensible.
Fig. 2.5shows theISI effect on a 4-level PAM signalby theabove channel.Thesignal
samplesat theoutputof thechannelarehighly correlatedandhave a non-uniformampli-
tudedistributionasopposedto thetransmittedsymbols. Fig. 2.5(c, d) shows thesamples
of theinputandoutputof theequivalentchannelatsymbolrate.As seen,thefour levelsof
−5 0 5 10 15 20 250
0.02
0.04
0.06
0.08
0.1
0.12
Post-cursor ISIPre-cursorISI
Ak Ykh(n)
Noise (Zk)
+
Delayed and attenuated symbol
h(n)
Time (Normalized to symbol period)
(a)
(b)
Figure 2.4: (a) Channel impulse response. (b) Discrete time model for a channel.
Chapter 2:Background 13
the transmittedsymbolsaredistortedby ISI error. An equalizercanrecover the original
level of thedatasymbols.A linearzero-forcingequalizeris primarily a filter equalto the
inverseof the channeltransferfunction.Therefore,the attenuationby thechannelwould
causesignalenhancementby theequalizer, particularly, athighfrequencies.Thisenhance-
mentis harmfulin thepresenceof additivenoisesuchaschannelnoiseandADC quantiza-
tion noise.
Sincethechannelcharacteristiccanchangeover thetime, theequalizerfilters areusu-
ally madeadaptive. Practically, equalizersareadaptedsuchthat the residualerrorbefore
theslicer is minimized,ratherthanforcing themto have thechannelinverseresponse.In
this way, the noise enhancement amount can be optimized as well.
Fig. 2.6 shows several equalizationarchitectures.Part (a) and(b) show feedforward
(FFE)anddecisionfeedback(DFE)digital equalizertypes.In DFE,sincethefeedbackfil-
ter utilizesthesliceroutput,it doesnot enhanceadditive noise.However, in caseanerror
0 5 10 15 20 25−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol number0 5 10 15 20 25
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
Time normalized to symbol number
correlation = 0.85
0 500 1000 1500 2000 2500 3000 3500 4000−1.5
−1
−0.5
0
0.5
1
1.5
Time, normalized to symbol period
Am
plitu
de
Figure 2.5: ISI effect on a 4-level PAM signal.
(a) Channel Input NRZ data (b) Channel Output
(d) Channel Output Samples at Fs(c) Channel input samples at Fs
0 500 1000 1500 2000 2500 3000 3500 4000−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
Time, normalized to symbol period
Am
plitu
de
Time, normalized to symbol number Time, normalized to symbol number
Time, normalized to symbol numberTime, normalized to symbol number
Am
plit
ud
e
Am
plit
ud
e
Am
plit
ude
Am
plit
ude
14
occursat thesliceroutput,theerrorpropagatesfor a longtime.Moreover, thefeedbackfil-
ter in DFE can only cancel the post-cursor ISI.
Another categorizationof digital equalizersis basedon their running samplingrate.
Baud-ratedigital equalizersrun at thesymbolrateandfractionally-spaceddigital equaliz-
ers run at higher rates.An importantadvantageof fractionally spacedequalizersis that
they canperformasa combinationof matchedfilter andequalizers,andthis is favorable
over noisy channels.However, at high baudrates,baud-rateequalizersmay be preferred
becauseof difficultiesin building ADCswith largesamplingratesandexcessiveorderand
power consumption by digital equalizers, as is the case in this work.
Part (c) shows anadaptive full-analogequalizer. In this case,aftertheanalogequalizer
thesymboldatalevelsarerecovered.Thus,a sampleranda slicercandetectthetransmit-
SlicerFFEADC
DFE
ChannelOutput
SlicerFFEADCChannelOutput
Analog Equalizer
SlicerFFEADC
DFE
ChannelOutput
PartialAnalogEqualizer
Slicer
Akˆ
Akˆ
Akˆ
Akˆ
(a)
(b)
(c)
(d)
Figure 2.6: Different equalization architectures.
Chapter 2:Background 15
tedsymbols.Building a high speedadaptive analogequalizerwith a largeorderin CMOS
processis notaneasytask.Moreover, it doesnothavetheflexibility androbustnessof dig-
ital equalizersandit cannotbenefitfrom lower noiseenhancementby architecturessuch
asDFE. However, dependingon theapplication,whenit is possible,it offersadvantages
suchaseliminatingthe needfor an ADC andlower power consumption.Several BIPO-
LAR and BICMOS analog equalizers have been reported for video applications [24][25].
Part (d) shows a partial analogequalizeralong with an ADC and digital equalizers.
This is theapproachwhichhasbeenpresentedin this thesisandwhichwill bediscussedin
Chapter3. In summary, this approachsuggestsa simpler analogpre-equalizationthat
would relax the complexity requirement by the ADC and the digital equalizers.
2.5 Adaptive Filtering Overview
An adaptive filter is a self-adjustingtime-varyingfilter wherethetuningis achievedby
minimizing thepower of anerrorsignal,asshown in Fig. 2.7.Theerrorsignalis thedif-
ferencebetweenthe filter output and the desiredoutput. The desiredoutput can be
obtainedinitially from a training sequence.In equalizationapplications,the difference
betweentheinputandoutputof theslicercanbeusedastheerrorsignal.At thebeginning
of adaptationsincethesliceroutputhasanincorrectvalue,it takeslongerfor adaptationto
converge.Theuseof thetrainingsequenceat thebeginningandthenreplacingthedesired
signal with the slicer output is another choice, and is used in this thesis.
Theadaptationof thefilters is performedby adjustmentof their coefficientsor thegain
andthezero-polelocations.Gradientsearchwith themethodof steepestdescentis acom-
Figure 2.7: An adaptive filter block diagram.
Adaptive Filter
Adaptive Algorithm
Desired Outputd(n)
Inputx(n)
Errore(n)
Output
y(n)
16
monly usedmethodin adaptive filtering [26]. In this method,thecoefficientsareadjusted
in thedirectionof thegradientof themeansquareerrorperformancesurfaceat eachstep,
as shown below:
, (2.1)
where is the step size parametercontrolling the rate of convergence, s are the
coefficients of the filter to be adaptedand is the mean-squarederror signal
(MSE). Due to difficulties in obtaining a partial derivative of the MSE signal, the
instantaneoussquarederroris usedto approximateMSE.Therefore,(2.1)canberewritten
as
. (2.2)
In case of finite impulse response (FIR) or transversal filters, we have
, (2.3)
where is the desiredsymbols.Thus,the gradientterm in (2.2) canbe simplified to
. Thus, we can write:
. (2.4)
2.5.1 Adaptation of Cascaded FIR Filters
The above adaptationalgorithm is called the leastmeansquareor LMS algorithm,
which is usedin this thesisto adaptthe FIR equalizerfilters. Note the gradientsignals
arethe delayedversionof the filter input andin an FIR filter structurethey are
inherently available.
In caseof cascadedFIR filters, suchasH(z) andG(z) in Fig. 2.8, theLMS adaptation
of the secondfilter is straightforward.For the first filter, the gradientsignalshave to be
hi n 1+( ) hi n( ) µ ∂E e2
n( )[ ]∂hi
-------------------------
–=
µ hi
E e2
n( )[ ]
hi n 1+( ) hi n( ) 2µe n( ) ∂e n( )∂hi
-------------- –=
e n( ) d n( ) hix n i–( )i
∑–=
d n( )
x– n i–( )
hi n 1+( ) hi n( ) 2µe n( ) x n i–( )( )+=
x n i–( )
Chapter 2:Background 17
obtainedseparately. Theoutputerrorof thetwo cascadedfilters in Fig. 2.8canbewritten
as
. (2.5)
Therefore, the error gradient, with respect to the first filter coefficients, can be written as
, (2.6)
where is the input signalfilteredby . Fig. 2.8 demonstratestheblock diagram
of LMS algorithm implementation for two cascaded filters.
2.6 Coaxial Cable Modeling
An approximatetransferfunctionof thecablecanbederivedfrom thetransmissionline
lumped-parametermodelof thecable,asshown in Fig. 2.9 [5]. In this model,theprimary
constantsR, L, G andC aretheper-unit seriesresistance,seriesinductance,shuntconduc-
tanceandshuntcapacitance,respectively. Theseprimary constantsdependon many fac-
tors suchas geometryand the materialusedin the insulation.In a properly terminated
e n( ) d n( ) gihix n i– j–( )
i∑
i∑–=
∂e n( )∂hi
-------------- gix n i– j–( )i
∑ r n j–( )= =
r n( ) G z( )
H(z)
z-1 z-1 z-1
G(z)
G(z)
LMS Algorithm LMS Algorithm
Desired outputd(n)
Error signale(n)
x(n) y(n) z(n)
Figure 2.8: LMS adaptation for two cascaded filters.
r(n)
18
transmissionline the reversetravelling signalis zeroso that the transferfunctioncharac-
teristic is given by
, (2.7)
where is the cable length and , known as propagation function, is defined as [27]
. (2.8)
Therealpartof determinesthecableattenuationandits imaginarypartdetermines
the phaseof the cable.In (2.7), the resistanceR is a complex valueproportionalto the
squareroot of the frequency. This is dueto theskin effect (the tendency of thecurrentto
flow nearthesurfaceof theconductorwhich increasestheresistance).TheparameterG is
a measureof thedielectriclosseffect, which is negligible in data-gradecables.Via some
rearrangementsandapproximationssuchasneglecting relative to and at
higherfrequencies,andthediscardingof constantdelayterms,(2.7) resultsin thetransfer
function
, (2.9)
where .
By using the Belden 8281 cable data sheet, was curve-fitted to
. The exponentialcableresponsein (2.7) was also modeledby an eight-
ordertransferfunctionusingmatlabinvfreq algorithm[28] in orderto easeits usagein the
simulationsduring the currentstudy. The accuracy betweenthe two transferfunctionsis
lessthan0.5 dB in therangeof 1 MHz - 1 GHz. Fig. 2.10shows themagnituderesponse
C d ω,( ) ed γ ω( )⋅–
=
d γ ω( )
γ ω( ) R jωL+( ) G jωC+( ) α ω( ) jβ ω( )+= =
γ ω( )
G ωC R ωL«
C d s,( ) ed k s⋅–
=
k C L⁄=
Cdx Gdx
RdxLdxI
V
I+dI
V+dV
Figure 2.9: Lumped-parameter model for a short section of cable.
k 393.4 109–×
s
rad---------
1 2⁄m
1–
Chapter 2:Background 19
of a 300-mcoaxial cableaccordingto Belden8281datasheetsand the cablemodel in
(2.9).
2.7 Summary
In this chaptervariouswired communicationchannelsandapplicationswerereviewed.
This includedthecoaxialcablechannelusedthroughoutthis thesisasthe targetapplica-
tion medium.Themodelingandcharacteristicsof this channelwerereviewedaswell. A
generaloverview of digital communicationsystemswaspresented.This includedband-
width requirement, NRZ line codes, equalization and adaptive filtering concepts.
Figure 2.10: The magnitude response of a 300-m coaxial cable.
100
101
102
103
104
105
106
107
108
109
−90
−80
−70
−60
−50
−40
−30
−20
−10
0300 Meter Coaxial Cable Magnitude Response
Freq (Hz)
Gain
(dB)
20
21
CHAPTER
3.1 Introduction
In this chapter, the effect of the numberof ADC bits, or quantizationnoise,in digital
communicationsystemsand their error performanceis discussed.Also, efficient analog
preprocessingapproachesintendedto reducethebit requirementby thefront-endADC in
digital communication receivers are investigated.
Thetargetapplicationusedthroughoutthis chapteris a communicationsystemwith 4-
level PAM datatransmissionat 622Mb/s over 300-mcoaxialcable.This channelhas32-
dB lossat half of thebaud-ratefrequency, i.e. 155.5MHz [18]. This largeamountof loss
produceslarge inter-symbolinterferencecomponents(ISI). It is shown thata partialana-
log equalizer(PAE) cansignificantlyreducetheADC front-endresolutionrequirementby
partially reducingtheISI. Theoptimizationof thepartialequalizationtaskis discussedas
well. Finally, it is shown that for our target application,a systemwith an efficient 2-tap
PAE with a 6-bit ADC, performs as good as an 8-bit ADC system without the PAE.
3.1.1 Analog to Digital Conversion in Digital Communication Receivers
Thequantizerat thefront-endof a digital communicationsystemintroducesinevitable
quantizationnoise.Thisaffectstheperformanceof thereceiver in termsof bit errorrateor
meansquareerror (mse). Oneof themaindifferencesbetweenquantizationnoiseandthe
channelnoiseis that quantizationnoisebandwidthis determinedby the ADC sampling
ratebut thechannelnoisebandwidthis alsolimited by thebandwidthof thefront-endana-
ADC Requirements
and Partial
Equalization
3
22
log filter. Generally, thechannelnoiseis assumedaswhite Gaussianbut thequantization
noiseis assumedas white uniform noise.Sincethe quantizationnoiseis relatedto the
input signal,it is not necessarilyan independentrandomnoise[29]. However, whenthe
signalis not highly oversampled,suchasin baud-ratesamplersin communicationreceiv-
ers, the above assumption is acceptable1.
Fig. 3.1 shows a digital communicationsystemwith a front-endADC followed by a
baud-ratedigital linearequalizer(DLE) anda symboldetectorsliceron thereceiver side.
To demonstratetheeffect of theresolutionof thefront-endADC in our targetapplication,
the signal samplesbeforethe slicer (after the linear equalizer)for different numberof
ADC bits areshown in Fig. 3.2.Theorderof theDLE filter waschosento be largesoas
not to bea limitation in thisexperiment.As indicatedin thefigure,ADCswith resolutions
less than 8 bits are not sufficient for an appropriate eye opening.
To quantify this comparison,Fig. 3.2(d) shows the relative root meansquareerror
(RRMSE)of the recoveredsymbols.The RRMSEis definedas the residualRMS error
beforetheslicer, relative to thedistancebetweenthePAM symbollevels.A symbolerror
rate(SER)of about10 -7 occurswhen andthis is particularlytruebecause
theresidualerrorhasa Gaussiandistribution dueto theDLE. Thesimulationsfor our tar-
get applicationverify this assumption.As seenfrom Fig. 3.2(d),an acceptableRRMSE
valueof about10%(correspondingto ) is attainedby morethan8 bits resolu-
tion for the front-end ADC.
1. Particularlyin communicationsystems,thechannelnoiseactsasditherandmakesthequantizationerrorhave a more random nature and white spectrum.
Figure 3.1: A digital receiver using baud-rate linear feedforward equalizer.
Digital Linear
Equalizer (DLE)Channel + filtering
Error
Detector
Channel
Noise
σa
2 σx2
+a
-3a-a
+3a
H ejω( ) -
C ejω( )
Analog
ADC
fs
a n( )
a n( )
Front-end Filtering
x n( )
RRMSE 0.1≈
SER 107–≈
Chapter 3:ADC Requirements and Partial Equalization 23
3.2 Quantization Noise
In a uniform quantizer, assumingtheadditive quantizationerroris uniform within each
quantization interval , the variance of the quantization error can be written as [3]
, (3.1)
where is theprobabilitydensityfunction(pdf) of thequantizationerror
and is the expectationfunction.Thequantizationstep is a functionof the input-
signal peak value and the number of quantization bits as
. (3.2)
Figure 3.2: (a), (b), (c) Signal samples before symbol detector for different number of ADCbits. (d) Relative mean square error versus number of ADC bits for the system in Fig. 3.1.
0 2000 4000 6000−2
−1
0
1
25 bits ADC
0 2000 4000 6000−2
−1
0
1
26 bits ADC
0 2000 4000 6000−2
−1
0
1
28 bits ADC
3 4 5 6 7 8 9 100
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5Effect of ADC resultion on rmse
Number of bits
Rel
ativ
e m
se
(a)
(d)
(c)(b)R
RM
SE
Number of bits
∆
σqz
2E Q
2[ ] pQ q( )q2
qd∆– 2⁄
∆ 2⁄∫= ∆=
212⁄=
pQ q( ) 1 ∆⁄= q
E .[ ] ∆
x peak R
∆ 2x peak 2R–⋅=
24
In general,the quantizationerror introducedby an R-bit ADC to an input signal with
variance can be defined as [30]
, (3.3)
where is the quantizerperformancefactor. Generally, dependson the quantizer
structuresuchasquantizeruniformity andthedistributionof theinputsignal[30][31]. For
a uniform quantizer with a random input signal, by combining (3.1) & (3.2) and
comparingthat to (3.3), we can see that is proportional to the input crest factor
as
. (3.4)
To estimate for quantizationpurposes,we can define an acceptableclipping
probability such that
. (3.5)
Table 3.1 compares the quantizer error for different distributions and clipping
probabilities.As seen,for a fixedsignalpower , thequantizationerrorcanbe12 times
(10.8dB) better, if thequantizerinput signalamplitudedistribution is uniform ratherthan
Gaussian.
σx
2
σqz
2 εq
22
2R–σx
2=
εq
2 εq
εq
x peak σx⁄
εq
2 1
3--- x peak σx⁄( )2
=
x peak
Pclip
P X x peak>[ ] Pclip=
σx
2
Chapter 3:ADC Requirements and Partial Equalization 25
3.3 ADC Input Characterization
In a basebanddigital communicationsystemin which thefront-endADC samplesand
quantizes the input signal at baud rate, the ADC input signal can be written as
, (3.6)
where are the samplesof the equivalent channelimpulse response(including both
transceiver front-end and back-endanalog filters) and are the transmitteddata
symbolsat thechannelinput. For instance,in a 4-level PAM scheme, cantake four
different values, each with equal probability. By assumingthat the transmitteddata
symbolsatdifferenttime instants,i.e. , areindependentrandomvariables,wecan
characterizethe ADC input from (3.6).For example,basedon (3.6), , the varianceof
, can be written as [32]
. (3.7)
Table 3.1: A comparison of quantization error for different input signal distributions
Input signalDistribution
Gaussian 6 12
Gaussian 5.2 9
Uniform (Continuous) 1.7 1
Uniform a
(Discrete 4-level)1.34 - -
Uniform b
(Discrete N-level)- -
a. For the signal with discrete amplitude distribution, is highly dependent on the quan-
tization decision levels. Ideal placements of those levels can result in a zero quantiza-
tion error or .
b. For an N-level PAM, the levels are of the form:-(N-1)a, -(N-3)a,..., (N-2)a, (N-1)a.
Thus, and . Therefore, .
Pclip
xpeak
σx
⁄ εq
2 σq2 σ
x2⁄ ε
q2
22R–
=
109–
12 2( ) 2R–
107–
9 2( ) 2R–
0 2( ) 2R–
0
0 3N 1–( )
N 1+( ) )---------------------
εq
2
εq
2 0=
σ2x N
21–( )a
23⁄= x
peakN 1–( )a= x
peakσ
x⁄ 3
N 1–( )N 1+( ) )
---------------------=
x n( ) cka n k–( )k∑=
ck
a n( )
a n( )
a n k–( )
σx
2
x n( )
σx
2 σa
2ck
2
k∑
=
26
To obtaintheADC inputpdf from (3.6),werecallthatthepdf of thesummationof
two independentrandomvariablesis equalto theconvolution of thepdf of eachvariable.
Therefore, by defining , the pdf of the ADC input can be estimated as
. (3.8)
where is the convolution operator. Fig. 3.3 shows the channelresponse with
normalizedenergy for our target application. Assuming the transmitteddata has no
redundantinformation, the pdf of the data signal at the input of the transmit filter is
uniform for differentamplitudelevels. For example,for a 4-level PAM scheme,the pdf
value is 1/4 at each PAM level and zero for the rest of the amplitude range.
Eachof thepdf termsin (3.8),hasthepdf of theoriginaldata,which is scaledalongthe
amplitudeaxisby channelimpulsesamples , asshown in Fig. 3.4.Theresultof thesuc-
cessiveconvolutionof thesepdf termsis alsoshown in Fig. 3.4.As indicatedin thefigure,
whenthenumberof nonzerocoefficients becomeslarger in (3.8), thepdf of theADC
input signal will changefrom uniform towardthatof a Gaussianshape.This con-
ceptis compatibleto thegeneralizedform of thecentrallimit theoremin probability the-
ory [32][33].
pX x( )
uk cka n k–( )=
pX x( ) … * pU 1–c 1– a n 1+( )( ) * pU 0
c0a n( )( ) * pU 1c1a n 1–( )( ) * …=
*
−5 0 5 10 15 20 250
0.02
0.04
0.06
0.08
0.1
0.12
Post-cursor ISIPre-CursorISI
Figure 3.3: The impulse response of a 300-m coaxial cable sampled at 311 MHz.
ck
k
ck
ck
ck
pX x( )
Chapter 3:ADC Requirements and Partial Equalization 27
As mentionedpreviously, changingthe uniform distribution to that of a Gaussianone
increasesthecrestfactorby 4.5times(seeTable3.1).Sincethecoefficients , except ,
representtheISI componentsoccurringwithin thechannel,if beforetheADC theequiva-
lentchannelimpulseresponseis changedsuchthatit hasfewernonzero , wecanbenefit
from a lower crestfactor. As a result,a lower additive quantizationerroroccurs.Fig. 3.5
shows thechannelresponseafterbeingpartiallyequalized,andits outputamplitudedistri-
bution from (3.8).Whenthenumberof largeISI componentsis reduced,thedistribution is
−2 −1 0 1 20
0.2
0.4
−2 −1 0 1 20
0.2
0.4
−2 −1 0 1 20
0.2
0.4
−2 −1 0 1 20
0.2
0.4
−2 −1 0 1 20
0.2
0.4
−2 −1 0 1 20
0.05
0.1
−2 −1 0 1 20
0.02
0.04
−2 −1 0 1 20
0.005
0.01
−2 −1 0 1 20
0.005
0.01
−2 −1 0 1 20
5
x 10−3
−2 −1 0 1 20
5
x 10−3−2 −1 0 1 2
0
0.2
0.4
*
*
*
*
Figure 3.4: Amplitude distribution of the received signal after the channel shown in Fig. 3.3for a 4-level PAM NRZ signal at the input of the front-end ADC (see (3.8)); as seen, for alarge number of nonzero ISI components in the channel impulse response ( ), thisdistribution can be estimated by a Gaussian shape.
ck k 0≠,
−2 −1 0 1 20
0.2
0.4
δ≅ n( )
δ≅ n( )
*
After c55
Ideal Gaussianwith variance
σx2
pU 2–c 2– a n 2+( )( )
pU 0c0a n( )( )
pU 1c1a n 1–( )( )
pU 2c2a n 2–( )( )
pU 55c55a n 55–( )( )
of:
pU 1–c 1– a n 1+( )( )
Amplitude
Pro
babili
tyP
robabili
tyP
robabili
tyP
robabili
tyP
robabili
tyP
rob
ab
ility
Amplitude
ck c0
ck
28
moreuniform-like. Here,thechannelresponsehasonemajor ISI componentandthedis-
tribution of the channeloutput hasseveral peaks.The location of thesespeakscan be
obtainedfrom the convolution sequencein (3.8). It is worth noting that this distribution
peaksmay be usedin nonuniformquantizationin order to achieve a lower quantization
average error [31].
Generally, if most of the energy of the channelimpulseresponseis accumulatedin
coefficientssuchthattherestof thecoefficientsarenegligible, basedon(3.8)wecanwrite
, (3.9)
where is the peak amplitude of the ADC input. The above estimation is
considerablyusefulwhenwe needto estimatethe improvementof the channelresponse
through analogpreprocessingaccordingto the crest factor and the quantizationerror
performanceimprovement.To evaluatethechangeof thecrestfactorwithin thechannel,
(3.9) and (3.7) can be combined as
. (3.10)
Generally, while is fixedor simply is normalized to one (see (3.7)), a
betteranalogpreprocessingin termsof crestfactorimprovement,shouldproducea lower
. This can be used as an optimization criterion for better analog preprocessing.
L
x peak a peak ckL∑=
x peak
x peak
σx
-------------a peak
σa
------------- ck∑
ck
2∑---------------------×=
σx
2 σa
2⁄ ck
2∑
ck∑
Chapter 3:ADC Requirements and Partial Equalization 29
3.4 ADC Resolution Requirement
Fig. 3.6 shows a basebanddigital communicationsystemwith a digital receiver. To
maintainanacceptablesystembit errorrate,thefront-endADC hasto meetacertainreso-
lution requirement.To determinethis requirement,we considerthe varianceof the total
remaining error before the slicer in Fig. 3.6 as
, (3.11)
−2 −1.5 −1 −0.5 0 0.5 1 1.5 20
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5x 10
−3
−2 −1.5 −1 −0.5 0 0.5 1 1.5 20
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
−2 −1.5 −1 −0.5 0 0.5 1 1.5 20
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.1
−2 −1.5 −1 −0.5 0 0.5 1 1.5 20
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0 5 10 15 20 25 30 35 40
0
0.2
0.4
0.6
0.8
1
1.2
Figure 3.5: Estimation of the signal peak when the signal is output from a combinedchannel/partial equalization filter with less ISI components.
pU 4c4a n 4–( )( )
pU 5c5a n 5–( )( )
x peak a peak ck∑⋅=
U 4 5, peak u4 u5+=
ck
k
*
Channel impulseAfter partialequalization
*
σerr
2 σqz
2 σn
2+( )K DLE
2[ ] σISI
2+=
30
where is thequantizationnoisevarianceintroducedby theADC, is thevarianceof
the channeladditive noise, is the error enhancementfactorcausedby the digital
linear equalizer (DLE), and is the remaining ISI error variance.
The total noiseerror aroundeachsymbol level hasapproximatelya Gaussianshape
becauseof thesummationsof independentnoisecomponentsoccurringin theexpression
(3.11)andalsowithin thedigital equalizerfiltering operation.Therefore,thesymbolerror
rate (SER) can be estimated as
(3.12)
where is half of the distancebetweenthe PAM levels andQ(.) is the tail areaof the
Gaussiandensity. Expression(3.12)providesaconstraintfor thevarianceof thetotalerror
(noise)beforethe slicer in (3.11).By recalling the expression(3.3) for the quantization
error introducedby an R-bit ADC, i.e. , combiningit with (3.11), and
rearranging, we can write
, (3.13)
Here is related to the desired SER and the participation ratio of the enhanced
quantization noise to the total error , or specifically
. (3.14)
σqz
2 σn
2
K DLE
2
σISI
2
LinearEqualizer
GChannel + Filtering
Symbol Detector
ADC
ChannelNoise
QuantizerNoise
σx
2 σx
2
σqz2
σn
2
+a
-3a-a
+3a
_
Figure 3.6: Block diagram of a digital communication system receiver with 4-level PAM symbols at the input.
( Slicer )
Delayσerr2
X K
XK
Digital
SER p error a>( ) 2Q a σerr⁄( )= =
a
σq
2 εq
22
2R–σx
2=
22R– L
2
K DLE
2 εq
2⋅-----------------------<
L
σ'qz
2 σqz
2K DLE
2= σerr
2
La
σxQ1–
SER 2⁄( )--------------------------------------
σ'qz σerr⁄⋅=
Chapter 3:ADC Requirements and Partial Equalization 31
The inequality (3.13) can be written in dB scale as
. (3.15)
Either(3.13)or (3.15)canbeusedto determinetheminimumeffective numberof bits
requiredfor the front-end ADC. is a system-designparameterthat dependson the
desiredSERandtheorderof thedigital equalizer. Thus,themainapproachto reducingthe
bit requirement is to reducethefactors (thecrestfactorof theADC inputsignal)and
(the amount of the noise enhancement by the digital equalizer).
To reducethe ADC resolutionrequirement,an optimumanalogpreprocessingcircuit
mustminimizeboth and simultaneously. This canbeachievedby reshapingthe
equivalentchannelimpulseresponseand its components beforethe ADC. Recalling
from (3.4), is 1/3 of thecrestfactorof theADC input signalandthis canbeobtained
from (3.10).Accordingto (3.10),if thechannelimpulseenergy is normalizedto
one, is minimized by minimizing .
The quantization(white) noiseenhancementby a feedforward equalizer(FFE) with
coefficients is given by
. (3.16)
The above expressionis a valid criterion when the channelimpulseenergy is
normalizedto one.If theDLE is a linearzeroforcing equalizerin the frequency domain,
is ideally the inverseof thechannelfrequency response . Thus,we can
write:
. (3.17)
Thediscretefourier formatof (3.17)is ( is theDFT of )
which can also be used to evaluate .
R L– dB( )2
K DLE dB( )2 εq dB( )
2+ +( ) 6.02⁄>
R
L
R εq
2
K DLE
2
εq
2K DLE
2
ck
εq
2
ck
2
k∑
εq
2ck
k∑
hi
K DLE
2hi
2
i∑=
ck
2
k∑
H ejω( ) C e
jω( )
hi
2
i∑ 1
2π------ H e
jω( )2
ωd
π–
π
∫ 1
2π------
1
C ejω( )
2----------------------- ωd
π–
π
∫= =
1 N⁄( ) 1 C k( )( ) 2⁄∑ C k( ) ck
K DLE
2
32
3.4.1 Example and Comparison to Simulation Results
As anexample,expression(3.13)canbeutilized to calculatetherequiredADC resolu-
tion for the systemin Fig. 3.6 whenappliedto our target application(622-Mb/s4-level
PAM over 300-mcoaxial cable).First, note that for the 4-level NRZ PAM with a level
spacing of we can write
. (3.18)
Thus, in (3.14) will be . The assumption of and
,as design specifications,results in or . The
channelresponsedefinesanequalizerboostof or . A clippingerror
of givesthe quantizationfactoras or . Exploiting theseparameter
values in (3.15), results in a minimum bit resolution of bits.
Fig. 3.7depictsacomparisonof errorperformanceversusADC resolutionaccordingto
both analyticalexpression(3.13)1 andsystem-level simulationresults.The minor devia-
tion at lower resolutionsis dueto the fact that the crestfactor in the analyticalonewas
1. Notethatin (3.13)for achosen , weobtaintheparameter which is relatedto theSER.Also, SERis
related to according to (3.12).
2a
σx
2E X k
2[ ] 1
4--- 3a–( )2
a–( )2a( )2
3a( )2+ + +[ ] 5a
2= = =
a σx⁄ 1 5( )⁄ SER 109–
=
σ'qz
2 σ2err⁄ 1 3⁄= L
21 560⁄= 27.5dB–
K DLE
217.5= 12.4dB
107– εq
29.4= 9.7dB
R 8.3=
5 6 7 8 9 10 110
0.05
0.1
0.15
0.2
0.25
Number of ADC bits
Rel
ativ
e R
MS
E
10-22
10-6.2
10-3
10-12
10-7.6
10-9.4
10-16
Equ
ival
ent s
ymbo
l err
or r
ate
Figure 3.7: A comparison of error performance according to the analyticalexpression in (3.13) and system-level simulation.
Simulation
Analytical
R L
σ2err
Chapter 3:ADC Requirements and Partial Equalization 33
basedontheassumptionof anADC inputwith aGaussianamplitudedistribution,whereas
the simulations was based on the actual channel output.
3.5 ADC Bit Requirement Reduction Techniques and PartialAnalog Equalization
From expression(3.13),we seethat and arethe only factorswhich canbe
reducedin orderto lower theresolutionrequirementfor thefront-endADC. Usinga deci-
siona feedbackequalizer(DFE) reducesthe , but sincetheprecursorISI cannotbe
cancelledby feedbackequalizeraswell asdue to error propagation andclock recovery
difficulties,theorderof thefeedbackfilter is limited. Therefore,theneedfor anFFEstill
exists and a considerable amount of quantization noise enhancement will remain.
Oneapproachto reducingthequantizerfactor is to usea nonuniformquantization
suchthatthequantizererroris decreased[30] [31]. However, thisapproachis notefficient
sinceit doesnotaffect andfurthermore,resultsin anon-standardADC architecture.
Ideally, a full analogequalizercanreducethe ADC bit requirementto as low as the
slicerorder;for example,two bits for a4-level PAM scheme.Nevertheless,therearemany
practicaldifficultiesin thedesignof adaptiveanalogfilterswith largeorders,suchasaccu-
rate calibrationand adaptationof filter parameters,distortion accumulation,DC offset,
mismatchand compatibility with complicatedpulse shapingor modulation schemes.
Moreover, thereis alwaysa preferenceto have somedigital receiver capabilitiessuchas
adaptive digital filtering, decision feedback equalization and digital clock recovery.
Partial analogequalization(PAE) canbe definedassplitting the equalizationamong
digital andanalogsides[17]. An exampleof splitting the10-tapFIR into two 4-tapanalog
and7-tapdigital, with the sametotal numberof zeros,is shown in Fig. 3.8. Simulation
resultsshow thatpartialequalizationreducesboth and simultaneously. Therea-
sonbehindthe reduction,asmentionedpreviously, is thattheamplitudedistribution of
thesignalat theoutputof thechannel,greatlydependson theamountof the ISI compo-
nents.After partialequalization,theamplitudedistributionof thesignalat theADC input,
becomesmoreuniform ratherthanGaussian,due to a considerablereductionin the ISI
components.
εq
2K DLE
2
K DLE
2
εq
2
K DLE
2
K DLE
2 εq
2
εq
2
34
For example, Fig. 3.9 shows the effect of a 4-tap analog FIR partial equalizer on the
channel impulse response and the channel output, for our target application. Note that can-
celling the ISI components by the PAE greatly changes the shape of the signal amplitude
distribution, thereby reducing by a factor of about 4.5 and according to (3.13), reducing
the ADC resolution requirement by more than one bit.
Further bit requirement reduction is due to the reduction of noise enhancement by the
DLE. Table 3.2 summarizes the improvement in parameters and for this exam-
ple. According to (3.13), those parameters result in a bit reduction of 2.8 bits. To verify
this result, the above PAE has been placed in the system of Fig. 3.8 and the recovered sym-
bols before the slicer are compared to a similar system without PAE. Two different 5-bit
and 8-bit ADCs have been used in this simulation. As seen in Fig. 3.10(a) and Fig.
3.10(b), there is a considerable performance degradation when the number of bits is
Figure 3.8: (a) The receiver architecture for a 622-Mb/s, 300-m coaxial cable with a 4-tap partial analog and a 7-tap digital linear equalizer. (b) Zero locations of the partialanalog and digital equalizers, obtained from a 10-tap original digital equalizer.
Channel
7-tap FFE
LinearEqualizer
Error
Detector
-
LP ADC
fs
OutputPartial Analog
Equalizer
4-tap PAE
−2.5 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5−2.5
−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
2.5
Zeros movedfrom 10-tap DLEto a 4-tap PAE
(a)
(c) Zero locations of equalizers in architecture (a) and (b)
Splitting a 10-tap equalizer between the analog and digital sides
εq
2
εq
2K DLE
2
Chapter 3:ADC Requirements and Partial Equalization 35
reducedfrom 8 to 5 for thecaseof a full-digital equalizationwith no PAE. In contrary, by
using the analog pre-equalization the performance degradation is fairly tolerable.
ComparingFig. 3.10(b, c) shows that theADC resolutionrequirementis reducedby
about3 bits.Fig. 3.10alsoshows thebenefitof usinga partialequalizerwhenthenumber
of ADC bitsarelow, i.e.5 bitshere.Otherwise,thequantizationparticipationin contribut-
ing to the total error is negligible and the existence of the PAE is not of much benefit.
Figure 3.9: The effect of a 4-tap PAE on the ADC input amplitude distribution and 300-m coaxial channel impulse response (with normalized energy). (a) Before PAE. (b)After PAE. (a, b) (i) ADC input samples. (a, b) (ii) The corresponding equivalentchannel impulse responses.
0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500
−3
−2
−1
0
1
2
3
Receiver input samples before analog partial equalizer
Am
plitu
de
Time, normalized to symbol period
0 5 10 15 20 25 30 35 40 45 50−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
Am
plitu
de
Time, normalized to symbol period0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500
−3
−2
−1
0
1
2
3
Receiver input samples After analog partial equalizer
Time, normalized to symbol period
Am
plitu
de
0 5 10 15 20 25 30 35 40 45 50−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
Time, normalized to symbol period
Am
plitu
de
Channel
Channel +PAE
(a) (ii) Channel Impulse response(a) (i) ADC input (when PAE is off)
(b) (i) ADC input (when PAE is on) (d) (ii) Channel + PAE Impulse response
36
3.6 Partial Equalizer Design
The optimum partial equalizerprimarily dependson the structurechosenfor the
receiver. The variety of the structurescomefrom different topologies,filter types, the
Table 3.2: comparison of architectures with and without PAE
RMSE with8-bit ADC
RMSE with5-bit ADC
Minimum “R”for SER=10-9
Architecture without PAE, 17.5 9.4 0.09 0.52 8.3 bits
Architecture with PAE, 1.65 2.1 0.08 0.09 5.5 bits
Comparison 1 / 10.9 1 / 4.5 1 / 1.13 1 / 5.78 -2.8 bits
K2
DLE εq
2
0 1000 2000 3000 4000 5000 6000−1.5
−1
−0.5
0
0.5
1
1.5
Time, normalized to symbol period
Am
plitu
de
0 1000 2000 3000 4000 5000 6000−1.5
−1
−0.5
0
0.5
1
1.5
Time, normalized to symbol period
Am
plitu
de
0 1000 2000 3000 4000 5000 6000−2
−1.5
−1
−0.5
0
0.5
1
1.5
2
Time, normalized to symbol period
Am
plitu
de
0 1000 2000 3000 4000 5000 6000−1.5
−1
−0.5
0
0.5
1
1.5
Time, normalized to symbol period
Am
plitu
de
(a, b) Without partial equalizer
8-bit ADC5-bit ADC
(c, d) Using partial equalizer
8-bit ADC5-bit ADC
Figure 3.10: Performance comparison of the architectures with and without PAE fordifferent numbers of ADC bits. (a, b) 10-tap DLE, without partial equalizer. (c, d)Using partial equalizer (4-tap PAE, 7-tap DLE).
(a) (b)
(c) (d)
RMSE=0.52 RMSE=0.09
RMSE=0.09 RMSE=0.08
Chapter 3:ADC Requirements and Partial Equalization 37
ordersof thedigital andpartialanalogequalizersandalsonumberof bits availablefor the
ADC. For example,if a largenumberof bits is available,thereis no needto have analog
preprocessingfor the quantizationnoisereduction.However, in this casethe analogpre-
equalizationcanbeconsideredto reducethecomplexity of digital equalizerandtherefore,
possibly, saving power andarea.In this part,we limit thereceiver structureto a FIR DLE
and an analog FIR for the partial equalizer.
In PAE design,the ultimategoal is to minimize the total remainingerror beforethe
slicer. Generally, thedesignof thepartialanalogequalizerandthedigital equalizerarenot
independent.PAE determinesthe distribution of the quantizerinput signal, and thus,
affectsthe amountof the quantizationerror for a certainbit resolution.The PAE is also
relatedto theshapeof DLE regardingtheequalizationtaskcompletionandtheamountof
channeland quantizationnoise enhancement.Therefore,the optimization of PAE and
DLE with a giventotal orderandADC bit resolutioncanbea complex task.Assumingan
analogFIR filter for PAE anda digital FIR filter for DLE, severalapproachesto finding a
close to optimum PAE/DLE design solution are proposed and investigated.
3.6.1 Optimizing the PAE Independently for Maximal Equalization
In thisapproach,asshown in Fig. 3.11,thepartialanalogequalizeris adaptedfor max-
imum possibleequalization,independentfrom its digital counterpart.This methodcanbe
performedby removing thedigital equalizeror settingits coefficientsto zeroat thebegin-
ning,runninganLMS algorithmfor PAE, makingits coefficientfixedandthenperforming
theadaptationalgorithmfor thedigital equalizer. SincetheISI beforeADC will bemini-
mized,the crestfactorof ADC input andthe noiseenhancementfactorby DLE will be
reduced.Thus, accordingto the expression(3.13), a lower ADC bit resolutionwill be
Figure 3.11: Optimizing a partial equalizer independently for maximum equalization.
KChannel
+a
-3a-a
+3a
C ejω( )
PAE
Delay
Errora n( )
G(z)
a n( )a n( )
38
required.Although this approachis practically simple and straight-forward, it exhibits
someimperfections.Oneconcernis thatfor agivenorderfor PAE andDLE, afteroptimiz-
ing PAE wemaynothave thebesttotal ISI reductionby adaptingDLE with limited order.
Generally, adaptationof two cascadedfilters independentlydoesnotgive theoptimalsolu-
tion, unlesswe adaptthemsimultaneously(seeChapter2) [34]. Othermethodsdiscussed
later in this sectionwill resolve this concernat a costof increasedcomplexity. Another
problemwith this methodis theproperdelayvalue.If thedelayvaluein Fig. 3.11is not
appropriatelyset,thesolutioncanberelatively far from optimum.In providing asolution,
if thetotalorderof filters is low, theoptimizationtaskduringinitializationcanberepeated
for differentdelaysandthebestdelaychosen.On thedigital side,if initially we canapply
a larger order digital filter, then the location of the nonzerocoefficients determinesthe
appropriate delay.
3.6.2 Splitting an Optimum Equalizer into Analog and Digital Filters
In this method,a largerorderequalizerwith anappropriatetotal numberof zeroswill
bedesignedusingadaptingtechniquessuchasanLMS algorithm.It will thenbesplit into
two differentfilters by groupingits zerossuchthat they conformto the desiredorderof
PAE andDLE. In this way, we ensurethat thefinal remainingISI error is minimizedfor
the desiredtotal filters orders.A criterion to group the zerosamongPAE and DLE is
required.Sincethis criterionis just basedon bit-requirementreduction,theresultsin part
3.4 canbe utilized. Anotherway to split the zerosis to choosethe PAE zerossuchthat
they arecloseto the zerosof a suboptimalPAE found independentlyusingthe previous
method.
The zero splitting approachis more reliable since it follows a regular equalization
schemewith an optimum lowest channelnoiseenhancement.However, still it doesnot
necessarilygive the best optimum solution regarding the ADC resolutionrequirement
reduction,or in otherwords,minimizing thefactors and . It shouldbenotedthat,
for somegiven ordersof PAE andDLE the zerosplitting methodmight be not feasible,
due to conjugate zeros which cannot be split into separate real filters.
εq
2K DLE
2
Chapter 3:ADC Requirements and Partial Equalization 39
3.6.3 Global Optimization Using Genetic and/or Gradient Search
A generalglobaloptimizationtechniquesuchasGeneticAlgorithm [35][36] or Global
GradientSearch [26] canbeusedto find thezerolocationsof thePAE andDLE filters.As
demonstratedin Fig. 3.12,usingtheresultsin part3.4a closedformulafor thetotal error
canbecreated.It will includetheremainingISI, theenhancedquantizationerrorandthe
channelnoiseversusthedesignparameters.This formula is usedasa criterionto find the
optimumfilters coefficientsandthe delay in the equivalent total channelresponse.Note
thattheamountof theenhancedquantizationnoisedependsonnotonly thenumberof bits
(R), but alsotheshapeof PAE andDLE dueto their effect on and , respectively.
Accordingto thesimulationresults,GeneticSearch algorithmis usefulto obtainanover-
all estimationof the optimum delay and filters zero locationsquickly. However, after
coarseadjustmentof zeroslocationsof PAE andDLE we caneitherusethis resultasa
guidein thepreviousmethodto split thezerosproperlyor usethemasa startingpoint for
ckChannelCharacteristic
σ2nch
NumberR of bits
ChannelNoise power
Minimizing error througha global optimization
PAE Coefficients: gi
Impulse response
DLE Coefficients: hi
Delay: d
σ2total error–
σ2isi σ2
qz σ2n+ +
c*g*h( )d
2-------------------------------------------=
σ2isi c*g*h( )i
2
i d≠∑=
σ'2
qz σqz
2K DLE
2⋅=1
3---x
2peak 2
2R–hi
i∑⋅
2=
σ'2
n σ2nch
g*h( )i
2
i∑⋅=
Figure 3.12: Global optimization of PAE/DLE coefficients.
x peak a peak c*g( )ii
∑⋅=
σ2total error–
algorithm
Order of PAE/DLE
εq
2K DLE
2
40
anothergeneraloptimizationalgorithm.This could includea Gradient Search algorithm
who maysuffer from local minimaexistences.Fig. 3.13depictstheblock diagramof the
Genetic Search algorithm used in this investigation.
As mentioned,theGlobal Gradient Search algorithmcanbeconsideredanalternative
or continuingmethodfor the Genetic Search of the optimumfilters. This methodin the
priceof addedcomplexity helpsin findingacloserto optimumsolutionfor apartialequal-
izationdesign,comparedto thepreviousmethods.Dueto thenon-linearityandcomplex-
ity of the error function, the algorithmmight get stuck in somelocal minimum. In this
case,obtainingtheinitial startingpointsfrom eitherof thepreviousmethodscanbehelp-
ful. The sametotal error criteria shown in Fig. 3.12canbe usedto generatethe gradient
componentshere.Note that as opposedto the caseof the Genetic algorithm, the delay
termhasto bedefinedbeforerunningthis algorithm.Sincethetotal errordependson the
cascadedPAE/DLE coefficientsboth directly (by their effectson the filters output)and
indirectly (throughtheir effect on and ), thegradienttermdefinitionis relatively
complex. The details of this algorithm are described in Appendix B.
Essentially, theaboveglobaloptimizationmethodsareusefulif weareconcernedabout
imperfectionsin thepreviousmethods.They canalsobeusedasa verificationtool in the
design stage or as an aid tool for splitting the zeros in zero splitting method.
Create initial Population
Evaluation:
each member setcalculate total error for
Create offspring:more number for member
with lower error
Create Next GenerationRandom selection/mixing/mutation
Figure 3.13: Genetic search algorithm block diagram used for PAE/ DLE architectureoptimization.
K DLE
2 εq
2
Chapter 3:ADC Requirements and Partial Equalization 41
3.6.4 Simulation Results and Comparisons
Table3.3comparestheperformanceof thesystemthatwasshown in Fig. 3.8with a 5-
bit ADC, whenPAE andDLE areadaptedwith previously discussedmethods.Also, the
componentswhich contribute to the total remainingerror accordingto (3.11)and(3.13)
arequantifiedin eachrow. In the first row, the systemconsistsof a 10-tapDLE with no
analogpreprocessing.In thiscase,theamountof thetotalerroris enormousbecauseof the
sizeof the crestfactorandthe quantizationnoiseenhancement.The restof the rows are
relatedto thearchitecturesin which a 4-tapPAE anda 7-tapDLE areutilized. Note that
thetotal numberof zerosof bothDLE andPAE is thesamefor all of therows. In thesec-
ondrow, PAE is optimizedindependentlyfrom DLE for thehighestattainableequalization
andthenthesamefor DLE (Method3.6.1). Comparedto thefirst row, it showsaconsider-
able reductionof the enhancedquantizationerror . Nevertheless,the remainingISI
error varianceis increasedby about1.5 dB becauseof less-optimumequalizationwhile
the total order of equalization (the number of zeros of PAE+DLE) is the same.
.
The third row utilizes the methodof splitting the zerosof a singleequalizer(method
3.6.2). The ISI cancellationis asgoodasthe first row at the costof greaterquantization
noise,comparedto thesecondrow. Thelastrow showstheresultsof thedesignusingGlo-
bal Gradient Search algorithmcombinedwith Genetic Search algorithm(method3.6.3).
Theresultsarenow moreoptimizedaccordingto boththeremainingISI andthequantiza-
tion noise.Thedifferencebetweenthefinal resultsof differentmethodscomparedto the
Table 3.3: Comparison of PAE optimization method for a 5-bit ADC system
Architecture andDesign Method
R (bits) KDLE CrestFactor (dB) (dB) (dB)
Without PAE, single 10-tap DLE 5 17.5 6 12 -6.9 -24.6 -6.8
Method 3.6.1:4-tap PAE, 7-tap DLE, independentlyadapted for maximum equalization
5 1.40 1.41 0.66 -29.37 -23.2 -22.2
Method.3.6.2:4-tap PAE, 7-tap DLE, PAE obtainedfrom splitting method
5 1.75 1.52 0.77 -26.9 -24.6 -22.5
Method.3.6.3:4-tap PAE, 7-tap DLE, adapted by bothGlobal Genetic andGradient Search
5 1.67 1.46 0.71 -27.5 -24.6 -22.9
σ'qz
2
εq
2 σ2qz σ2
ISI σ2err
42
overall improvement,versusthe casewithout PAE (first row), is not considerable.How-
ever, for otherarchitectureswith differentADC resolutionsandfilter orders,the results
canbemorevariable.In conclusion,thefirst suboptimalmethod,i.e. optimizingPAE for
maximumindependentequalization,couldbeused.However, in thesystemlevel design,
wemustassuretheresultsarenot far from apossibleoptimumresult,andthiscanbeveri-
fied through method3.6.3.
Fig. 3.14shows thelocationof thezerosof the4-tapPAE and7-tapDLE for theabove
examples.If we considerthe resultsof the last row designasthe optimal locationof the
zeros, this figure shows how close to optimum the other methods are.
3.7 Two-tap PAE: An Efficient Choice
Fig. 3.15shows a comparisonof errorperformanceimprovementby PAE versustheir
ordersanddifferentADC resolutionsfor our targetapplication,i.e.622Mb/s4-level PAM
datatransmissionover 300-mcoaxialcablewith -27dBadditive channelnoise.Thecrite-
rion usedhere,is therelative root meansquareerror(RRMSE). As previously mentioned,
RRMSEis the residualRMS error beforethe slicer, relative to the distancebetweenthe
PAM modulationlevels. resultsin abit errorrateof about10-7 for aGaus-
−3 −2 −1 0 1 2 3−3
−2
−1
0
1
2
3
Figure 3.14: Zero locations of examples discussed in Table 3.3.
Zero location of
obtained by different
PAE/DLE
PAE zeros
approaches
PAE zeros
PAE zeros
Unit circle
10-tap DLE with
Method 3.6.3 (Global LMS)
Method 3.6.1
Method 3.6.2
The sign used for
no PAE
PAE DLE
PAE zeros
Method 3.6.3(Genetic)
RRMSE 0.1≈
Chapter 3:ADC Requirements and Partial Equalization 43
sianresidualerror. TheDLE usedin this simulationwas11 tapswith 7-bit coefficients.It
wasobservedthat further increasingof theDLE orderandits coefficientsresolutionhave
negligible effect on the error performance in the current system.
In Fig. 3.15(a)it is notablethat,for a 5-bit ADC, a major improvementis achievedby
thelowestorderof apartialanalogequalizercomparedto theslightextra improvementby
an additionalPAE order. Fig. 3.15(b)demonstratesthe samefor different ADC resolu-
tions. As we can see,using PAE is advantageouswhen a low resolutionADC is used,
becausefor a largenumberof bits, the total error is dominatedby the remainingISI and
channel-noiseerrors,ratherthanby quantizationerror. An importantobservation in Fig.
3.15(b)is that, for , a 2-tapPAE / 6-bit ADC performsaswell asa 9-bit
ADC withoutPAE. This is equivalentto 3 bits improvementonADC performanceby add-
ing a low-cost low-order analog pre-processor.
The reasonfor attaininga major improvementusinga low orderPAE is that the PAE
doesnot have to do fine equalizationandto resemblethechannelinverseprecisely. Based
on (3.13),PAE is mainly responsiblefor reducingthecrestfactorandtheamountof noise
boostby DLE. Thus,a roughanalogpre-processorsuchasa 2-tapanalogFIR cando this
to a greatextent.Fig. 3.16(a,b) comparesthechannelcharacteristicsof a 300-mcoaxial
0 2 4 60
0.1
0.2
0.3
0.4
0.5
Number of PAE taps
Rel
ativ
e R
MS
E
2 4 6 8 100.05
0.1
0.15
0.2
0.25
0.3
Number of ADC bits
Rel
ativ
e R
MS
E
No PAE 2 TAP PAE3 TAP PAE4 TAP PAE
Figure 3.15: (a) RRMSE improvement for Fig. 3.8 architecture with 5-bit ADC fordifferent PAE orders. (b) A comparison of RRMSE improvement for different PAEorders and different ADC resolutions.
(a) (b)
No PAE
2-tap PAE
3-tap PAE
4-tap PAE
RRMSE 0.1≈
44
cableandits first orderdiscretetimeapproximation.Theinverseof thisfirst-orderapprox-
imation results in an efficient partial equalizer in the form of
. (3.19)
The impulseresponseafter the channeland partial equalizeris shown in Fig. 3.16(c).
Although someISI componentsstill exist, a major portion of themarecancelled.Thus,
regardingthediscussionmadein part3.4,aconsiderablylower resolutionADC fulfills the
quantization requirement for the system.
Regarding the resolutionof the PAE coefficients, it shouldbe mentionedthat their
requirementsare fairly relaxed due to post-adaptationof the DLE filter. Moreover, the
importanceof PAE is moreevident in worstcaseISI which happensfor thelongestchan-
nel. For shorterchannelsa rough settingof PAE coefficients is sufficient becauseof a
lower ADC resolutionrequirement.Fig. 3.17shows theeffect of thecoefficient variation
on theerrorperformancefor a 2-tapPAE whenchannelis setto its maximum,i.e. 300m.
As we cansee,up to 10% changeof the PAE coefficient (dueto quantizationor circuit
implementationerror)doesnot affect theadvantageof having PAE considerably. Regard-
G z( ) K 1 a– z1–( )=
Figure 3.16: The channel characteristics of a 300-m coaxial cable and its first orderdiscrete time approximation. (a) Frequency Responses. (b) Impulse responses. (c)Equalized impulse response after a 2-tap PAE.
0 10 20 30 40 50 600
0.2
0.4
0.6
Time, normalized to symbol period
Am
plitu
de
0 10 20 30 40 50 60−0.5
0
0.5
1
Time, normalized to symbol period
Am
plitu
de
102
103
104
105
106
107
108
−30
−20
−10
0
10Cable Magnitude Response
Freq (Hz)
Gai
n (d
B)
300m coaxial cable Frequency response One pole discrete time approximation
Channel Impulse ResponseFirst order App. Impulse Response
Chapter 3:ADC Requirements and Partial Equalization 45
ing the fact that ADC resolutionrequirementsaremorecrucial for longerchannels,the
PAE coefficient setting(or quantization)can be performednon-uniformly by assigning
morePAE coefficient settingswhenchannelis longer. As it will bementionedin Chapter
4, having useda2-tapPAE for our targetapplication,4 differentsettingsfor thecoefficient
arechosensuchthatwhenchannellengthis closeto it longestvaluethePAE coefficient
settings are not more than 10% apart.
3.7.1 Using Decorrelation Concept for a 2-tap PAE Design
Becauseof the simplicity of the mentionedfirst orderapproximation,we may recon-
sidertheapproachesof designingPAE for this simplercase.Onenew approachis consid-
ering the 2-tap PAE as a first order decorrelator [16]. In essence,the independent
uniformly distributedsymbolsat the input of thechannelbecomehighly correlatedat the
outputof thechannelbecauseof ISI. Removing thecorrelationof thesymbolsat theout-
put of the channelis the sameasflatteningthe power spectrumof the incomingsignal
[30][33]. A baud-rateequalizerdoesthe sameaspart of the Nyquist condition [7], and
essentially, theoutputsymbolsof anidealequalizerareindependent.However, a decorre-
lator is not necessarilyanoptimumequalizersincedecorrelationis only aboutthemagni-
tude of the signal spectrum,whereasNyquist condition relatesto the both phaseand
magnitudeof thesignal.Nevertheless,by assumingthat theoutputof thechannelis a fil-
a
2 4 6 8 100.05
0.1
0.15
0.2
0.25
0.3
Number of ADC bits
RR
MS
E
Optimum PAE10% coff. variation30% coff. variationNo PAE
Figure 3.17: The effect of coefficient variation of a 2-tap PAE on RRMSE.
46
teredrandomprocess,a 2-tapdecorrelatoris sufficiently closeto a partial coarse equal-
izer, playingtheroleof awhiteningfilter. Having anFIR baud-rateequalizeris equivalent
to assumingthat the channelis estimatedby an all pole discretefilter andconsequently,
theoutputof thechannelis anauto-regressive random(AR) signalasshown in Fig. 3.18.
Notethat,if necessary, by cascadingsomeextradelaycellswecanincludeaprecursorISI
into themodeltoo.However, in thecaseof the2-tapequalization,themajority of thecan-
celledISI componentsarepost-cursor. This is particularlytrue,in abaudratesystemwith-
out ananalogmatchfilter. In this case,theapproximatemodelof thechannelis asshown
in Fig. 3.18(a) and we can write its output as
. (3.20)
Thusa2-tappartialequalizer(or decorrelatorhere)wouldbetheinverseof thechannelas
. (3.21)
By assumingthe simple model in (3.20) the correlationbetweenneighbouringoutput
samples can be calculated as
(3.22)
Figure 3.18: The channel modeled by an: (a) AR(1) process and (b) AR(N) process.
Z-1 Z-1 Z-1
1aN 1–aN
+
az1–
(a) (b)
C z( ) 1
1 a– z1–
-------------------= C z( ) 1
1 ak zk–
k∑–
-----------------------------=
x n( ) y n( ) x n( ) y n( )
y n( ) x n( ) ay n 1–( )+=
1
C z( )----------- 1 a– z
1–=
Ryy 1( ) E y n( ) y n 1–( )[ ] aσ2y= =
Chapter 3:ADC Requirements and Partial Equalization 47
and a recursive calculation gives:
. (3.23)
Therefore,thecoefficient in thedecorrelator(3.21)canbewell estimatedfrom (3.22)as
an autocorrelation factor1:
(3.24)
The above is anotherapproachto finding the zeroor the singlecoefficient of a 2-tap
PAE andit doesnot needany trainingsequenceandcanbeestimateddirectly by channel
outputsamples.Thesimulationresultsfor ourexampleapplication(622Mb/s over 300-m
coaxialcable)show that the resultof theabove approachis sufficiently closeto theopti-
mum solution.
3.7.2 Using the PAE Inverse in the Digital Domain
Whenthe analogpreprocessoror PAE is designedwith the goal of ADC bit require-
mentreduction,althougha low orderroughpre-equalizerprovidesa major improvement,
theISI errorandchannelnoiseenhancementmayexceedfrom theiroptimumperformance
dueto limited orderof digital equalizers.To preventthis,we canaddanextra postdigital
filter equalto the inverseof thePAE beforeDLE. For the2-tapcase,basically, theADC
block is replacedby thesubsystemshown in Fig. 3.19.In thisway, thedigital communica-
tion systemfunction is the sameasthe casewithout an analogpreprocessorandthe ISI
error and channelnoiseenhancementsremainrelatively unchanged.With regard to the
1. An ideal estimation must satisfy both (3.22) and(3.23) and this depends on how realistic the AR(1)model in (3.20) is.
Ryy k( ) E y n( ) y n k–( )[ ] ak σ2
y= =
a
a ρ E yi
∑ i( ) y i 1–( ) y i( ) 2
i∑
⁄ = =
48
ADC andquantizationnoiseperformance,the systemis quite different.In Fig. 3.19 the
ADC input hasa lower crestfactor; thus, lessadditive quantizationnoisewill be intro-
ducedby theADC. Also, thequantizationnoiseis highly degradedby thepostdigital fil-
ter, particularly at high frequencies.It shouldbe mentionedthat this architecture(Fig.
3.19) is mainly applicablewhenPAE is a 2-tapanalogdecorrelator. This is becauseits
zero’s magnitudeis equalto thecorrelationfactorin (3.24)which is lessthanone.There-
fore, the PAE zero is insidethe unit circle andthe PAE inverseis stableandfeasibleto
implement.
Themismatchbetweenthevaluesof in theanaloganddigital sidein Fig. 3.19can
bea concern.Table3.4shows a comparisonof thereceiver RRMSEfor 0 to 10 percentof
mismatch.For low mismatch(up to 2%), RRMSEremainslow. For a largermismatch
betweenthevaluesof , theRRMSEcanbeconsiderable.However, thepromisingpoint
is thattheadaptationof thedigital equalizercancompensateto agreatextentfor this mis-
matcheffect (last columnof the table).It shouldbe notedthat in the currentdesign,the
Table 3.4: The effect of mismatch of values before and after ADC on the relative RRMSE
Fixed equalizer
Equalizer is adaptedafter addingmismatch
Mismatch 0% 1% 2% 5% 10% 10%
RelativeRRMSE
0.085 0.085 0.091 0.120 0.210 0.087
ADC
αz-1 αz-1
1 αz 1––
_
Decorrelator
Figure 3.19: ADC quantization performance improvement using an analog decorrelator
2-tap analog
ρyy
1( )FIR pre-processor
Digital post-filter
1 1 αz 1––( )⁄
x(n) y(n)
α
α
α
α
Chapter 3:ADC Requirements and Partial Equalization 49
valueof in theanalogsideis theratioof two transconductanceamplifiers’gainandit is
mainly determinedby their degenerationresistorsratio. Theseresistorsarecarefully laid
out besideeachother in an inter-segmentedform. Therefore,regarding the mismatch
propertiesin CMOStechnology[37], thevariationof theanalog is not expectedto be
more than 10%.
3.7.3 Comparison with predictive coding systems (ADPCM)
A 2-tapPAE/decorrelatoris similar to thepredictivedifferentialcodingsystems[33] in
which theinput samplesarepredictedby theprevioussampleswith theaid of correlation
informationamongthem.Generally, in predictive codingsystems,the predictionis done
in a feedbackloop (Fig. 3.20(b))ratherthanin a feedforward loop (Fig. 3.20(a)).In this
case,thequantizercanalsobemovedinto thefeedbackloop(Fig. 3.20(c)).As aresult,the
quantization noise will be divided by the loop gain as well.
α
α
αz-1
_
x(n)_
x(n)
αz1–
1 αz1–
–----------------------
ADC
_
x(n)
αz1–
1 αz1–
–----------------------
ADC
Figure 3.20: Comparison of (a) feedforward and (b) feedback predictive systems. (c)The Quantizer (ADC) is placed inside the feedback loop (ADPCM). (d) Post digitalfilter (reconstructing the original signal).
αz-1
Digital post-filter
1 1 αz 1––( )⁄
y(n)
x n( )
xd n( )
x n( )
x n( )D/A
1 αz 1––1 αz 1––
1 αz 1––
xd n( )
xd n( )
ADC
(a) (b)
(c) (d)
xdˆ n( ) xd
ˆ n( )
xdˆ n( ) xd
ˆ n( )
50
If the quantizeris placedinsidethe predictionfeedbackloop, after signalreconstruc-
tion by the post digital filter (Fig. 3.20(d)), the quantizationnoiseremainsunchanged.
However, it shouldbe notedthat for highly correlatedsignalsthe quantizationnoiseis
much smallerbecausejust the signal with variance is
beingquantizedby theADC. As a result,thequantizationnoiseis reducedby a factorof
,known as the prediction gain.
The analogimplementationof the feedbackpredictive coding (Fig. 3.20(d)) is not
alwaysfeasibleathighspeeds,dueto thelargeloopdelaycausedby ADC andtheloopfil-
ter. This delayshouldbe smallerthanthe symbolperiod.However, the possiblewaysof
combatingthe loop delayproblem,suchasusingparallelfastcircuits,canbeconsidered
as an open research topic [38][39].
In feedbackpredictive systems,thepredictionfilter usesthequantizedsamplesto pre-
dict the next sample.In the feedforward method,the non-quantizedsamplesare used
instead.Therefore,in theprocessof postdigital filtering, thevarianceof thequantization
noisewill beincreasedagain,but with adifferent shape in thefrequency domain.Sincethe
post digital filter is lowpass,the quantizationnoisewill be coloredand will be highly
reducedathigh frequencies.Thiscausesthedigital equalizer, whichbooststhehigherfre-
quency components,to have a reducedenhancementeffect on the coloredquantization
noise.Interestingly, theconceptof quantizationnoiseshapingis alsousedin delta-sigma
modulator ADCs, but in a different way [2][3][29].
Although in feedforwarddecorrelation(Fig. 3.20(a))the reductionof thequantization
erroreffect is dueto thereductionof thecrestfactorandDLE noiseenhancementfactor,
the power of the coloredquantizationnoisemay also be reduced.To evaluatethis, we
comparethe varianceof the final quantizationnoiseafter the postdigital filter with
original quantizationnoise from thesystemwith no analogpredictionor preprocess-
ing. By remembering
, (3.25)
xd n( ) x n( ) x n( )–= σ2xd
σ2x«
σ2xd
σ2x⁄
σqd
2 ′
σq
2
σq
2 εq
22
2R–σx
2=
Chapter 3:ADC Requirements and Partial Equalization 51
and similarly
(3.26)
and ignoring the change of quantizer factor , then we will have
. (3.27)
The quantization noise after the digital post filter is as
. (3.28)
Thus, the change in the quantization noise will be as
. (3.29)
The above value when is equal to one. For some other
, aswasfoundin oursimulationresults,theabovefactorcanbelessthan1. This
implies that, in such cases the quantization is more reduced.
σqd
2 εqd
22
2R–σxd
2=
εq
2
σqd
2
σq
2-------
σxd
2
σx
2--------=
1 G ejω( )( )⁄
σqd
2 ′ 1
2π------
σqd
2
G ejω( )
2----------------------- ωd
2π∫=
σqd
2 ′
σq
2---------
σxd
2
σx
2--------
1
2π------
ωd
G ejω( )
2-----------------------
2π∫⋅
1
2π------
ωd
G ejω( )
2-----------------------
2π∫ S xx e
jω( ) G ejω( )
2ωd
2π∫⋅
S xx ejω( ) ωd
2π∫
--------------------------------------------------------------------------------------------------= =
G ejω( )
2S xx e
jω( )1–
=
G ejω( )
2
52
3.7.4 PAE Usage in FFE and FFE/DFE Architectures and Comparisons
Decision feedbackequalizers(DFE) also reduce channel and quantizationnoise
enhancements.However, while they canonly eliminatethepost-cursorISI, their practical
use is limited due to propagation error, initialization and clock recovery difficulties.
Although the advantageof using PAE is superior in an FFE system,in a FFE/DFE
receiver, theusageof PAE canbeconsiderablybeneficialaswell. To investigatethis fact,
two FFE andFFE/DFEreceiversusedin our target applicationareshown in Fig. 3.21.
Using the inverseof PAE, simplifiesthe equalizationperformanceanalysisasthe signal
remainsunchangedwithin theprocessof quantizationwith pre/postfiltering. In this case,
the equalizationtaskcanbe freely divided amongFFE andDFE filters, independentof
pre/postfilters, for thebestISI andchannelnoisereductionperformance.By PAE pre-fil-
tering,someequalizationis partially, but temporarily, donebeforeADC andwill beneu-
tralizedafterwardsby the PAE inverse.The pre-filteringreducesthe crestfactorandthe
post-filteringcolors the quantizationnoiseto a lowpassshapesuchthat it is not signifi-
cantly enhanced by the FFE.
Figure 3.21: Receiver architectures including ADC with pre-filter (analog)and post-filter (digital). (a) FFE. (b) FFE/DFE.
Slicer
H2(z)
H1(z)1/G(z)ADCG(z)
Analog pre-filter(decorrelator)
Inputfr omChannel
SlicerH(z)1/G(z)ADCG(z)
DigitalAnalog pre-filter(decorrelator)
Inputfr omChannel
Post-filter
Digital Post-filter
FFE
DFE
FFE
(a) FFE
(b) FFE/DFE
DetectedSymbols
DetectedSymbols
Chapter 3:ADC Requirements and Partial Equalization 53
Fig. 3.22shows thefrequency responseof thepostdigital filter, thefeedforwardequal-
izersandtheir combinationsfor bothFFE/DFEandDFE architecturesin our targetappli-
cation.The numberson the curvesshow the amountof their relevant white quantization
noisepower changeafter eachfilter while the signalpower at the ADC input andslicer
outputarenormalizedto one.It canbeseenthat thefeedforwardfilter in FFE/DFEarchi-
tecture has 3.6 dB less noise enhancement compared to the FFE-only system.
Thepostdigital filter ( ) hasa sharplowpassshapeandhasa 2 dB quantiza-
tion noisereduction,dueto thepredictiongain from equation(3.29).Thecombinationof
postdigital filter andfeedforwardequalizerin eitherof theFFE/DFEor DFEarchitectures
canceleachother’sboostingpart.As aresult,thereis aquantizationnoisepowerreduction
of 10.6dBand7.5dB for FFE andFFE/DFEarchitectures,respectively. As we cansee,
temporarypost cursorequalizationof the input signal makes a significantreductionin
quantizationnoiseafter FFE,while the advantageof DFE in the overall system,i.e. less
channel noise enhancement, is not affected.
Fig. 3.23showstheabovefactin termsof thepowerspectrumof thetravelingquantiza-
tion noisein DFE andFFE/DFEarchitecturesin Fig. 3.21with or without pre/postfilter-
Figure 3.22: Frequency response of the post digital filter and the feedforwardequalizers and their combinations for both (a) FFE/DFE and (b) FFE architectures inFig. 3.21.
0 50 100 150−20
−15
−10
−5
0
5
10
Frequency MHz
Ma
gn
itud
e(d
B)
0 50 100 150−20
−15
−10
−5
0
5
10
15
Frequency MHz
Ma
gn
itud
e(d
B)
σq2∆ 5.1dB–=
σq2∆ 2dB–=
σq2∆ 2.4dB=
σq
2∆ 2dB–=
σq
2∆ 5.9dB=
σq
2∆ 4.7dB–=
(a) FFE/DFE (b) FFE
Combination of FFE and post digital filter
FFE filterPAE inverse or post digital filter
1 G z( )⁄
54
ing at different points: after ADC, after digital post filter, after feedforward equalizer filter
or beforeslicer. Thetotal quantizationnoisevariance,i.e. theintegral of eachPSDcurve,
is given in the figure. PSD curves are obtainedthroughWelch’s averagedperiodogram
method and Gaussian windowing [28][40].
As seenin Fig. 3.23(a1,a2),having theanalogpre-filter initially reducesthequantiza-
tion noiseby 7.8dB dueto crestfactorreduction.Moreover, thequantizationnoisepower
is reducedin Fig. 3.23(a3,b3)becauseof theshapingof thenoiseby thepostdigital filter
beforeits enhancementby FFEin both theFFE/DFEandFFEschemes.It is evident that
we achieve moreperformanceimprovementin FFE-onlysystemscomparedto FFE/DFE
systems.Nevertheless,the improvement in the DFE system is still remarkableand
depends on the amount of non-flatness of the FFE spectrum.
0 50 100 150−50
−40
−30
−20
−10
psd
(dB
)
0 50 100 150−50
−40
−30
−20
−10
psd
(d
B)
0 50 100 150
−60
−40
−20
Frequency MHz
psd
(d
B)
0 50 100 150−50
−40
−30
−20
−10
psd
(dB
)
0 50 100 150−50
−40
−30
−20
−10
psd
(d
B)
0 50 100 150−60
−40
−20
0
Frequency MHz
psd
(d
B)
Figure 3.23: Power spectral density of the quantization noise in: (a) FFE/DFE (b) FFEarchitectures (shown in Fig. 3.21) at different points: (1) After ADC, (2) After post digitalfilter (3) After feedforward equalizer (before slicer), with the variety shown below.
ADC with pr e/post filtering:ADC without pr e/post filtering:QZ noise after FFE if no post filter
σ220 dB–=
σ227.8dB–=
σ225.5dB–=
σ217.6dB–=
σ232.9dB–=
σ229.8dB–=
σ232.5dB–=
σ222dB–=
σ214.1dB–=
σ229.8dB–=
σ220 dB–=
σ227.8dB–=
(a)(1)
(a)(3)
(b)(2)(a)(2)
(b)(1)
(b)(3)
Chapter 3:ADC Requirements and Partial Equalization 55
3.8 Simulation Results
3.8.1 Quantization Noise Reduction Demonstration
Fig. 3.24 demonstratesthe quantizationnoisepower reductionby employing a low
order2-tappre/postfiltering. A stronglow frequency tonecombinedwith a weaker high
frequency tonerepresentsa signalwith a lowpassshapeat the receiver input. The PAE/
decorrelatorpre-filter(with no gain) reducestheamplitudeof thesignalat lower frequen-
cies.After a gain amplifier, thesignalis amplifiedbackto theoriginal amplitudebut with
astrongerhigh frequency tone.Thesignalis thenfed into a5-bit ADC andthepostdigital
filter consecutively. The result is shown in Fig. 3.24(f). It shows the reconstructedand
0 0.5 1 1.5 2 2.5
x 10−6
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
0 0.5 1 1.5 2 2.5
x 10−6
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
0 0.5 1 1.5 2 2.5
x 10−6
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
0 0.5 1 1.5 2 2.5
x 10−6
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
0 0.5 1 1.5 2 2.5
x 10−6
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
0 0.5 1 1.5 2 2.5
x 10−6
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
0 0.5 1 1.5 2 2.5
x 10−6
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
Decorrelator1 - a.z-1
Digital post-filter(1/1 - a.z-1)
VGA
ADCQuantizer
5 bits
ADCQuantizer
5 bits
Equalizer Equalizer
Figure 3.24: Demonstration of quantization noise power reduction when a low order pre/post filtering processor is employed.
(a)
(b)
(c)
(d)
(e)
(f)
(g)
56
quantizedform of the original input andcanbe comparedwith a regular 5 bit quantized
form of input (Fig. 3.24(b)).The former result elaboratesbetterhigh frequency details
becauseof the quantizingerror degradationat high frequenciesby the post filter. Fig.
3.24(c)and(g) shows thefinal resultsafterFFEfilter (from theFFE/DFEsystem).Aswe
cansee,thereis significantlylessnoisepower in pre/postfiltering architecturecompared
to direct quantization.
3.8.2 Using 2-tap PAE in Coaxial Channel Application
Fig. 3.25showstheamountof therelativeRMSEfor differentnumbersof ADC bits for
two receivers with and without PAE filters in a 4-PAM 300-m coaxial applicationwith
symbolratesof 300 MS/s and150 MS/s.For ( ) the receiver
with PAE needs2.5bits lessresolutionthanthecasewithoutPAE in the300-MS/scase.A
similar comparisonfor a lower speedof 150MS/sshows a resolutionrequirementreduc-
tion of 1.5 bits. The useof the PAE is lessadvantageousin the 150 MS/s casedueto a
lower ISI asthis resultsin thecorrelationfactorbetweentheinput samplesdroppingfrom
0.85to 0.7.It canalsobeobservedthat,ata largenumberof bits,sincetheRRMSEis sat-
urated by the residual ISI and additive noise, the error reduction is not evident.
RRMSE 0.10≅ SER 107–≅
2 4 6 8 100
0.05
0.1
0.15
0.2
0.25
(a)
# of ADC bits
Re
lative
err
or
(rm
se
)
2 4 6 8 100
0.1
0.2
0.3
0.4(b)
# of ADC bits
Re
lative
err
or
(rm
se
)
Figure 3.25: Comparison of relative RRMSE versus number of ADC bits with andwithout decorrelator for 4-level PAM transmission over 300-m coaxial cable atdifferent speeds. (a) 300 MS/s. (b) 150 MS/s.
(a) (b)
Without decorrelatorWith decorrelator
150 MS/s300 MS/s
Chapter 3:ADC Requirements and Partial Equalization 57
3.9 Summary
In thischapterwereviewedtheimportanceandtheeffectof a front-endanalog-to-digi-
tal converter resolutionin a basebanddigital communicationsystemreceiver and dis-
cussedapproachesto reducethis resolutionrequirementthroughanalogpreprocessing.
Thequantizationnoiseandits effect on thesymbolerror ratewerediscussed.Estimation
of thesignalcrestfactorbeforetheADC with or without analogpreprocessingweredis-
cussed.A formula to estimatethe numberof bits requirementfor the ADC for a certain
symbolerror rateandreceiver architecturewasproposed.Basedon this, the advantages
anddisadvantagesof full analogequalizationandpartialanalogequalizationwereinvesti-
gated.Partial equalizationwasshown to bea betterpracticalsolutionfor ADC resolution
requirementreduction.Differentapproachesfor optimizationof thesplitting theequaliza-
tion job betweenthepartialanalogequalizer(PAE) andthedigital linearequalizer(DLE)
were proposed and compared.
It was shown that a low order analogfiltering block is enoughto createsignificant
improvementin theADC resolutionperformance.Specifically, a two-tappartialequalizer
wasdemonstrated,anddiscussedin detail,asa very efficient analogpreprocessingchoice
to reducethe ADC requirements.Two-tapanalogpre-filteringenablesus to performthe
inverseof the pre-filteringin the digital side.Thus,otherefficient equalizationarchitec-
tures such as DFE with low order filters and less channelnoise enhancementcan be
employed as well.
For thecaseof a2-tapPAE thesinglezeroof thefilter canbeestimatedthroughadeco-
rrelationfactoraswell. The2-tapanalogPAE/decorrelatorreducesthebit requirementof
the analogto digital converterup to 2.5-3bits for 622Mb/sdatarateover 300-mcoaxial
cablewith 4-level PAM schemeapplication.This improvementis dueto reducingthecrest
factorof thesignalbeforeADC andtheamountof quantizationnoiseenhancementin the
digital equalizerafterADC. Theimplementationandverificationof PAE andADC will be
reviewed in the next chapters.
58
59
CHAPTER
4.1 Introduction
Accordingto the resultsin thepreviouschapter, a 2-tapPAE or decorrelatorfollowed
by a 6-bit ADC, asshown in Fig. 4.1, is anefficient front-endchoicefor our targetcable
application.This front-endperformsbetterthanan8-bit-ADC-only one.Here,the imple-
mentationissuesfor thisanalogfront-enddesigndiscussed.In thenext chaptertheexperi-
mentalresultsof the fabricatedprototypechip in a 0.18-µm CMOS technologywill be
presented.
4.2 Partial Analog Equalizer Design
A two-tap PAE is essentially an analog FIR filter of the form
, (4.1)
Figure 4.1: Analog front-end top-level block diagram.
ADC
αz-1
1 αz 1––
_
PAE/decorrelator
x(n)G To digital
signalprocessing
DigitallyControlled
x1
Voltage buffer
H z( ) G 1 αz1–
–( )=
Circuit
Implementation4
60
whereG is thegain adjustmentfactorto compensatefor thesignalamplitudeattenuation
within decorrelation.This makesthesignalamplitudeconformwith theADC
input dynamicrange.Several analogFIR filters with differentnumberof tapshave been
reported[8][6][9][41].However, in thecaseof a 2-tapPAE, becauseof adjustmentof only
a singlecoefficient, we canconsidera morespecificarchitectureandthusachieve higher
speed and performance.
As seenin Fig. 4.1, the building blocks for the 2-tapPAE consistsof a delay line, a
coefficient multiplier, a subtractor, and finally, an -dependent gain adjuster.
4.2.1 Delay Line Generation Techniques
Fig. 4.2depictshow interleavedsample-and-holdblockscanbeusedfor thedelayline
generation.In Fig. 4.2(a)eachS/Houtputis usedmorethanonce;andtherefore,theexist-
enceof a buffer to preserve the held signal is mandatory. In addition,a switch matrix
selectstheproperS/H for eachoutput.Thisarchitecturesavessiliconareaby reducingthe
1 αz1–
–( )
α α
Vin
CH
Figure 4.2: Delay line generation by interleaved sample and hold blocks.
CH
Vin(n)
Vin(n-1)
Vin
CH
Vin(n)
Vin(n-1)CH
CH
x1
x1
φ1
φ2o
φ2e
φ3o
φ3eφ1
φ2o
φ3o
φ3e
φ2e
φ1e
φ1o
φ2e
φ2e
φ2o
φ2o
CLK
φ1o
φ2e
φ2o
φ1e
(a)
(b)
Chapter 4:Circuit Implementation 61
numberof S/H blocks.However, the necessityof the buffer causesa signaldrop during
buffering andthusrequirestheS/H to operatefor a largersignalswing.This is morediffi-
cult in a low voltage technology. Furthermore,the clock feedthroughof the switching
matrix throughthe parasiticsof the buffer canchangethe held signalbeforeits second
usage,andtherefore,introducingextra distortionby changingthe held sample.It should
be notedthat advancedopampclosedloop buffers canreducesignal lossanddistortion,
but they limit the maximum speed compared to their open-loop counterparts.
Fig. 4.2(b)shows anotherdelayline generationin which eachsampledsignalis utilized
only onceat the costof addingmoreinterleaved S/H blocks.In this case,sincethe held
samplesarenot neededfor a secondusage,by directly connectingtheS/H outputswe can
do the addition or subtraction via charge sharing techniques.
4.2.2 PAE Topology Choices
PAE/Decorrelator Architecture Using Charge Distribution
Thedesignin Fig. 4.3is basedonthechargedistributionof sample-and-holdcapacitors
[16]. Theminimumnumberof S/Hblocksin thisarchitectureis three.Thefirst S/H is run-
t1 t2 t3
v(t1)-αv(t0)v(t2)-αv(t1)
track holdφ1
φ2
φ3φ4
S/H
C VDD
α1C
αiC
φ4.ci
Vin+ − Vcm
Vcm
Ci: Selectingαi
φ1
φ2,3
φ4
φ4.c1
φ4.c1
Subtracting
φ4
φ4S/H
C
φ2
S/H
φ3
node
S/H
DigitallyControlled
Gain
v(t0)
v(t1)
v(t2)
Cp
Figure 4.3: PAE block diagram using a charge sharing technique.
V/IConverter ADC
62
ning with themainsamplingrateandtwo otherswith half of thesamplingrate.Theratio
of thecapacitorsvaluein thesecondaryS/H pairsto thecapacitorsvaluein thefirst S/H
determinesthevalueof thecoefficient in (4.1).Therefore,thesecondaryS/H pairsare
selectedamongdifferentchoicesdependingon thevalueof . Thecontrolsignalsfor this
selectioncomefrom the digital domain.After the trackingtime, enablesthe relevant
hold switches,suchthat the properS/H block sharesits capacitorcharge with the main
S/H capacitor. After a settlingtime, thevoltageat thesubtractingnodein Fig. 4.5 is a lin-
earcombinationof eachof thesampledvoltages.Thenegative signof thecoefficient is
obtainedthroughanoppositeconnectionof differentialoutputsof S/Hblocks.Thevoltage
at the subtracting node is given by
, (4.2)
where is theparasiticcapacitanceat thesubtractingnodeand is its voltagebefore
charge sharing. Although the value is much smaller than sample-and-hold
capacitances,extra switchesareusedto force the subtractingnodesto a fixed common
modevoltageduring the tracking time. This is doneto remove any memory from the
previouscycleandpreventthebuffer transistorsfrom beingturnedoff. Thus, in (3)
causesa dc shift at the summingnode,which is cancelledin at the differentialmode.A
differentialcommondrain buffer reducesthe anddrivesthe following variablegain
amplifier (VGA). This VGA compensatesfor the signal loss during the subtractionin
order to cover the ADC input full range.
Theabove architectureis power efficient andgoodfor mediumspeedandresolution,but
at thecostof a largesilicon area,dueto theneedfor extra capacitors.Furthermore,asthe
technologyshifts to lower voltagesand shorterchannellengthsseveral other concerns
exist aswell. As seenfrom (4.2),becauseof chargesharingwehaveextrasignallosswith
a factor of
. (4.3)
This is in additionto the lossby thedecorrelation,i.e. . Therefore,theneed
for extra gain in theVGA imposesspeedandresolutionlimitations,particularlyat lower
α
α
φ4
α
V out
CV t iαC– V t i 1–
C pV p+
C αC C p+ +--------------------------------------------------------=
C p V p
C p
C pV p
C p
C
C αC C p+ +-------------------------------- 0.5≅
V in 1 az1–
–( )
Chapter 4:Circuit Implementation 63
voltages.In addition,sincethechargesin thecapacitorsaredestroyedby chargesharing,
the requiredtime of S/H settlingwill increase.This canbe crucial for the speedof low
voltageswitchesin the sample-and-holdblocks if they do not benefitfrom a bootstrap
technique[42]. It shouldbe notedthat generally, bootstrappingis often avoided due to
reliability andextensivecomplexity issues.Theextra time for chargesharingandtheneed
for an S/H buffer to reducethe effect are other concerns.The above concernsare
relatively commonin otherformsof switchcapacitorFIR implementationasa candidate
for PAE architecture [43][41].
PAE Architecture Using Current Subtraction and Switch Matrix
Fig. 4.4shows the2-tapPAE/decorrelatorarchitecturebasedon current-modesubtrac-
tion. The minimum numberof sample-and-holdblocks is two, and their outputsare
switchedevery othercycle by theswitchmatrix.Theinput samplesandtheir delayedver-
sionsareconvertedto currentby two transconductorsandthensubtractedfrom eachother.
The gain ratio of the two transconductors is equal to the PAE factor .
C p
α
S/H
Digitally
Vin+ −
t1t2
v(t1)-αv(t0) v(t2)-αv(t1)
φ1
φ1φ2
φ3
φ2
φ3
G
αG
& buffer
S/H& buffer
t0
SwitchControlled
GainMatrix
G.[v(ti)-αv(ti-1)]
Sample and hold Subtracting stage Variable Gain Amp.
Oddsamples
Evensamples
Figure 4.4: Current-mode implementation of the 2-tap PAE/decorrelator.
I / VConverter ADC
64
Thisarchitectureis moreareaefficientdueto thelow numberof S/Hblocks.Moreover,
S/H capacitorschargesarenot destroyedat theendof eachclock cycle.Thefirst stageof
the transconductorsneeda better linearity performance(about 1-2 bits more than the
ADC), becausethey convert the input samplesto currentbeforesubtraction.Thesecond-
stageGm-Cell is a variablegain amplifier (VGA) andthusrelaxesthe gain requirement
for thefirst stageGm-Cellswhich have to toleratea larger input swing. In this topology,
eachS/Houtputis utilizedmorethanonce,thus,theneedfor thebuffer andotherconcerns
mentioned for the switch matrix delay line exist here as well (see 4.2.1).
Chosen Topology for the 2-tap PAE/Decorrelator
Fig. 4.5depictsthetop-level circuit architecturechosenfor the2-tapPAE followedby
a6-bit flashADC. Two setsof triple interleavedsample-and-holdblocksprovidethebaud-
ratesamplesof the input signalat the time instants and . In this way, eachS/H
capacitoris usedonceandits chargeis not destroyedbeforethenext samplingtime. Fur-
thermore,interleaving relaxes the S/H designat low voltage operation.Two separate
transconductorswith anadaptive gain ratio equalto theequalizationfactor(or decorrela-
Digitally
Vin+ −
G
αG
ControlledGain
G(v(ti)-αv(ti-1))
Sample and hold Subtracting stage/VGA
S/H
S/H
S/H t3n
t3n-2
t3n-1
Single CLK
CLK pass control
I /V Converter Buffer
v(ti)
v(ti-1) 6 bit
t1t2
φ3nt0
φ3n-1
φ3n-2
t3
x1ADC
Figure 4.5: The top-level circuit architecture for the 2-tap partial analog equalizer.
V/IConverter
Main CLK
v(t1)-αv(t0)
v(t2)-αv(t1)
S/H
S/H
S/H
t3n
t3n-1
t3n-2
ti ti 1–
Chapter 4:Circuit Implementation 65
tion factor) convert the consecutive samplesto current.In this topology, the VGA is
combinedwith thesubtractorstage.Thus,thecurrentsignalsarefirst amplifiedandthen
subtractedfrom each other. This improves noise toleration at the current subtracting
nodes.Direct connectionof the S/H to Gm-Cellsreducessignal lossanddistortionand
allows the useof Nch track-and-holdswitches.To reducethe distortiondueto the mis-
matcheffect in interleavedsample-and-holds,a singlemasterclock techniqueis used,as
will be described later.
4.2.3 Sample-and-Hold design
Sample-and-hold(S/H) circuits play a crucial role in the designof dataacquisition
interfaces.Front-endsample-and-holdsarefundamentallydifficult to designbecausethey
mustoperateat theextremeedgeof theperformanceenvelope.They mustsimultaneously
achieve goodlinearity, high speed,largevoltageswings,high drive capabilities,andhave
low power dissipation.In low-voltageandhigh speedsystems,analogsamplingbecomes
morechallengingbecauselimited headroomfurthertightensthetrade-offs amongtheper-
formanceparameters.MOS S/H circuits mainly suffer from channelcharge injection of
samplingswitchesand clock feedthroughdue to gate-overlap capacitances.Moreover,
therearetwo additionalsourcesof dynamicerror:thevariationof theswitch-on-resistance
with theinput level andinput-dependentsamplinginstantdueto thefinite transitionof the
samplingclock. In addition,whentheseerrorsareinput-dependent,they createnon-linear
distortion, which can be more damaging than a fixed offset error.
Althoughclosedloop S/H circuits [3][44] usingopampsalleviatetheseerrorsandpar-
ticularly their signaldependency, their operatingspeedsareseriouslydegradeddueto the
necessityof guaranteeingthat the loop is stablefor the desiredloop gain. Therefore,for
our targetapplication,which requiresmediumprecisionbut high-speedsamplingrate,an
open-loopdesignis preferred.Amongopen-loopS/H circuits therearetwo conventional
parallelandserialarchitectures,asdepictedin Fig. 4.6(a,b) [44]. Seriessamplinghasthe
advantageof isolatedinput andoutputcommon-modevoltagesandlessnonlinearcharge
injection whenS2 turnsoff earlier thanS1. However, it hasthe disadvantageof charge
sharingwith thenonlinearcapacitanceCP, andlongerholdsettlingtimedueto thesettling
of the voltageat the outputnodeto a new common-modevalue.The S/H in Fig. 4.6(c)
shows anotherarchitecture,in which S2 turns off a little earlier than S1, suchthat the
α
66
chargeinjectionfrom S1into CH is prevented[16]. Notethatsincethechargeinjectionby
S2is signalindependent,it is not crucialandcanbecancelledthroughdifferentialsignal-
ing. Despitetheabove mentionedadvantagesfor Fig. 4.6 (b, c), theconventionalparallel
S/H in Fig. 4.6 (a) is favorablebecauseof its speedand simplicity. Particularly, if the
capacitorcharge is not destroyed during the hold time, the trackingsettlingtime will be
considerably reduced.
In this design,to meetthespeedrequirement,a parallelfully-dif ferentialS/H with tri-
ple-channelinterleaving is utilized.Thus,aswasseenin thePAE architecturein Fig. 4.5,
six S/Hblocksexist in thetotaldesign,just two of whichoperatein samplingmodesimul-
taniously. The circuit diagram of a single S/H block is shown in Fig. 4.7.
A low common-modevoltageof 450mV enablestheuseof NMOSswitcheswith rea-
sonablesizes.TheinterleavedS/H architectureprovidesextendedhold time with a length
of two full clock cycles,onefor the delay in PAE andthe otherclock cycle for the
analogprocessingby thefollowing subtractorandamplifierstages.In addition,aboutone
clock cycle is assignedfor the tracking time, thereby, permitting the useof a holding
capacitor(CH) aslargeas1 pF. A largeCH reducesthenon-linearcharge injectioneffect
of thesamplingswitches.This charge injection is proportionalto the inverseof thehold-
ing capacitorvalue[3]. Moreover, it reducestheeffectof chargesharingdueto thefollow-
Vin VoutCH
S1
Vin VoutCH
S1
S2
Vin VoutCH
S1
S3
S2
Vdd
(a) (b)
(c)
Figure 4.6: (a) Parallel sampling. (b) series sampling. (c) parallel sampling with aseries switch to reduce non-linear charge injection effect.
Cp
z1–
Chapter 4:Circuit Implementation 67
ing stageinput capacitor. The above mentionedinput capacitoris mainly the relatively-
lineargatecapacitanceof thePMOSinput transistorof thenext stageandits initial charge
belongsto the previous sample.As a result,the charge sharingof CH andthe next-stage
inputcapacitorbehavesasadiscrete-timelinearlowpassfilter with arelatively largeband-
width andit canbetolerated.To furtherreducethechargeinjectionerror, dummyswitches
(M2, M5) with half of thesizeof trackingswitches,with aninvertedclock,areutilized in
serieswith thesamplingswitches[3]. Regardingthe low orderof thepartialequalizerin
the next stageandthe chosenPAE topology, eachS/H hasto drive the input of a single
transconductoramplifier. Therefore,by appropriatebiasing,it is possibleto connectthe
transconductorsof thenext stagedirectly to theS/H blocks.This eliminatestheneedfor
an extra buffer; thereby, having less signal loss and additive distortion.
Mismatch Effects Due to Interleaving
While interleaving is becomingan effective solution in high speedlow voltagedata
acquisitionsystems[45], mismatchamongdifferentchannelsseverelylimits theprecision
of suchsystems.Thesemismatchescanbecategorizedasdifferentoffset,gain andclock
timing errors among interleaved blocks [11][46].
Vin+
Vout+
CH
Vin-
Vout-
CH
Figure 4.7: Sample-and-hold circuit.
CP CPM3
M2
M1 M6
M5
M4
M7M8 M9
φTrack_select
φHold
Master Clock
φTrack_select
Master Clock
φHold
φHold(z-1
)
M1,6: 3/0.2M2,5: 6/0.2M3,4: 12/0.2
M7: 2/0.18M8: 4/0.18M9: 6/0.2
CH: 1pF
68
Offset Mismatch Effects: The offset mismatchis due to the different non-differential
mismatcheffectsin interleavedblocks.This offsetmismatchcausesfixedpatternnoiseat
the outputwhich is repeatedevery Fs / M, whereM is the interleaving factorandin this
design M=3. This additive noise causes noise peaks at .
Gain Mismatch Effects: Gain mismatchcanbe causedby variousmismatches,suchas
different charge sharingfactorsand different time constants.As in the offset mismatch
case,thebasicerroroccurswith aperiodof , but themagnitudeof theerroris mod-
ulatedby the input frequency . Therefore,noisespectrumpeaksdueto the gain mis-
match appear at .
Clock Timing Error Effects: There are two kinds of clock timing errors: clock skew
(systematicerror)andclock jitter (randomerror).Interleavedtopologiessuffer from extra
clock skew effectsdueto the differentskews of the interleaved blocksinput clocks.Ide-
ally, thesamplingedgeof eachinterleavedS/Hclockhasto occurmidwaybetweenneigh-
boring S/H clocks. In reality, due to substantialmismatchesin frequency dividers
componentsand parallel clock paths,the samplingedgesdeviate from their ideal time
instants.This timing mismatchcausesnoisein S/H output.Thelargesterroroccurswhen
the input signalhasthe largestslope.For a sinusoidalinput, the envelopeof the error is
largestat the zerocrossingandit varieswith a periodof . Thus,aswith the gain
mismatch, the noise spectrum peaks are at .
Mismatch Effects Reduction
To reducethe above mismatcheffects,thereareseveral approachesthat canbe taken.
Theseincludeplanninga carefullayoutof theparallelcomponentsto minimizetheir mis-
matches,changingthe circuit architectureto reducethe numberof parallel components
and finally, carrying out backgroundcalibration to combat existing mismatcheffects
[47][48][49]. In this design,the interleavedpartsarelimited to thesample-and-hold(not
the entire PAE and ADC) and the requiredresolutionfor it is in the order of 8-9 bits.
Therefore,by usinga simplerS/H with minimum componentsanda careful layout, the
offset andgain mismatchesareminimized.In this regard the S/H capacitorsarebuilt by
interdigitatedmetalM2-M5, mainly usinglateralcapacitanceswith smallerunits, to give
better matching properties [50].
f noise k F s M⁄×=
F s M⁄
f in
f noise f in k F s M⁄×+–=
F s M⁄
f noise f in k F s M⁄×+–=
Chapter 4:Circuit Implementation 69
Theclock’s timing mismatchescanbeconsiderablyreducedif a singleclock drivesall
of theinterleavedS/H blocks[53]. In this design,theproperedgeof a singlemasterclock
is assignedto differentS/H blocksratherthanusinga clock divider. As a result,themis-
matcheffect is reducedto themismatchbetweentheclock-pass-controlswitchesandthe
singleswitchesin theS/Hblocks.Accordingto Monte-Carlosimulationresults,if thesize
andthresholdvoltagesof theseswitchesvarieswithin threetimesof the technologymis-
matchstandarddeviation (approximatelymaximum10%),usingthis techniquetheclock
skew is below 5 ps.Theworstcasevoltageerrorfor a sinusoidalinput is at its zerocross-
ing and can be found from
. (4.4)
For example,for a typical 600-mVpeak-to-peak100-MHzinput, theerrorvoltageis less
than 0.94 mV, which is quite tolerable for an 8-bit resolution.
Performance Evaluation
Fig. 4.8 shows the simulationresultsfor the differentialtriple interleaved S/H, with a
400-MHzclock anda 102-MHzinput tone.Theinput toneis chosensuchthat it is not an
integerdivisor of theclock frequency. Thereby, thesamplingpointscover the full ampli-
tuderange.Fig. 4.8(a)exhibits theS/H outputin the time domain.As we cansee,dueto
interleaving, almosta full clock cycle of sampleddatais availablefor theanalogprocess-
ing by thefollowing stagesandtheworstcasesettlingtime from cycle to cycle is lessthan
0.1 ns. Fig. 4.8(b) shows the S/H outputspectrum.The outputSNDR is 66 dB, or 10.7
bits.Notethatbecauseof sampling,thethird andfifth harmonicsarealiasedto thein-band
frequency range.For instance,the harmonicat 306 MHz appearsat 400 - 306=84MHz.
Fig. 4.8(c)shows thesameoutputspectrumin thepresenceof up to 10%additive random
mismatchbetweenthecomponentssizesin all interleavedanddifferentialbranches.Vari-
ousmismatchnoisetonescanbeobservedat theoutputspectrum.Thetotal SNDRin this
worstcaseis about55dB, whichmeetsthe8-bit resolutionrequirement.As expected,due
to themasterclock technique,theclock mismatchnoisecomponentis not themajordis-
tortion component,comparedto theoffsetmismatchnoisecomponentappearingat Fs/3 =
133.3 MHz.
∆v
∆t------
max
V pp π f in 2π f int( )cos⋅t 0=
V p p– π f in⋅= =
70
0 20 40 60 80 100 120 140 160 180 200−140
−120
−100
−80
−60
−40
−20
0
20
40FFT PLOT
FREQUENCY (MHz)
AM
PLI
TU
DE
(dB
)
0 20 40 60 80 100 120 140 160 180 200−140
−120
−100
−80
−60
−40
−20
0
20
40FFT PLOT
FREQUENCY (MHz)
AM
PLI
TU
DE
(dB
)
Figure 4.8: Simulation results for the differential triple interleaved S/H, with 400-MHzclock (Fs) and 102-MHz input tone (fin). (a) Output in time domain. (b) Output spectrumwithout added mismatch. (c) Output spectrum in the presence of up to 10% additiverandom mismatch between the component sizes.
(a)
(b)
(c)
Aliased 5th harmonic(5xfin-Fs=110MHz)
Aliased 3rd harmonic(Fs-3xf‘in=110MHz)
Due to offset mismatchFs/3=133.3MHz
Due to gain and clock mismatch(-fin+Fs/3)=31.3MHz
Aliased 3rd harmonicAliased 2nd harmonicFs-2xfin=196MHz
Aliased gain / clock mismatchFs/3 - (fin+Fs/3)=164.67MHz
39dB
-18dB
39dB
-28dB
1% Settling time<0.1ns
Chapter 4:Circuit Implementation 71
4.2.4 Non-overlapping Triple Phase Clock Generation and Digital
Controls
Fig. 4.9shows a simplifiedsingleendedversionof thetriple interleavedS/H with rele-
vant clocking signals.The hold control switchesselectthe properS/H. It is crucial for
their clockingsignalsnot to overlapotherwise,thesampledsignalwill bedestroyed.Fig.
4.10depictsthe circuit usedfor a non-overlappingtriple-phaseclock generatorfrom the
maininput clock.ThethreeD flip-flops areinitialized by theword 100.Then,by rotating
that word in eachclock cycle, they generatethreedifferentclockswith onethird of the
mainclock frequency anda 120degreephaseshift. Theseclocksenterthefollowing sub-
circuit comprisedof threeAND gatesandthreedelaycells.This circuit createsnon-over-
lapping intervals on the clock transitions, depending on the delay durations.
The PAE circuit, as shown in Fig. 4.5, includestwo setsof triple interleaved S/H
blocks.WhenthePAE factor is setto bezero,oneof theS/Hblocksis turnedoff by dis-
abling the buffers in Fig. 4.10.This, disablesthe hold control signals.At the sametime,
VCM
To PAEφHold_a
φHold_b
φHold_c
φTrack_select_a
φTrack_select_b
φTrack_select_c
Master Clock
Vin
Figure 4.9: Simplified schematic of the Triple interleaved S/H.
(Subtractor/Amplifier)
φTrack_select_a
Master Clock
φHold_a
φTrack_select_b
φHold_bφHold_c
φTrack_select_c
Non-overlapping
α
72
thecorrespondingS/H outputis setto VCM by theextra switchshown in Fig. 4.9. In this
case, the PAE consists of one Gm-Cell and performs as a gain amplifier.
Fig. 4.11 shows a circuit that provides different clocks with properdelaysand duty
cyclesfor S/H andtheADC. Themasterclock,aswasshown in Fig. 4.7,is a clock with a
largepositivedutycycle.This is becauseits high-level durationis thetrackingtime,which
is closeto onefull clock cycle. In addition,a multiplexer is usedfor optimizingtheADC
clock delay, by selecting among four different delays via a 2-bit digital control signal.
D QDelay
D Q
D Q
R S
R S
R S
Delay
Delay
Input CLK
RST
Figure 4.10: Non-overlapping triple phase clock generator from the input clock.
φHold_a
φHold_c
φHold_b
φTrack_select_b
φTrack_select_c
φTrack_select_a
EnableB
uffe
r w
ith e
nabl
e co
ntro
l
Ena
bled
Buff
er
Clock divider (by 3) Non-overlapped triple-phase clock generator
MU
X
ADCClock
MasterClock
To Clock Divider
ADC ClockDelay Adjustment
Figure 4.11: The circuit that provides different clocks with proper delays and dutycycles for S/H and the ADC.
InputClock
x4
x4
2
Chapter 4:Circuit Implementation 73
4.2.5 The Design of Transconductors
According to the PAE topology in Fig. 4.5, two transconductanceamplifiers (Gm-
Cells)areneededto amplify andconvert the input samplesto thecurrent.TheGm-Cells
bandwidthsshouldbelargeenoughsuchthatthesubtractionresultis settledat theinputof
theADC latchcomparatorsin a fractionof a clock cycle. Thesubtractionof thetwo cur-
rentsmusthave a minimumof 6 bits resolution.Notethatwhentwo correlatedsignalsare
subtractedfrom eachother, the resulting SNR degradesdependingon the correlation
betweentheir noise-distortioncomponents.In theGm-Cell designhere,themain resolu-
tion limitation is dueto non-lineardistortionterms.However, sincethe non-linearterms
belongto oneinput signal,they arerelatively correlatedbeforesubtraction.Thus,they do
not accumulate considerably during the subtraction.
Fig. 4.12depictsa conventionaltopologyfor a differentialtransconductanceamplifier
(Gm-Cell) of which the transconductance gain is [3]:
, (4.5)
where is the transconductancegain of the input transistors.A smaller providesa
larger , but makes more dependenton (becausein (4.5) the term
becomesmore comparableto ). Since dependson the current of the input
transistors,it varieswith input voltage;thereby, causinga significantnon-lineardistortion
at the output. As a result, in this design, an improved architecturewith inherent
Gain
Figure 4.12: Conventional transconductance amplifier circuit architecture.
VDD
M1
RS
Control
I1
Vin-
I1
VDD
M2
Vin+
I1
I1
io io
Gm
io
vi
----1
Rs 2 gm⁄+-------------------------= =
gm Rs
Gm Gm gm 2 gm⁄
Rs gm
74
linearization technique [54], as shown in Fig. 4.13, is utilized. The components sizes of
this Gm-Cell design are shown in Table 4.1.
Table 4.1: Gm-Cell components sizes
Component Sizea
a. µm/µm for transistors.
Component Size
M1-2 18 x 3.5/ 0.22 R1-2 548.7 Ω
M3-6 7 x 3/ 0.22 R3-4 203.9 Ω
M11-14 9 x 10.5 / 0.22 R5-6 401.8 Ω
M7-9 14 x 3 / 0.22 R7 2.3 kΩ
M15-18 3 x 3 / 0.22 R’1-2b
b. R’ values relates to the second Gm-Cell in the PAE circuit.
651.4 Ω
R8-9 303 Ω R’3-4 282.8 Ω
C1-2, C5-6 580.8 fF R’5-6 1.6 kΩ
C3-4, C7-8 380.2 fF M20-21 10 x3.5 /0.18
M23-24 3 x 2 / 0.18 M22 5 x3.5 / 0.18
Iout-Iout+
Gain
Figure 4.13: Linearized transconductor circuit architecture.
VDD
Vbn
Vcn
Vcp
Vbp
Vcn Vcn
Vctrl
VDD
Vbn
Vcn
Vcp
Vbp
VcnVcn
Vctrl
M1
M1
M2
M3
M5
M4M7
M9
M13
M11
M15
M17
R1
R3
R5
R7
R2
M20
M21
M22
R4
R6
R8 R9
C1 C2
M23 M24
RS
Control
M10
M8
M16
M18
I1
I2
M6
M14
M12
Vin- Vin+
Chapter 4:Circuit Implementation 75
In thisarchitecture,thecurrentof theinput transistorsM1 andM2 areforcedto becon-
stantby a feedbackloop comprisedof transistorsM3-M6. For instance,in the left-hand-
side loop, if the currentof transistorM1 increases,the voltageat the drain of M17 will
increase(dueto thefinite outputresistanceof thecurrentsourceI2 comprisedof M15 and
M17). Then,M3 andM5, asacascodeamplifier, decreasethevoltageat thesourceof M1;
thereby, reducingthecurrentof M1 andessentially, keepingit constant.Thus,theVGS’sof
the input transistorsbecomealmostconstantand the input small signal appearson the
resistorbetweenM1 andM2 sources,andproducesa currentequalto . This cur-
rent will be mirrored to the output transistorsthroughthe currentmirrors comprisedof
M3-M9.An advantagefor this architectureis that we canobtainan extra gain factorby
currentamplificationthroughthe currentmirrors.This preventsthe useof very small Rs
whenlargergainsarerequired.In this design,anextra gain of 2 is attainedby thesecur-
rent-mirror amplifiers.
In appendixA, it is shown thatthegainof thementionedfeedbackloopcanberoughly
approximatedto , it is alsoshown that the transconductancegain of this
circuit approximately is
. (4.6)
where is theamplificationgain by thecurrentmirrorsM3-M9. As seenfrom (4.6), the
effect of the of input transistors is reduced by the factor , i.e. the loop-gain factor.
Sincethelinearityof thetransconductoramplifierusedhereis highly dependenton ,
linearpoly resistorshave beenusedratherthantriodetransistorsastheir varieswith
thepassingsignal.Thegain changeis performedby switchesM20-M22 by makingparts
of theresistorshortcircuit symmetrically. Anothersourceof distortionis thefinite output
resistanceof thecurrentsourcesI1 andI2; particularly, sincetheseresistancesarenon-lin-
earin shortchanneltechnologies.Carefulbiasingandsizingof thetransistorshasenabled
the useof cascodecurrentsources;thus,considerablyincreasingthe linearity of the cir-
cuit. In addition, the current mirrors M3-M10 are of the cascodetype. This further
improvesthelinearityof thecircuit, asit makesthevoltagesof theM3-M4 drainscloseto
thedrainsof M7-M8. Otherwise,evenfor smallsignalswingstherecouldbeconsiderable
V in Rs⁄
A gm3 rds1⋅=
Gm
io
vi
----K
Rs 2 gm1 A 1+( )( )⁄+---------------------------------------------------= =
K
gm A
Rs
RON
76
linearitydegradation.Moreover, thecascodecurrentmirrorsarealsohelpful in preventing
thetransconductancegain reduction,dueto thelimited outputresistanceof outputtransis-
tors M7-M10.
Anotheradvantageof this circuit is that it usesp-channelinput transistorswhich carry
certainbenefits.First, it enablesthe useof n-channeltransistorsfor the switchesin the
front-endsample-and-holdstage.Using n-channeltransistorsin S/H circuits is crucial,
becausefor thesameon-resistancetheswitcheshavesmallersizesandcreatelessparasitic
capacitanceandcharge injection.The secondadvantageof p-channelinput transistorsis
that thebodyeffect canbereducedby connectingthebodyof the input transistorto their
sources,asshown in Fig. 4.13.Thebodyeffect directly affectsthe linearity of thecircuit
by contributingacurrentcomponent,which itself dependsonthevoltageof theinput-tran-
sistors.However, thedrawbackof a source-bulk connectionis theadditionof extra para-
sitic bulk capacitanceto thesourceof input transistor. This will causethesecondpoleof
thetransferfunction to move towardslower frequenciesasthefirst pole is roughlydeter-
minedby theequivalentRC at thedrainof theinput transistors.To improve thefrequency
responseof thecircuit two major techniquesareutilized: First, largercurrentsareusedto
increasethe of input transistorsand (seeAppendixA). Second,leadcompensa-
tion is employed when a large is chosen for lower gain values.
ThecombinationsR8-C1-M23andR9-C2-M24in Fig. 4.13performasleadcompen-
sationcircuitsto improve thestability characteristicof thecircuit andthephasemargin of
thefeedbackloops.M23 -M24 aretheenableswitchesandthey will beturnedon in cases
wherethetransconductoris setto its lowestgain value.At lower gains,thelargevalueof
increasestheloop unity gain frequency anddecreasesthenon-dominantpoles.By
enablingthecompensationcircuit, while thecapacitorsC1-C2reducesthe , addingthe
leadresistorsintroducesanextra zeroat higherfrequency. This cancelspartof thephase
lag causedby the non-dominantpoles.A detailedanalysisof the loop gain, frequency
responseandtheleadcompensationof thisGm-Cellcircuit canbefoundin AppendixA.1.
Fig. 4.14shows thesimulationresultsregardingtheovershootreduction,both in thestep
andthe frequency responsesof the transconductorcircuit, by enablingthe compensation
circuit.
gm gm3
Rs
Rs ωu
ωu
Chapter 4:Circuit Implementation 77
4.2.5.1 Gm-Cell Performance Characterization
To evaluatetheperformanceof theGm-Cells,their specificapplicationin Fig. 4.5must
beconsidered.Specifically, in conventionalVGA applicationstheinput swingis at a min-
imum whenthegain is setto maximum.However, heretheoutputof Gm-CellsA andB
aresubtractedfrom eachothersothatevenatmaximumgain theinputcanbeat full swing
along with the output after subtraction.This complicatesthe designand verification of
0 5 10 15 20 25 30 35 40
−0.4
−0.2
0
0.2
0.4
0.6
Time (ns)
Am
plitu
de (
V)
0 5 10 15 20 25 30 35 40
−0.4
−0.2
0
0.2
0.4
0.6
Time (ns)
Am
plitu
de (
V)
103
104
105
106
107
108
109
1010
0
200
400
600
800
1000
1200
1400
Frequency (Hz)
Mag
nitu
de (
mV
)
Without compensationWith lead compensation
Figure 4.14: Effect of lead compensation in transconductor circuit regardingovershoot reduction. (a) Time domain step response. (b) Frequency response.
Before compensation
After compensation
(a) Time domain step response
(b) Frequency response
78
eachsingleGm-Cell.As a result,theperformanceof theGm-Cellsareverifiedboth indi-
vidually and together in the subtractor topology.
Table 4.2 shows the specificationof a single transconductorover the gain variation-
range.Thetest-benchfor this individualperformancetestis shown in Fig. 4.15.In this test
bench,theGm-Celloutputsarepulledup to thepower supplywith a linearRC load.This
loadis setsuchthattheoutputhas600mV swingandthecapacitorvalueis roughlyequal
to theparasiticloadcapacitanceof thatnodein themaincircuit, including thenext stage
(300 fF in here).Fig. 4.16 shows the FFT of the transconductoroutput currentfor the
worstcaselinearitywhich is 58dB whenthegain is at its highestvalueandinput is at full
swing (600 mV pk-pk-diff) at 100 MHz.
Table 4.2: Transconductor Specification
Specification Value
Transconductance Gain 2.9-0.9 mA/V
Total Harmonic Distortion (THD) 58 - 66 dB
Input Swing 600 mV pk-pk diff.
3-dB Bandwidth 0.85 - 2.8 GHz
Power (single Gm-Cell) / Power Supply 6.8 mW / 1.8 V
Figure 4.15: Gm-Cell performance evaluation test circuit.
+_
GA
Vin i-
i+
Gain Control
Chapter 4:Circuit Implementation 79
4.2.6 Curr ent Amplifier and I/V Converter and Voltage Buffer
Fig. 4.17showsthecurrentamplifierstageandI/V converterandthedifferentialsource
followersasvoltagebuffers.In this circuit, thedc currentaccumulatedduringthecurrent
subtractionis removedandis thendoubledandconvertedto voltage.Eliminating this dc
currentenablestheuseof linearresistorsfor final I/V conversionandprovidesroomfor an
extra currentamplificationgain of two. During thesubtraction,thesmallsignalamplitude
is reducedwhile thedc componentsandtheevenharmonics(asopposedto oddharmon-
ics) are added together.
Open-loopn-channelsourcefollowers with single-transistorcurrentsourcesprovide
appropriatebandwidthandlinearity asthe ADC input buffer. The following ADC input
loadcapacitanceis approximately3 pF. As shown in Fig. 4.17,a separatebias-generator
circuit is usedfor this voltagebuffer in orderto prevent couplinglarge distortionsto the
restof thebiascircuit. Thevoltagebuffer sinks4 mA from a 1.8-V supply, thereby, con-
suming7.2mWof power. For a100MHz 800mvdiff-pk-pk inputand3pFcapacitive load,
the bandwidth of the buffer is 1GHz and its THD is 74dB, as shown in Fig. 4.18.
0 100 200 300 400 500 600 700 800 900 1000−140
−120
−100
−80
−60
−40
−20
0FFT PLOT
FREQUENCY (MHz)
AM
PLI
TU
DE
(dB
)
Figure 4.16: FFT of the transconductor output current for the worst caselinearity which is 58 dB when the gain is at its highest value and input is at fullswing (600 mV pk-pk-diff) at 100 MHz.
80
VDD
Vcp
Vbp
VcnVcn
M11
M9
VDD
M15
M13
Vcn
IBias-p IBias-n
Vbn
VDD VDD
Vcp
Vbp
Vcn Vcn
M12
M10
VDD
M16
M14
VDD
Iin+Iin-
Vout+ Vout-
Figure 4.17: I/V converter, current amplifier, voltage buffer.
M7
M5
M3
M2
M18
M17
M19
M1
M4
M6
M8
M1-4: 26 x 10.5 / 0.220M5-7: 3 x 2.3 / 0.220M9-12: 6 x 2.3 / 0.220
M17: 6 / 0.220M18: 6 / 0.220M19: 3 / 0.220
M13-16: 10 x 6 / 0.220
Figure 4.18: (a) FFT of the output of the ADC input buffer with 3 pF capacitance load and800-mV peak-to-peak differential 100-MHz input tone. (b) Frequency response of the ADCbuffer with 3 pF capacitance load.
0 100 200 300 400 500 600 700 800 900 1000−140
−120
−100
−80
−60
−40
−20
0FFT PLOT
FREQUENCY (MHz)
AM
PLI
TU
DE
(dB
)
103
104
105
106
107
108
109
1010
−10
−9
−8
−7
−6
−5
−4
−3
−2
−1
0
Frequency (Hz)
Am
plitu
de (
dB)
Chapter 4:Circuit Implementation 81
4.2.7 Overall Performance and Simulation Results
To assessthe performanceof the analogprocessingblocks together, the test-benches
shown in Fig. 4.19wereused.Table4.3 summarizestheoverall bandwidth,gain, settling
timeandlinearityperformanceof thecircuit for differentgains,correspondingto four dif-
ferent PAE factors.
Fig. 4.19 (a) is usedto evaluatethe individual gainsandbandwidthof the pathfrom
eachsingleGm-Cell to theADC input. This pathincludesoneGm-Cell,a currentampli-
fier, a V/I converterandthevoltagebuffer. Thefirst threerows of theTable4.3 show the
simulationresultsfor bothof thetransconductorsfor differentgain settings.In thesecond
row, the test-benchof Fig. 4.19(a)is slightly alteredsuchthat the input voltageis fed to
Gm-CellB while Gm-CellA input is ac-grounded.Thethird row exhibits thePAE/decorre-
lation factor for eachselectedgain combination,which is basicallytheratio of GA/GB.
v(ti-1)
GA
GB
G.(v(ti)-αv(ti-1))
V/Iconverter
Gain Control
Vin
BufferDifferentialOutputto ADC
Figure 4.19: Test benches for PAE performance characterization.
GA
GB
G.(v(ti)-αv(ti-1))
V/Iconverter
Gain Control
Vin
Vcm
BufferDifferentialOutputto ADC
T-1
v(ti)
(a)
(b)
(3 pF capacitive load)
(3 pF capacitive load)
α
82
As we cansee,for a larger , largergainsareused;thereby, compensatingfor thesignal
amplitude degradation after subtraction.
To evaluatethedistortionperformanceof theGm-Cellstogether, thetestcircuit shown
in Fig. 4.19(b) is used.Thedelaycell in this testbenchis idealandis equalto 2.5ns,one
periodof 400-MHzclock.Thetotal harmonicdistortionat theoutputareshown in rows 4
and5 of Table4.3.The last row of the tableshows thesettlingtime for a full swingstep
outputshown in Fig. 4.19(a).TheresultsensurethattheADC input is settledto a fraction
of the clock cycle; thereby, leaving enough time for comparator circuits.
In summary, thetotalpowerconsumptionof theanalogpreprocessingcircuit, including
theADC buffer, is 27mW. Thefinal THD beforetheADC is 47dB with a600mV differ-
ential swing. The voltageamplificationgain variesfrom 1.7 to 5.7, correspondingto a
bandwidth of 970 MHz to 680 MHz.
Table 4.3: Performance of the PAE analog processing blocks
ParameterGainSelection I
GainSelectionII
GainSectionIII
GainSelectionIV
GA / BW: Output voltage gain and
bandwidth versus Gm_Cell (A)
input (Fig. 4.19 (a))
4.5 V/V,
675 MHz
3.6 V/V,
750 MHz
2.5 V/V,
970MHz
1.4 V/V,
972 MHz
GB / BW: Output voltage gain and
bandwidth versus Gm_Cell(B)
input
3.9 V/V,
714 MHz
2.9 V/V,
900 MHz
1.24 V/V,
972 MHz
0
PAE factor: 0.87 0.8 0.5 0
THD / Gain for 10 MHz input in
PAE test set-up in (Fig. 4.19 (b))-54 dB,
1.1 V/V
-56 dB
0.9 V/V
-58 dB
1.2 V/V
- 58 dB
1.3 V/V
THD / Gain for 100 MHz input in
PAE test set-up in (Fig. 4.19 (b))-47 dB,
6.9 V/V
-47 dB,
5.5 V/V
-47 dB
3.1 V/V
-48 dB
1.3 V/V
Compensation None None None lead comp.
1% Settling time for step input
(Fig. 4.19 (a))1.4 ns 1.35 ns 1.16 ns 1.15 ns
α
α GA GB⁄≅
Chapter 4:Circuit Implementation 83
4.3 ADC Flash Architecture
A varietyof architecturesexist to implementtheADC in CMOStechnology[4][3]. The
target designspecificationfor ADC is 400-MHzsamplingwith 6-bit resolutionfor input
frequenciesup to 200 MHz. This is slightly higher thanwhat is requiredfor our target
cableapplication.Pipelinearchitecturesarepopularcandidatesfor high resolutionappli-
cations[42]. However, they suffer from large latency andoperatingthemat clocksmore
than150 MHz is problematic,mainly dueto the accuracy limitation of their inter-stage
blocks.Sincedigital processingblocksafter theADC control the front-endadaptive gain
amplifier(AGC) andadapttheclock recovery system,generallylow conversionlatency is
desired.ADCswith folding architecturesareagoodchoicefor highspeed,low power, and
low latency. However, they have bandwidthandperformancelimitations due to the cir-
cuitry that processesthe folded signal. Interpolatingarchitectureis anotherchoicethat
reducesthepowerby reducingthenumberof preamplifiers.However, it increasesthedriv-
ing load for amplifiers.Regarding the above considerations,andgiven that the required
resolution is 6 bits, a full flash ADC architecture was chosen for the current application.
Fig. 4.20showsthetop level architecturefor theflashADC usedin thisdesign,onethat
is proceededby PAE. Thearchitectureis fully differentialin orderto reducetheeffect of
power supplynoisein thepresenceof thedigital circuitry. TheADC consistsof 64 com-
Figure 4.20: Flash architecture for the analog-to-digital converter.
Vin+ -
Thermo-
meter to
Binary
Decoder
ROM
Bubble
Removal
Digital
Control
6bits
0
0
1
1
0
1
0
1
1
1
0
0
i+1i+2
i+1i+2
Ref. Voltages
Latch/FF
i-1i
i-1i
Latch/FF
ii+1
Latch/FF
ii+1
&
84
paratorswith switch capacitoroffset cancellation.The control circuits for this prototype
aredesignedsuchthatthreeautozeroingmodesof operationarepossible.Autozeroingall
comparatorstogetherperiodically, every several clock cycles,within every single clock
cycle and interleaved autozeroingtechnique(IAZ) are threeautozeroingmodesconsid-
ered.In theIAZ modetheoffsetof eachcomparatoris cancelled(autozeroed)in theback-
ground, while the other 63 comparatorsare in a comparisonstate,and a column of
multiplexersselectstheproperoutputsof theworking comparatorsfor thefollowing digi-
tal back-end stage.
4.3.1 Comparator Design
In ADCs theoffsetof eachcomparatormustbewithin a certainlevel of accuracy. Dif-
ferentialcomparatorswithout switchcapacitoroffset cancellationcancontinuouslycom-
pare the differencebetweenVin and referencevoltagesVref. However, the comparator
elementsmustbeoptimizedfor minimuminherentoffsetandgenerally, thedesignwould
bedifficult with theminimumof transistorsizes.Averaginganddigital calibrationarethe
mosteffective techniquesto improve accuracy; particularly, for continuoustime compara-
tors [55]. However, they increasethe complexity, power consumptionand areausage.
Moreover, the DC commonmodelevel of the input signal is restrictedasit providesthe
biasof theinput transistorsof thecomparatorpreamplifier. Anotherdifficulty, asshown in
Fig. 4.21, is the capacitive feedthroughdue to the Cgs of the input transistorsfrom the
input signalto thereferenceladder. Thiscausesaneffect calledresistor-stringbowing [4].
In thisADC implementationadifferentialcomparatorwith switchcapacitoroffsetcan-
cellation(autozeroing)is utilized [4]. Fig. 4.22shows thecomparatorarchitecture.It con-
Vref_iVin
Figure 4.21: Input signal feedthrough to the reference ladder in continuous timecomparators.
Cgs Cgs
Chapter 4:Circuit Implementation 85
sistsof a two-stagepreamplifieranda regenerative latch, followed by an SR latch. The
timing diagramin Fig. 4.22(b)shows the comparator’s front-endoperation.In autozero
mode,whenφaz andφaz_a is high, thetwo-stagepreamplifieris configuredin closedloop
modeandthe input sidesof the couplingcapacitorsareconnectedto the referencevolt-
ages.This resetsthe capacitorschargesby the referencevoltagesand the preamplifiers
input offset.φaz_a is thesameasφaz, exceptthat it falls a bit earlierthanφaz in orderto
prevent the charge injection effect by S3 and S4.
In comparisonmode,φaz is low andφVin is high. Thus,the feedbackloop is broken
andthedifferencebetweentheinputandthereferencevoltagesis amplifiedby thepream-
plifier. Notethattheinput offset is cancelledby theoffsetpreviously storedin thecapaci-
tors during autozeromode.The amountof this cancellationdependson the gain of the
preamplifier. To find thefinal residualoffset in moredetail,we canconsiderthefeedback
circuit in offset cancellation mode and write
, (4.7)
Comparator+-
+-
Figure 4.22: (a) The autozeroing (switch-cap) comparator block diagram. (b) Timingdiagram of comparator operation.
φaz
φaz_a
ComparatorOutput
ComparatorInput
Latch Clk
φVin
Vin
Vref
(a)
(b)
Latch Clk
C1S5
φaz φaz_a
φaz_aS4
S1
S2
φaz
φVin
φVin
S3
S6To Digital
Backend
Vref +
Vref -
Vin +
Vin-
Track Comparison Mode
Reset Mode
(autozeroing)
C2
LatchSRLatch
1
2
A–( ) V 12 V OSA–( ) V 12=
86
whereA is theopen-loopamplifiergainand is theamplifierinputoffset.Therefore,
assuming Vref+=Vref-, the capacitors are charged totally by
. (4.8)
Thus, the residual input offset will be reduced byA+1 as
. (4.9)
In additionto , the input referredlatchoffset andthecharge injection
mismatchbetweenS5 andS6 ( ) contributeto thecomparatorinput offset[4]. Thus,the
total offset will be
, (4.10)
where . Generally, due to charge injection mismatch,KT/C noise,and
leakageconsiderations,a largevaluefor theinputcouplingcapacitorsis desired.However,
the loadingeffect of their parasiticsto the previous buffer stageandthe time constantin
the resetmodemustbe taken into account.Thechosenvalueof C in this designis about
300 fF. An interdigitatinglayout structureusing metal layers2-4 reducesthe parasitics
such that the settling time of nodes 1 and 2 meets the target speed requirement.
4.3.1.1 Circuit Description
Fig. 4.23 shows the circuit architectureof the comparatordesign.The corresponding
componentsizesarelistedin Table4.4. Fig. 4.23(a)showsthepre-amplifiercomprisedof
two cascadedNch-MOSdifferential input amplifiers,loadedby non-silicidedpoly resis-
tors.Thepreamplifierprovidesa propergain-bandwidthto reducetheeffect of theoffset
and the kickback noise of the following regenerative latch.
Thedc currentof eachpreamplifierstageis 164µA. Usingresistive loadsratherthan
diodeconnectedloadsenhancesthespeeddueto lessparasiticloadcapacitance(5.3fF for
eachloadresistor)andbetterrecovery from overdrivesituation.Thetotalbandwidthof the
V OSA
V C0V 12
A
A 1+-------------
VOSA
= =
V OSA'
V 'OSA V OSA
A
A 1+-------------
VOSA
–V OSA
A 1+-------------= =
V 'OSA V OSLCH A⁄
∆q
V OS residual( )V OSA
A 1+-------------
∆q
C-------
V OSLCH
A--------------------+ +=
C C1 C2= =
Chapter 4:Circuit Implementation 87
two stageamplifier is 550MHz with a total gain of about26 dB andtheunity gain band-
width is 4.4GHz.A usefuloptimizationtechniquefor multiple stageamplifiersaccording
to their numberof stagesandgains,canbefound in [56]. Two majorpolesarecreatedat
the output of each amplifier as
, (4.11)
where is thepull-up loadresistorand is theloadcapacitanceat theoutputof each
amplifier. Whentheautozeroingloop is closedthe of thesecondamplifier is larger
Vbn
Vcn
VDD VDD
Vbn
Vcn
VDD VDD
VDD VDDVDD VDD VDD
M1 M2 M3 M4
M5M7
M9
M11
M8
M10
M12
R1 R2 R3 R4
M13
M15
M14
M16
M21M23
C1
M22
M19 M20
M24
M25
M17 M18
M26
M31 M32
M27 M28
M29 M30
M6
C2
MD6
MD5
Figure 4.23: Comparators building blocks. (a) two-stage pre-amplifiercomparator. (b) Comparator and SR latches.
164µA 164µA
Vin+
Vin-
Vref1+
Vref2+
Vref2-
Vref1-
LatchClock
(b) Comparator and SR Latches
(a) Pre-amplifier
Vamp+Vamp-
outputComparator
bits
Vamp-Vamp+
p1
RC load
-----------------=
R C load
C load
88
dueto extra loadingparasiticof the loop. This makesthe secondamplifier pole smaller
and helps the stability of the autozeroing feedback loop.
TransistorsM5 andM6 arethefeedbackswitcheswhich turnon in autozeromodeandare
Pch-MOSbecauseof therelatively high biasvoltage(1.4V) acrossthem.Thedc common
mode of the input signalsand referencevoltagesare designedto be 450 mV. This is
differentfrom thecomparatorpreamplifierinput, which is around1.4 V. This is possible
due to the existing couplingcapacitorsin this comparatorarchitecture.The lower input
commonmodeenablesthe useof NMOS front-endswitchesandensuresreliableswitch
operationwithoutbootstrapclocking[42] or very largeswitchsizes.In theautozeromode,
theswitchesM5 andM6 turn off prior to M9-12.Therefore,thechargeinjectionsof M9-
12 do not affect thecouplingcapacitorscharges.To reducethechargeinjectionandclock
feedthroughby M5-6 ontothecouplingcapacitors,their sizesareminimizedanddummy
transistors MD5-6, with half the size of M5-6, are added to the circuit.
To attainenoughresolutionfor a relatively low input swing(600-800mV pk-pk diff.)
andlow VLSB (9 -12 mV), a two-stageamplifierprovidesa gain of 20.Sucha gain would
costmorepower andcausea speedlimitation on the comparatorpreamplifier. However,
augmentingtheinputswing,by increasingthegainof thepreviousstage,is moredifficult.
Thereasonfor this is that thelinearity performanceof theamplifiersbeforethecompara-
tors shouldmeet the resolutionrequirementof the ADC while this is not the casefor
preamplifierswhich only amplify thesignof thedifferencebetweensignalandreference
Table 4.4: Comparator circuits
Transistors W/L (µm/µm) Element Sizes
M1-4 5x2/ 0.220 M23-24 2x1.2/0.200
M5-6 3x2/0.200 M27-28 4x1.2/0.180
M7-8 3x2/0.180 M29-30 2x1.2/0.180
M9-12 3x1/0.180 M31-32 4x2.4/0.180
M13-16 6x1/0.220 INV1-2(N,P) 2x900/0.180
M17-18 1x1/0.200 R1-4 5 kΩ
M19-20 2x1.2/0.200 C1-2 250 fF
M21-22 4x1.2/0.200 MD5,MD6 3/0.200
Chapter 4:Circuit Implementation 89
voltages.Accordingto thesimulationresultsshown in Fig. 4.24,for theworstcasesitua-
tion whenthe input variesfrom full swing above the referenceto 3 mV below the refer-
ence,it takes1.6nsfor thepreamplifierto provide 65 mV at theinput of theregenerative
latch.This ensurescorrectcomparisonresultsagainstworst-caseoverdrive, anddynamic
and mismatch offset effects.
Theregenerative andSRlatchesareshown in Fig. 4.23(b).Thecoreof bothof themis
a conventionalbackto backinverterarchitecture.Thecomparatorlatchoutputis resetto
the power supply throughM23-24, While the preamplifieris tracking the input signal.
Also, in thetrackingperiodM26-27turn off; thereby, no staticpower is consumed.M17-
18 injects enoughdifferential currentto force the latch to go to the properstatein the
regenerationprocess.At theend,theSRlatchpreservestheCMOSlevel of thecompara-
tor output during the full clock cycle.
65mV
3mV
1.6 ns
5% settling 0.35ns
ComparatorOutput
Regenerativelatch Output
Latch Clock
PreamplifiersOutput
Input DifferentialInput and
Voltage
Reference
Input
Reference
Volt
Figure 4.24: Comparator performance, worst case for extreme overdrive to theweakest conversion, with a clock of 500-MHz, and input changing by 250 MHz.
0.24ns
0.37ns
90
The latching time for the back-to-back inverters can be approximated by [3]
, (4.12)
where is the initial input voltage difference, is the final desiredlogic
differentialvoltagelevels,and is thetransistorschannellength.Therefore,to maximize
speed,the channellengthhasto be minimized.However, dueto matchingconsideration
for the comparatorlatch transistors,the chosenchannellengthsareslightly greaterthan
the minimum, i.e. 200 µm. For the SR latch, sincethe inputsarealreadycloseto logic
values, matching is not a major issue, and the transistors channel lengths are minimized.
4.3.2 Autozeroing Techniques
Allocating extra time for a resettingor autozeroingoperationis oneof the disadvan-
tagesof switch capacitorcomparators,comparedto continuous-timeones.As shown in
Fig. 4.22(b), after eachautozerocycle, several comparisoncycles can be performed,
dependingon thechargeleakageof thecouplingcapacitors.To estimatethelongesttoler-
able interval between two autozero cycles we can write [57]:
(4.13)
where is the leakageonto the couplingcapacitorC and is the permissible
error voltage.Thecurrent is mainly flowing throughthe reversebiasedPN junction
of the autozeroingswitchesand is roughly 20 pA. Therefore,for fF and
mV, the accuracy of ADC is not affectedup to around67 µs. Experimental
resultson theprototypechip showedthat theADC outputis valid up to about40 µs after
each single offset cancellation.
Conventionally, an autozerocycle canbe performedat every clock cycle if the clock
periodis long enough.In someapplications,suchasdisk-drive readchannels[59], ashort
periodof time occursperiodically, wherethe outputof the converter is not used.Those
time slots can be utilized for autozeroingpurposes.Another solution includesusing an
interleavedautozerotechnique(IAZ), wheretheoffsetof eachcomparatoris cancelledin
the backgroundwhile the other comparatorsare in comparisonmode [57]. The clock
T ltch
L2
V eff
----------V iclog∆
V 0∆-----------------
ln∝
V 0∆ V iclog∆
L
T H
T H
C 0.5V LSB( )I lkg
------------------------------<
I lkg 0.5V LSB
I lkg
C 300=
V LSB 9=
Chapter 4:Circuit Implementation 91
control logic in thecurrentwork is designedsuchthat it is ableto exploit all of theabove
three modes of autozeroing technique.
Interleaved Autozeroing (IAZ)
As seenin Fig. 4.20,by addingan extra comparatorrow anda setof multiplexers,a
singlecomparatorrow canbe calibratedin the backgroundwhile the othercomparators
arein comparisonmode.Fig. 4.25demonstratestheup/down orderof thecomparatorscal-
ibrationsandthealternative usageof theneighboringreferencevoltages.TAZ =8 TCLK is
thetotal calibrationtime interval. Thelongestinterval betweentwo calibrationoperations
happensfor theendcomparators.This is 126Tclk, i.e. 2520ns for a 400-MHzclock fre-
quency.
A detailedtiming diagramof the control signalsfor the ADC designin Fig. 4.20 is
depictedin Fig. 4.26.During theinitializationof theADC, all comparatorsareresetto the
properreferencevoltages.At themomentof transferringthecomparatorfrom autozeroing
into comparisonmodetheamplifieroutputis distortedby theclockfeedthroughandpossi-
bly ringingbecauseof theopeningof thefeedbackswitch.Therefore,asseenin Fig. 4.26,
four clockperiodsareassignedfor resettingthecomparatorandtheotherfour areusedfor
extra delays,beforeandafter resetting.Autozeroingstartsoneclock after disconnecting
Vin from thecouplingcapacitors.Theinput signalVin will bereconnectedoneclock after
autozeroingis terminated.Then,aftertwo moreclockcycles,theoutputof thecomparator
Ref63
Ref62
Ref1
Ref1
Ref63
Ref63
Ref2
Ref63Ref63
TIME
-TAZ TAZ 62TAZ 63TAZ 64TAZ 125TAZ 127TAZ0 126TAZ
64
63
2
1
CO
MP
AR
AT
OR
RO
W N
UM
BE
R
Figure 4.25: Interleave up/down autozero demonstration.
92
will be selectedby the multiplexer and becomesavailable for the following digital cir-
cuitry. Theseextra delaysensuretheisolationbetweencalibrationandcomparisonmodes
and the settling of the amplifier outputs after autozeroing.
The hardwaregeneratingthe control signalsfor IAZ andotherautozeroingmodesis
shown in Fig. 4.27.WhenthesignalsAz_mode2_enandAz_mode2_enaredisabled,IAZ
controlsignalswill begenerated.As shown in Fig. 4.27(a),anup/down serialshift regis-
ter, clocked with oneeighthof the main clock, generates64 commandsignalsAZen(i).
This determineswhich row hasto undergo a calibrationprocess.The circuits shown in
Fig. 4.27(b)producethe final control signalswith properdelays,asshown in Fig. 4.26.
WhenAz_mode2_enis high, while IAZ signallingis disabled,thecircuit in Fig. 4.27(b)
generatestwo non-overlappingclocksfor the autozeroingandcomparisonmodeswithin
eachclock cycle. The lastmodeof operationoccurswhenAZ_mode1_enis high. In this
mode,usingasynchronoussetandresetof theserialshift register, all of thecomparators
arecalibratedsimultaneously. This samefunctionis performedduringtheinitialization of
the circuit when thereset signal is low.
φaz(3)
φVin(3)
φmux(3) Vref2/Comp3 selected
Vref2
Vref1
Vref1
Vref2
Vref3
Vref1/Comp2Vref2/Comp2 selected
Vref1/Comp1 selected
Vref2
Vref3
Vref1
Vref63
Figure 4.26: Timing diagram of the control signals for interleave autozero technique.
φaz(1)
φVin(1)
φmux(1)
φaz(2)
φVin(2)
φmux(2)
φmux(64)
CLK
selected
Row #
Chapter 4: Circuit Implementation 93
D Q
Q
D Q
Q
D Q
Q
D Q
Q
Figure 4.27: The logic circuits generating control signals for autozeroing.
φaz(1)
φVin(i)
φmux(i)
Up/DownSerialShiftRegister
Up/Down
φVin(1)
Reset
Set
Clock
φref_selct
φaz1(i)
φaz2(i)
CLKAZ(i)
S
R
Q
Q
Row (1)
AZmode2
CLK
φaz_mode2
φVin_mode2
φaz_mode2
Reset
Az_mode1
A_mode2_en
(c) Non-overlap clock generation for autozrroing mode (2),
φaz_a(i)
φmux(1)
φaz1(1), φaz2(1), φaz_a(1)
φVin(1)
Row (1) φmux(1)
φaz1(1), φaz2(1), φaz_a(1)
Az_ext
(a)Block diagram of cControl signal generation for all rows
(b)Inside the logic block for control generation in each row
φaz_mode2
T-2
Control
ClkAZ(1)
ClkAZ(64)
CLK
several cycles when Az_ext=1
Az_mode2_en=1
Az_mode2_en=0
Interleaved autozeroing
Az_mode1_en=1
Az_mode1_en=1
Az_mode1_en=0Az_mode2_en=0
Aurozeroing every cycle
Autozeroing once in every
8CLK
s
φref_selct
CLK
94
4.3.3 ADC Reference Voltages
A differential reference ladder composed of two separate pieces of silicided poly resis-
tors with the value of 1.6 kΩ were used to generate the reference voltages. Two separate
resistor ladders, as compared to a single ladder, provide the possibility of calibration for
PAE/ADC systematic offset error. For example, in Fig. 4.28 in the case of
mV and mV in the single ladder, the reference voltages vary from 400 mV to
-400 mV. This demands a zero offset to cover the ADC full range. In the dual ladder, for
instance, if there exists an offset of +50 mV, then by shifting the and by 50
mV, the reference voltages will be in the range of 450mV to -350mV. This can compensate
for the mentioned offset.
The reference-ladder resistance is required to be low in order to accelerate the compar-
ators calibration process, in addition to reducing the coupling of the input signal onto the
reference ladder through the switch capacitor resistance. This coupling is demonstrated in
Fig. 4.29 and it should be mentioned that it becomes negligible when the comparators are
autozeroed, every several cycles. Based on the above considerations, power consumption
and layout constraints, each resistor division was chosen as 25 Ω.
V max 650=
V min 250=
V maxp V maxn
Figure 4.28: Reference voltage generation. (a) Single ladder. (b) Dual ladder.
Vmax
Vmin
Vmaxp
Vminp
Vminn
Vmaxn
Vref(62)
Vref(61)
Vref(1)
Vref(0)
Vref(62)
Vref(61)
Vref(1)
Vref(0)
(a) (b)
R=25Ω
Chapter 4:Circuit Implementation 95
Thecommonmodevoltageof theADC inputsignalis designedto becloseto thecom-
monmodeof thereferencevoltages,i.e. 0.4 V. This assuresthatcomparatorinput ampli-
fier doesnot exceedits properinput common-modebiasrangein comparisonmode.This
is becausethegateof thepre-amplifierinput transistors(VG in Fig. 4.29)is shiftedby the
value in comparison mode. The maximum possible shift of VG is
. Thus,thecommonmodeof and hasto becloseenoughsuch
that the amplifier biasingpoint remainsin its properlinear rangeandthat the voltageof
the VG does not exceed the power supply regarding the reliability issues.
4.3.4 Digital Back-End
Dueto thesample-and-holdprior to PAE, theADC input at the time of the latchingis
held. Thus,mismatchbetweenlatch delaysamongthe comparatorsand different clock
cycles doesnot producesignificantdistortion or sparkleerrors[4]. However, to further
reducetheprobabilityof sparklecodes,a columnof 4-inputAND gatesthatdetect0001
transitionsis used.Furtherbit error reductiontechniques,suchas the onespresentedin
[57][58], could be used;althoughin this PAE/ADC prototypeimplementationwerenot
utilized. Finally, asshown in Fig. 4.30,the AND gatesoutputcodewordsarefed to the
binarydecoderROM andthefinal outputsarefed into digital I/O drivers.Theschematic
of the ROM decoder is shown in Fig. 4.30.
V in V ref–
V inmaxV re f min
– V in V ref
Vref (i)
Vin
Cp
Req
T
CP
----=
Figure 4.29: Input signal feedthrough to the reference ladder in a switch-capacitor (autozeroing) comparator.
VG
96
4.3.5 Layout
Dueto thehigh samplingspeedandthecomplexity of thetotal circuit, thelayoutwas
carefully performed,with appropriateconsideration,to minimize coupling and skew
effects.Careful separationof the analogand digital and I/O grounds,the useof metal
shieldsaroundsensitive signals,the separationof the chip into two digital and analog
sides,includingtheirPADs anddrivers,thebufferinganddistributingof theclock in a tree
shapewerepartof theseconsiderations.Every two comparatorsandcontrolcircuit gener-
atorswereplacedin onerow. Thus,the distancebetweenthe first and the last row was
reducedby a factorof two. This improvedmatchingandreducedclocksandsignalsskew
alongthechip. Interdigitatedcapacitorsusingmetals2-6wereusedfor comparatorcapac-
itors. Thesecapacitorsutilize lateral fringing capacitancesandshow bettercapacitorper
area and matching properties compared to vertical metal to metals [50].
Figure 4.30: Thermometer to binary ROM decoder.
r62
r61
r60
r2
r1
Chapter 4:Circuit Implementation 97
4.4 Bias Circuit
Fig. 4.31depictsthebiascircuit. It generatesthereferencevoltagesfor differentcurrent
sourcesin the circuit. The coreof this circuit is the loop madefrom M1-M8, which is a
combinationof thewell-known constant-gmcircuit with wide swingcascodecurrentmir-
rors [51][52]. If (W/L)8 = 4(W/L)7, to a first order approximation, it can be shown that
. (4.14)
Therefore,the transistorstransconductancesareindependentof power supplyvoltageas
well as processand temperaturevariations.The transconductancesof other transistors
M1
Figure 4.31: Bias circuit.
M2
M4M3
M5
M7 M8
M6
M9
M10
M11
M14
M13
M12
M18M17
M15
M16
R2(Off-chip)
R1(On-chip)
Mcp2
Mcn2
Mcn1
Vbp
Vcn
Vbn
Vcp
Mcp1
Rbias
Table 4.5: Bias circuit component sizes
Transistors W/L (µm/µm) Components Sizes
M1-4 1x3/ 0.220 M15 1/5
M5-7 1x10.5/0.220 M16 3/0.220
M8 4x10.5/0.220 M17-18 1x3/ 0.220
M9-10 6x10.5/0.220 Mcp1,2 - Mcn1,2 8x20/3.5
M11 1x3/ 0.220 R2 1 kΩ
M12 1x10.5/0.220 R1 400 Ω
M13-14 6x3/ 0.220 Rbias (R1+R2) 1.4KΩ (0.4 + 1)
gm71
Rbias
------------=
98
drivenby thesamebiascircuit arestabilizedaswell asthey aremainly dependenton the
ratio of the corresponding transistors geometries.
Consideringthe secondaryeffects suchas body effect, finite output resistancesand
mobility degradation,theequation(4.14)canslightly deviatefrom its stabilizedform [5].
In thisdesign,by usingtheRbiasat thePchtransistorsandconnectingthebodyandsource
of M8 together, thebodyeffect erroris considerablyreduced.In addition,theeffect of the
limited output resistanceis reducedby usingwide swing cascodes.The performanceof
the biascircuit hasbeenverified at differenttemperaturesandprocesscornersat a 1.8V
supply, within 10%variation.If thepower supplydropsup to 10%,in a worstcasesitua-
tion of slow precess(SS)andT=100C, thereis a possibility thatcascodetransistorsM10
andM13 move slightly to theedgeof the triode region. However, this doesnot harmthe
performanceof the main bias circuit as the main loop transistorsremain in the active
region. For lower power supplyvoltagesa modifiedversionof this biascircuit usingop-
amps can be used [60].
Onedifficulty with thisbiascircuit is thepossibilityof oscillationif thegainof thepos-
itive feedbackloop exceedsunity at higher frequencies,due to the padandpin capaci-
tancesat thesourceof M8. To avoid this,partof Rbias (400Ω) is placedon-chip.Thetotal
Rbias in this circuit is 1.4 kΩ andthe currentof the current-mirrorloop is about84 µA.
This currentvalueenablesthe useof a reasonableunit sizefor all of the currentsource
transistorsin thecircuit; thereby, providing bettermatching.Anotherconsiderationis the
requirementof astart-upcircuit to ensurethatthepositive feedbackloopdoesnotbecome
stuckatzerocurrents.Thisstart-upcircuit automaticallyturnsoff afterthecircuit currents
arestabilized.Finally, to further stabilizethe biasvoltagesanddecouplehigh frequency
noises,2pF MOS capacitorsareutilized. Note that the Pchbiasesaredecoupledto Vcc
and the Nch biases are decoupled to the ground.
4.5 Summary
In this chaptercircuit designissuesfor thecombinationof 2-tapPAE anda 6-bit 400-
MHz ADC werepresented.All blockson thesignalpatharefully differential.Thechosen
topologyfor PAE usestwo setsof triple interleavedsample-and-holds(S/H) followedby
two variablegain transconductors,acurrent-to-voltageconverterandanADC inputbuffer.
Chapter 4:Circuit Implementation 99
A single masterclock for interleaved sample-and-holdreducedthe mismatchbetween
clock edges.Theharmonicdistortionof theS/H in thepresenceof up to 10%addedmis-
matchbetweeninterleavedblockswas-56dB. Anotherchallengingpartof thePAE design
wastheanalogsubtractor, comprisedof two variablegain transconductors.Dueto thesub-
tractionoperation,evenfor largergains,theinputcanbecloseto full swing.Thetranscon-
ductorsharmonicdistortionrangewas-58 to -66 dB with a bandwidthof 850MHz to 2.9
GHz, respectively. EachGm-Cellconsumed6.9mW at 1.8V supplyto accommodatethe
properbandwidthandsettlingtime.PAE outputTHD beforetheADC, includingtheADC
buffers, was 47-54 dB for 100 and 10 MHz inputs, respectively.
A 6-bit 400-MHzADC wasdesignedusingaflasharchitecture.An autozerooffsetcan-
cellationwasusedfor thecomparators.To have flexibility in the testingof theprototype
chip,threemodesof interleaved,periodiceverycycle,periodiceveryseveralcycleautoze-
roing wereapplied.Eachcomparatorconsistedof a two-stagepre-amplifierfollowed by
regenerative andSR latches.Accordingto simulations,the comparatorswerecapableof
resolving3-mV againsta worstcaseclock speedandoverdrive situation.The6-bit ADC
outputwasprovided by a digital back-endcircuit consistingof bubbleremoval, a ROM
decoderandeventuallyopen-drainPAD drivers.Opendraindigital PAD driversenablethe
useof anoff-chip pull-up loadresistor, dependingonthetest-equipmentloadingcapacitor.
Carefullayoutof thewholecircuit, particularlythefloor planningof theADC rows,wasa
critical part of the design implementation and was reviewed in this chapter.
100
101
CHAPTER
5.1 Introduction
In this chapter, we discussthemeasurementresultsfor theprototypechip discussedin
Chapter4. Thechip wasfabricateda in standarddigital 0.18-µm CMOStechnologywith
six metal layers.The microphotographof the chip is shown in Fig. 5.1. The chip was
insertedin a CFP-80-pinpackageand the 80-pin IC was solderedon a CFP80-TFtest
board as shown in Fig. 5.2
The chip consistsof a partial analogequalizeranda 6-bit flashanalog-to-digitalcon-
verter. In additionto theoverallperformancecharacterizationsuchaspower, SNDR,DNL
andINL, theperformanceof thechip in a400-Mb/s240-mcoaxialcablesystemwaseval-
uatedand the advantageof having a PAE prior to ADC, (i.e 2-3 bits improvement),is
demonstrated.The otherchannelmodelsand lossessuchas622-Mb/s300-mcablehas
beenemulatedby an arbitrary function generatorand testedon the chip. A list of mea-
sured chip specification can be found at the end of this chapter.
5.2 Test Set-up and Functional Testing
Fig. 5.3 shows thetestset-upfor testingthechip with input tonesat differentfrequen-
cies.Thedigital outputPADs arepulledupby 100-Ω resistorsto a1-V supplysincetheir
Experimental
Results5
102
.
Figure 5.1: Chip microphotograph consisting of the partial analogequalizer and the 6-bit ADC in 0.18-µm CMOS technology.
Bias Circuit
ADC
Dig
ital
Ana
log
Analog
Driver
Digital
I/O
(0.74 mm2)
(0.09 mm2)
I/O
Partial
Equalizer
Analog
(PAE)
Figure 5.2: printed circuit board (PCB) layout (PCB-TF80).
Chapter 5: Experimental Results 103
180 DegreeSplitter
Bias T
Bias T
TLA714 LogicAnalyzer
Computer
Off-chip DSP /
LPFilter
Bias
External Clock
6-bit ADCOutput codes
(Optional)
100Ω
6
1 V GND3
In+
In-
GND1
VDD1
α Selection
Signal GeneratorROHDE & SCHWARZ
GND2
VDD2Test Control Signals
50Ω50Ω
Oscilloscope
/ Spectrum
PAE An. Out+PAE An. Out-
b0
b1
b2
b3
b4
b5
FFT Analysis
6
ClockGeneratorDG2030
GND3
GN
D A
nalo
g
VD
D A
nalo
g
GN
D D
igital
VD
D D
igital
GN
D O
utp
ut
Dri
ver
VD
D O
utp
ut
Dri
ver
1.8
V
1.8
V
1.8
V
GND1
GND1
GN
D1
VD
D1
GN
D3
GN
D2
VD
D2
VD
D3
Clk
Prototype
CHIP
50Ω
50Ω
Figure 5.3: Test set-up for testing with sinusoid inputs at different frequencies.
Analyzer
VDD1
Rbias
1K
VDD3
100pF
GND3
1nF 100 nF
VDD2
100pF
GND2
1nF 100 nF
VDD1
100pF
GND1
1nF 100 nF
Ext_Autozero
4
Referencevoltages
1nF100pF
104
correspondingon-chip drivers are open drain type. The low pull-up resistorsprovide
appropriatetime constantconsideringthe logic analyzerprobesinput capacitances(1-2
pF).
To achieve a betteron-boardsupplynoiserejection,separatesuppliesandgroundsare
usedfor analog,digital and PAD-drivers circuits. TheseseparateVDDs and GNDs are
connectedat thepowersupplyoutletsandthey areseparateon thePCBaswell [61]. A set
of paralleldecouplingcapacitorsareusedbetweendc suppliesandgroundsto decouple
thepowersupplynoiseatdifferentfrequency ranges.Mostof themeasurementshavebeen
basedontheADC digital outputcodes,capturedby theTLA714 logic analyzer(LA). This
outputrepresenttheperformancesof boththeADC andthefront-endpartialanalogequal-
izer. However, to evaluatethePAE outputdirectly, apairof on-chipdifferentialanalogtest
switcheson thesignalpathareenabledanddrive thesignalto theoutputPADs. Fig. 5.4
shows thePAE outputwith a 1-MHz input toneanda S/H clock of 6 MHz while thePAE
factoris setas . In this experiment,thedc biasof thePAE outputwasverifiedas
well.
α 0.8=
Figure 5.4: The PAE output captured by 100-MHz Tektronix oscilloscope for a 1-MHz sinusoid input tone and a sample-and-hold clock of 6 MHz.
Input
Output
Chapter 5: Experimental Results 105
Fig. 5.5 shows the spectrum of the PAE output for a 10-MHz input tone while S/H
blocks were running at 100 MHz. The observed THD for this measurement was 42 dB.
The measured performance at this stage was limited, due to the large loading effect of the
test equipment, the limitation of the high current analog PAD driver, and additive distor-
tion by the analog test switches on the signal path. The mentioned test circuits were
mainly designed for functional test purposes. More accurate measurements, particularly at
higher speed, were performed by sampling the PAE outputs by the existing on-chip ADC
and analyzing the ADC output codes.
Fig. 5.6 and Fig. 5.7 show the output codes and their equivalent reconstructed wave-
form on the TLA714 logic analyzer for a 10-MHz and 85-MHz input tone at 250-MHz
clock frequency while the front-end PAE was active with the factor of . Note that
for (which corresponds to maximum partial equalization) the transconductors
gain were set to their maximum and as a result, the worst case situation at higher speed
inputs occurs. In Fig. 5.7, since the input frequency is large compared to sampling fre-
quency, the quality of the large swing transition by the ADC circuits, via an examination
of the beat envelope tone appearing on the reconstructed signal, can be observed [4]. In
Figure 5.5: The PAE output frequency response for a 10-MHz input tone and a 100-MHzsampling frequency.
α 0.8=
α 0.8=
106
this measurement,for a 250-MHzclock frequency andan85-MHz input tone,threeenve-
lope beats with 120 degree phase shifts appeared, with a frequency of
. (5.1)
The(total harmonicdistortion)THD of thesebeatsenvelopes,obtainedby FFT analysis,
was 33 dB.
Among the comparatorautozeroingmodes,periodic autozeroingwas utilized for all
measurements.It wasseenthat the ADC outputwasvalid for 40 µs after eachautozero
pulse.The interleavedautozeroingmodewasnot functioningproperlyin the testedchips
due to possiblebreakdown of somelogic gatesin the complex logic structure.Due to
limitation of thenumberof availabletestchipsandboards,it waspreferableto usethem
for major characterizationand performancetests using a well-functioning periodic
autozeroing mode.
fbeat
fin
fclk
k------------– 85Mhz
250MHz
3---------------------– 1.66Mhz= = =
Figure 5.6: ADC output bit streams and their equivalent magnitude at a 250-MHzsampling clock for a 10-MHz input tone captured by a TLA714 Logic Analyzer.
Chapter 5:Experimental Results 107
5.3 Dynamic Test and SNDR Measurement [62]
SNDR:Signal-to-noiseanddistortionratio (SNDR) is a well-known parameterfor ADC
dynamicperformanceevaluation.For sinusoidalinputsignalsSNDRis definedastheratio
of rms signal to rms noise, including the harmonic distortion components or
(5.2)
where is thermsoutputsignallevel and describesthe
rms sum of all spectral components below the Nyquist frequency, excluding dc.
ENOB: In the case where the input signal is sinusoidal, ENOB is related to SNDR as
. (5.3)
Figure 5.7: ADC output bit streams and their equivalent magnitude at 250MHzsampling clock for a 85 MHz input tone captured by TLA714 Logic ANalyzer. Abeat of 1.66 MHz (85-250/3) with 33 dB THD is seen.
SNDR 20ASIGNAL rms[ ]
ANOISE HD+ rms[ ]--------------------------------------------log=
ASIGNAL rms[ ] ANOISE HD+ rms[ ]
ENOBSNDR 1.76–( )
6.02-------------------------------------=
108
SFDR:Onedefinitionof spurious-freedynamicrange(SFDR)is theratio of RMS ampli-
tudeof thefundamentalsignalcomponentto theRMS valueof thelargestdistortioncom-
ponent [62]. SFDR indicates the practical output dynamic range of an ADC.
By applyingdifferentsinusoidinput tones,andusingthe FFT of reconstructedsignal
form the prototypePAE/ADC outputcodes,the dynamicperformanceof both ADC and
front-endPAE wasevaluated.Fig. 5.8 (a) andFig. 5.8(b)show theFFT plotsof theADC
outputfor samplingfrequenciesof 250and400MHz with input tonesat45and124MHz,
correspondingly. Fig. 5.9 exhibits theSNDRversusdifferentinput frequency at different
samplingfrequenciesrangingfrom 100MHz to 400MHz. ThepeakSNDRat 250-MHz
clock and45 MHz input tone is about34 dB andslightly decreasesat higher input fre-
quencies.TheequivalentENOBfor 34dB SNDRaccordingto expression(5.3) is 5.4bits.
In this measurement,PAE hasbeenenabledwith a maximumpartial equalizationfactor,
i.e. . In this case,the high gain of the Gm-C amplifiers
causestheworst caselinearity for theamplifierpart.Due to thehigh passeffect of PAE,
the input signalat high frequencieshasa low swingandthis relaxestheS/H functioning.
The combinationof thesetwo effectsmakesthe variationof the SNDR versusinput fre-
quency relatively flat for the combinedPAE /ADC architecture.By settingthe equaliza-
tion factor to zero,the PAE part of the circuit actsasa sample-and-holdstagewith a
close-to-unitygain amplifier, i.e. . In this case,while the
gain andinput full scaleis fixedat differentinput frequencies,SNDRdropsevenly from
35 dB to 31.5 dB.
G 1 αz1–
–( ) 5.7 1 0.8z1–
–( )=
α
G 1 αz1–
–( ) 1.2 1 0z1–
–( )=
Chapter 5: Experimental Results 109
0 20 40 60 80 100 120 140−70
−60
−50
−40
−30
−20
−10
0FFT PLOT
ANALOG INPUT FREQUENCY (MHz)
AM
PLI
TU
DE
(dB
)
Sampling Clock: 250 MHzInput Tone: 45 MHzSNDR= 34 dBSFDR= 45 dB
Figure 5.8: FFT plot of the PAE / 6-bit ADC output. (a) 250-MHz sampling clockand 45-MHz input tone, SNDR=34 dB, SFDR=45 dB. (b) 400-MHz sampling clockand 124-MHz input tone, SNDR=30dB, SFDR=37 dB.
0 20 40 60 80 100 120 140 160 180 200−70
−60
−50
−40
−30
−20
−10
0FFT PLOT
ANALOG INPUT FREQUENCY (MHz)
AM
PLI
TU
DE
(dB
)
Sampling Clock: 400 MHzInput Tone: 124 MHzSNDR= 30 dBSFDR= 37 dB
3rd Harmonic@400-124x3=28 MHz
-37dB
2nd Harmonic@400-124x2=152 MHz
(a)
(b)
110
5.4 Code Density Measurement and INL/DNL
Codedensitytestis acommonapproachfor thecharacterizationof ADCs’ non-lineari-
ties.The outputcodedensityor histogramis the numberof timesevery individual code
hasoccurred[63]. Differential non-linearity(DNL) for an output codeis relatedto the
deviation of its correspondinginput rangefrom the averagedstandardbin width. There-
fore, the numberof output codesoccurrencesis relatedto its correspondingDNL. For
example,for an ideal ADC with a full scalerampinput andrandomsampling,an equal
numberof outputcodesis expected.In practice,sincegeneratingan ideal linear rampis
difficult, asinewavesignalsourceis exploited.In thiscase,for anidealADC, thenumber
of outputcodesis proportionalto the probability of the sampleoccurrencein the related
input range (bin).
0 20 40 60 80 100 120 140 160 180 2000
5
10
15
20
25
30
35
40
45
50ADC+S/H+AGC performance with maximum decorrelation
Analog Input Frequency MHz
SN
DR
dB
100 Mhz Sampling Clock250 Mhz Sampling Clock400 Mhz Sampling Clock
Figure 5.9: Measured SNDR vs. analog input frequency for different sampling clocks at100 MHz, 250 MHz and 400 MHz.
Chapter 5:Experimental Results 111
The DNL corresponding to theth bin in an LSB unit can be defined as [63]
, (5.4)
where is the numberof countsin the th bin, is the total numberof output
samplesand is theidealbin width or theidealprobabilityof sampleoccurrencein the
th amplitude range.
The probability density function for a function of the form is
(5.5)
Thus, the probability of input samples occurring in the range of is
(5.6)
Fig. 5.10shows theidealprobabilitydensityfunctionfrom (5.6)andthemeasuredrelative
codedensityfor eachoutputcodeamong8000samplesfor thecombinationof PAE/ADC,
runningat 250-MHzclock frequency with a 124-MHzinput tone.Theoffsetof theoutput
codeswas removed by adjustmentof the differential referencevoltages.It should be
mentionedthat124MHz input tonegeneratesa1-MHz low frequency beatenvelop.Thus,
largenumberof samplescover the full amplituderange.In this way, theworst casehigh
frequency input andlarge swing transitionsareincludedin the DNL test.The measured
DNL or eachoutputcodeaccordingto (5.4) is depictedin Fig. 5.11.TheworstcaseDNL
is less than a 0.5 LSB.
Integral nonlinearity(INL) is themaximumdeviation of theinput/outputcharacteristic
from a straightline. INL canbe obtaineddirectly from DNL accumulationaccordingto
the following expression [4]
. (5.7)
i
DN Li
C i N total⁄Pi
------------------------ 1–=
C i i N total
Pi
i
p V( ) A ωt( )sin
p V( ) 1
π A2
V2
–---------------------------=
V i V i 1+,( )
p V i V i 1+,( ) 1
π---
V i 1+
A------------
asinV i
A-----
asin–=
IN L j DN Lk
k 0=
j 1–
∑=
112
Fig. 5.12 exhibits the integral nonlinearity (INL) performance of the combined PAE/ADC.
It should be mentioned that the nonlinearity of the PAE block was included in this
measurement as well. Therefore, the INL and DNL less than 0.5 LSB shows a satisfactory
result and good layout matching among ADC rows.
0 10 20 30 40 50 600
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
Output code
Rel
ativ
e C
ode
Den
sity
Figure 5.10: Experimental and theoretical relative output code density for 250-MHzclock frequency and 124-MHz input tone (1-MHz envelope beat).
Ideal sine wave
Measured ADC
relative code density
probability densityx
Chapter 5: Experimental Results 113
0 10 20 30 40 50 60−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
Output codes
DN
L (L
SB
)
Figure 5.11: Differential nonlinearity (DNL) obtained from code density measurement.
0 10 20 30 40 50 60−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
Output codes
INL
(LS
B)
Figure 5.12: Integral nonlinearity (INL) obtained from code density measurement.
114
5.5 Experiment in a 400-Mb/s 240-m Coaxial Cable System
5.5.1 Test Set-up
In this experiment the prototype chip was tested in the data transmission system shown
in Fig. 5.13. Two streams of binary data were generated by a pattern/data generator. By
setting the amplitude of one channel to one half of that of the other, and combining them
Data/PatternGenerator
DFG2030 CH1
CH2
Zero DegreeCombiner Converter
50 Ω / 75 Ω
Converter75 Ω / 50 Ω 180 Degree
Splitter
Bias T
Bias T
Test Board
TLA714 LogicAnalyzer
Computer
Off-chip DSP
Power Supply
LPFilter
Digital Equalizer &Symbol Detector
PAE / ADCPrototype Chip
x1
x1/2
Bias
External Clock
Clock
(Adjusted Delay)
4-level PAM
6-bit ADCOutput codes
Figure 5.13: Test set-up for 4-level PAM data transmission over 240-m Belden Coaxialcable.
(Optional)
PAE Factor (α) selection
6
75-Ω 240-m Belden Coaxial Cable
Chapter 5:Experimental Results 115
throughazero-degreepowercombiner, a4-level PAM datawith a reasonableeye opening
wasproduced.The eye diagramof the combineroutput is shown in Fig. 5.14.This eye
openingsufficesfor this experiment,althoughdueto the jitter andfrequency responseof
thedatageneratorandthecombiner, it is relatively degraded.Generally, usingline drivers
[64] anda high-speed4-level PAM generator[65] could improve thequality of thechan-
nel input.
A 75-Ω 240-mBeldencoaxialcablewasusedasthe transmissionchannel.The losses
of thischannelat frequenciesof 50MHz, 100MHz and150MHz are-15dB, -21dBand-
25 dB correspondingly. At bothchannelendsanimpedanceconverter, to convert from 50
Ω to 75 Ω andback,wasemployed for impedancematching.Fig. 5.13 shows a simple
resistive impedanceconverterdesignedfor this purpose.It shouldbementionedthatcom-
mercial types of this converter are available as well.
As shown in Fig. 5.13,a lowpassfilter with a bandwidthof about0.75timesthebaud
raterejectsout-of-bandnoiseafterthechannel.In theend,a180-degreepowersplitterand
two bias-Tsprovide differential inputswith properbias(450 mV) to the chip input. The
prototypechip samplesthechanneloutputandafterpartialequalizationand/ordecorrela-
tion, they arefed to the ADC. The chip outputcodeswerecapturedby a logic analyzer.
TheTLA714 logic analyzeris ableto useanexternalclockup to 200MHz. However, due
to its moderateexternalclock precision,the useof its internalclock waspreferred.The
TLA714 internalclock samplingmaximumis 500MHz plusanextra optionof 2 GS/sfor
a shortperiodof time (i.e. 1 µs). The latterwasemployed for off-chip clock recovery of
thesystem.Theclocksourceof theoriginalpatterngeneratorwasusedastheclocksource
of the testchip. The phasedelayof the transmitteddatarelative to the clock sourcewas
manually adjustedfor best clock matching. This was performedby transmitting an
impulse patternand the best clock phasematchingthat which producedthe strongest
channelimpulseresponsepeak.Also, a specificdatapatternwasplacedat thebeginning
of thebit streams,sothatthebit locationscouldberecognized.Thecodewords,captured
by the logic analyzer, weretransferredto thecomputerin orderto performtherestof the
116
signal processing. This consisted of an adaptive linear equalization and symbol detection
as shown in Fig. 5.16.
Figure 5.14: Four-level eye diagram produced at the input of the channel (Fs=200 MHz).
Figure 5.15: A 50Ω / 75Ω resistive impedance converter.
43.3Ω
86.6Ω75Ω 50Ω
50Ω75Ω
Chapter 5:Experimental Results 117
5.5.1.1 Measurement Results
Fig. 5.17depictsthemeasurementresultsfor thesystemin Fig. 5.13at 200-MHzbaud
ratein two casesof PAE, on andoff. All thesignalamplitudeswerenormalizedsuchthat
they hada varianceof , the varianceof an NRZ 4-level PAM with a maxi-
mum amplitudeof one.Fig. 5.17 (i) shows the channeloutputwaveform. Fig. 5.17 (ii)
shows the 64-level reconstructedwaveform correspondingto 6-bit codewordscaptured
from thechip output.WhenPAE is off, thechip is equivalentto anADC with a front-end
S/H andamplifier. Therefore,asseenin Fig. 5.17(i) (b), thechip outputis thequantized
versionof thechanneloutput.WhenPAE is on, thechipoutputis thequantizedversionof
thepartiallyequalizedchanneloutput.Compatiblewith thesimulationresultspresentedin
Chapter3, it is seenthattheADC outputhasamoreuniformdistributionanda lowercrest
factor. Thepart(iii) of thefigureshows therestoreddataaftertheoff-chip adaptive linear
equalizer. This equalizerin case(a) whenPAE is on, consistsof a 7-tap6-bit coefficient
feedforwardequalizer(FFE). In case(b), theequalizerorderwaschosenso that it would
Linear Equalizer
FFE
Decision
Feedback
Equalizer
Symbol Detector(Slicer)
Baseline Wander
Correction Filter G(z)
Output codes from
front-end ADC
Error
Error
Error
Figure 5.16: Off-chip signal processing block diagram for rest of equalization andfinal symbol detection.
σx 5 3⁄=
118
not to limit thequalityof theeyeopening.As seenin Fig. 5.17(b)(iii),whenPAE is active,
the transmitteddata can be restoredwith a significantly better error performance(i.e.
versus ). This improvementis equivalentto theadvantageof
usingan8-bit ADC withoutPAE. It shouldbementionedthat,althoughPAE andtheADC
weretestedup to 400 MS/s,whenplacingthe PAE/ADC in the testsystemof Fig. 5.13,
the maximum sampling rate was 200 MS/s, due to clock recovery test limitations.
RMSE 0.08≈ RMSE 0.18≈
0 500 1000 1500
−2
0
2
0 500 1000 1500
−2
0
2
0 500 1000 1500
−1
0
1
0 500 1000 1500
−2
0
2
0 500 1000 1500
−2
0
2
0 500 1000 1500
−1
0
1
Figure 5.17: Measured signals in the system with 4-level NRZ PAM transmitted at200-MHz baud-rate over a 240-m coaxial cable. (a) PAE is on. (B.) PAE is off. (i)channel output. (ii) ADC output. (iii) Restored data from ADC output after digitalequalizer. (a) (iii) Eye is opened using 7-tap 6-bit-coefficient FFE (RRMSE=0.08).(a)(iii) Best possible eye opening (RRMSE≅0.18). Here, the order of the digital FFEwas chosen such that not to limit the performance.
(a) PAE is on
(a) (i) Channel Output (b) (i) Channel Output
((b) (ii) 6-bit ADC Output, PAE Off(a) (ii) 6-bit ADC Output, PAE On
(a) (iii) Final Restored data, RMSE=0.08, PAE On (b) (iii) Final Restored data,RMSE=0.18 PAE Off
(b) PAE is off
Time normalized to Symbol period (Ts= 5 ns) Time normalized to Symbol period (Ts= 5 ns)
Chapter 5:Experimental Results 119
5.5.2 Special Considerations
Baseline wander effect: Since the transmittedsignal is ac-coupledby several blocks,
suchassplitterandbias-Ts,during thetransmissionpath,thedc componentof thesignal
wasdiscarded.This causeda low frequency drift on thesignalamplitudeknown asbase-
line wandereffect.Variousanaloganddigital techniquescanbeemployedto remove this
low frequency drift [5][66]. In thecurrentexperiment,thiseffectwasremovedby anextra
simpledigital feedbackfilter asshown in Fig. 5.16.This filter is a lowpassfilter of the
form that extractsthe dc drift of the error signalandsubtractsit
from the input. Note that this filter is differentfrom anerror-feedback-equalizerfilter [7]
which cancompensatefor high frequency loss.The outputof the baselineremoval filter
couldbesubtractedfrom theFFE outputaswell. This would give a slightly betterresult
for asimple . However, in thiscase,extracomplexity for theadaptationalgorithmof
the digital FFE equalizeris neededbecausethe adaptationstateshave to be modifiedto
includethecascadingeffect of thebaselinefilter on thesignalpath.Theeffect of baseline
wanderremoval is shown in Fig. 5.18.This figure shows the restoreddatain the experi-
mentalsystemof Fig. 5.13 with 100 MHz baud-ratewith and without baselinewander
removal.
G z( ) K z1–
= 1 z1––( )⁄
G z( )
Figure 5.18: 100MHz 240m system output. (a) baseline wander exists.(b) baseline wander removed.
0 500 1000 1500 2000−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol period TS (10 ns)
Am
plit
ud
e
0 500 1000 1500 2000−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol period TS (10 ns)
Am
plit
ud
e
120
Decision feedback equalizer: As mentionedin Chapter3, usinga DFE /FFEfor thedigi-
tal equalizerreducesquantizationerrorenhancementby theFFEaswell. Therefore,when
PAE is off, wecanobtainabettereyeopeningcomparedto anFFE-onlysystem.However,
anFFEis requiredbecauseof theprecursorISI andthelimited orderof thefeedbackfilter
dueto errorpropagationanddigital clock recovery difficulties.Experimentalresultsshow
thatusingPAE in anFFE/DFEsystemis alsobeneficialdueto crestfactorreductionat the
ADC input andreductionof the quantizationenhancementby the FFE part.This advan-
tage is more obvious at a lower number of ADC bits.
To evaluatethePAE/ADC systemwith a lower numberof bits, theleastsignificantbits
of the ADC output can be discarded.In this way, 5-bit and 4-bit code-words were
obtained.Figures5.19,5.20and5.21show themeasurementresultsfor the restoreddata
andtheir RRMSEfor differentnumberof bits for FFE-onlyandFFE/DFEsystems.The
DFE andFFE filters are5-tapand7-tapFIR filters. As seenin Fig. 5.19,usingPAE is
more advantageousin the FFE-only system.However, considerableimprovement is
achievedin theFFE/DFEsystemaswell. For example,thePAE/4-bit ADC front-endper-
formanceis equivalentto a6-bit-ADC-onlysystemin aFFE/DFEreceiverandalmosta7-
bit ADC-only systemin an FFE-onlydigital receiver. Thus,regardingthe resultsin Fig.
5.19,addingthe PAE reducesthe ADC resolutionrequirementto 5-6 bits insteadof 7-9
bits.
3 4 5 6 7 80
0.1
0.2
0.3
0.4
0.5
number of ADC bits
Rel
ativ
e R
MS
E
3 4 5 6 7 80
0.1
0.2
0.3
0.4
0.5
number of ADC bits
Rel
ativ
e R
MS
E
FFE/DFEFFE only
Figure 5.19: Restored data relative root mean square error (RRMSE) of therestored data in the 400-Mb/s 240-m coaxial cable system with an off-chip digitalFFE or an FFE/ DFE for different number of ADC bits and cases of PAE on and off.
PAE on
PAE off
PAE on
PAE off
Chapter 5: Experimental Results 121
0 200 400 600 800 1000 1200 1400 1600 1800 2000−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol period TS (5 ns)
Am
plit
ud
e
0 200 400 600 800 1000 1200 1400 1600 1800 2000−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol period TS (5 ns)
Am
plit
ud
e
0 200 400 600 800 1000 1200 1400 1600 1800 2000−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol period TS (5 ns)
Am
plit
ud
e
0 200 400 600 800 1000 1200 1400 1600 1800 2000−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol period TS (5 ns)
Am
plit
ud
e
0 200 400 600 800 1000 1200 1400 1600 1800 2000−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol period TS (5 ns)
Am
plit
ud
e
Figure 5.20: Restored data points for a 400-Mb/s 240-m coaxial cable system with off-chipdigital FFE/DFE for different number of ADC bits and the cases of PAE on and off.
PAE and 4-bit ADC with off-chip FFE/DFE 4-bit ADC front-end with off-chip FFE/DFE
PAE is offPAE is on
0 200 400 600 800 1000 1200 1400 1600 1800 2000−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol period TS (5 ns)
Am
plit
ud
e
PAE and 5-bit ADC with off-chip FFE/DFE 5-bit ADC front-end with off-chip FFE/DFE
PAE and 6-bit ADC with off-chip FFE/DFE 6-bit ADC front-end with off-chip FFE/DFE
122
0 200 400 600 800 1000 1200 1400 1600 1800 2000−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol period TS (5 ns)
Am
plit
ud
e
0 200 400 600 800 1000 1200 1400 1600 1800 2000−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol period TS (5 ns)
Am
plit
ud
e
0 200 400 600 800 1000 1200 1400 1600 1800 2000−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol period TS (5 ns)
Am
plit
ud
e
Figure 5.21: Restored data points for a 400-Mb/s 240-m coaxial cable system with off-chipdigital FFE for different number of ADC bits and cases of PAE on and off.
0 200 400 600 800 1000 1200 1400 1600 1800 2000−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol period TS (5 ns)
Am
plit
ud
e
0 200 400 600 800 1000 1200 1400 1600 1800 2000−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol period TS (5 ns)
Am
plit
ud
e
0 200 400 600 800 1000 1200 1400 1600 1800 2000−1.5
−1
−0.5
0
0.5
1
1.5
Time normalized to symbol period TS (5 ns)
Am
plit
ud
e
PAE and 4-bit ADC with off-chip FFE 4-bit ADC front-end with off-chip FFE
PAE and 5-bit ADC with off-chip FFE 5-bit ADC front-end with off-chip FFE
PAE and 6-bit ADC with off-chip FFE 6-bit ADC front-end with off-chip FFE
PAE is offPAE is on
Chapter 5:Experimental Results 123
5.6 Channel Emulator Using Arbitrary Waveform Generator
To evaluatethe performanceof the chip for different channelmodelsand losses,an
arbitrarywaveform generator(AWG) wasusedto emulatethe channeloutputwaveform
directly. Thetestbenchfor thismeasurementis shown in Fig. 5.22.Theadvantagesof this
experimentincludetheability to testdifferentchannelmodels,that thetransmitter’s non-
idealitiesarepreventedandthechannellosscanbenormalizedto a lower frequency. This
latterone,resultsin lessclock recovery difficultiesandability to performbetterfunction-
ality analysis for a larger channel loss.
180 DegreeSplitter
Bias T
Bias T
Test Board
TLA714 LogicAnalyzer
Computer
Off-chip DSP
Power Supply
Digital Equalizer &Symbol Detector
PAE / ADCPrototype Chip
Bias
External Clock
6-bit ADCOutput codes
Figure 5.22: Test set-up for 4-level PAM data transmission over 240-m Belden coaxialcable.
(Optional)
PAE Factor (α) selection
6
Arbitrary WaveformGenerator (AWG)
WAVETEK
10-M
Hz R
efe
rence C
lock
R OHDE & SCHWARSignal generator
ExtClk
Data ClockGeneratorDFG2030
ClkOut
PhaseAdjustment
Clock
124
Sincethe previous cabletest wasboundedto 240-mcableandup to 400 Mb/s, the
maximumtestedchannellosswas-21dB.In 622-Mb/s300-mCoaxialcablesystem,32dB
lossat Fs/2exists,whereFsis thebaudratefrequency. To investigatethefunctionalityof
the PAE/ADC in the above system,the channeloutputwasemulatedby the AWG with
100-MHzsamplingratewhile thebaud-ratewasnormalizedto 20MHz. The10-MHzref-
erenceclock of theAWG andtheclock generatorweresharedfor clock matching.Since
the chip input is constantduring 50 ns periods, the off-chip clock recovery is more
relaxed.An specificdatapatternwasplacedat thebeginningof thebit streams,sothatwe
could recognize the bit locations and measure the bits correctness.
Fig. 5.23 exhibits the measureddatawaveformsat the chip input, chip output (6-bit
codes)andaftertheoff-chip linearequalizerin bothcasesof PAE onandoff. As seen,due
to larger channel loss the effect of PAE is significant; i.e. RRMSE=0.07 versus
0 200 400 600 800 1000 1200 1400
−2
−1
0
1
2
(i) Channel Output
0 200 400 600 800 1000 1200 1400
−2
−1
0
1
2
(ii) (ii) Analog front−end chip ( S/H + VGA + 6 bit ADC ) output code
0 200 400 600 800 1000 1200 1400
−1
0
1
(iii) Restored data after digital FFE, RMSE= 0.27
0 200 400 600 800 1000 1200 1400
−2
−1
0
1
2
(i) Channel Output
0 200 400 600 800 1000 1200 1400
−2
−1
0
1
2
(ii) (ii) Analog front−end chip ( PAE + 6 bit ADC ) output code
0 200 400 600 800 1000 1200 1400
−1
0
1
(iii) Restored data after digital FFE, RMSE= 0.07
Figure 5.23: Measured signals in the system of Fig. 5.22, where the channel output of622-Mb/s 300-m coaxial cable is emulated by an AWG.(a) PAE is on. (B.) PAE is off. (i)channel output. (ii) ADC output. (iii) Restored data from ADC output after digitalequalizer. (a) (iii) eye is opened using 7-tap 7-bit-coefficient FFE (RRMSE=0.07). (B.) (iii)best possible eye opening (RRMSE≅0.27). Here, the order of the digital FFE was chosensuch that not to limit the performance.
(a) PAE is on (a) PAE is off
Chapter 5:Experimental Results 125
RRMSE=0.27.The RMSE=0.07is closeto the performanceof a 9-bit ADC front-end
which indicates an improvement of about 3 bits.
5.7 Summary
Thefabricatedchip consistingof a partialanalogequalizeranda 6-bit ADC, waschar-
acterizedandits performancein thereceiver front-endof a 400-Mb/s240-mcoaxialcable
channelsystemwasmeasured.Table5.1shows a summaryof themeasuredIC character-
istics alongwith someotherrecentstate-of-the-artADCs. To demonstratethe impactof
theADC effective resolution,usingsimulationson a 622-Mb/ssystemwith a 20-tap-FFE
receiverandasymbol-errorratebelow 10-7, themaximumachievablecoaxialcablelength
for the correspondingADC effective resolutionswere obtainedand are shown in this
table.While thechangesin technologiesis to benotedin Table5.1,it is seenthatthecom-
binationof PAE and6-bit ADC is anefficient approach.This is trueaccordingto thearea
andpowerconsumption,whencomparedto asingle8-bit ADC for usein wiredcommuni-
cation applications.
Table 5.1: Measured IC characteristics and comparisons
Specification, Unit This work [67] [57] [53]
CMOS Technology, (µm) 0.18 0.35 0.35 0.6
Sampling Frequency, (MS/s) 400 200 400 150
Power Supply, (V) 1.8 3 3 3.3
ADC resolution, (bits) 6 8 6 8
Equivalent bit resolutionfor long cable applications, (bits)
> 8 6.8 5.5 6.5
Maximum coaxial cable length for 622 Mb/sapplication for SER <10-7according to the given effectiveresolution, assuming ADC runs at fs = 311MHz, (m)
300 225 140 200
Total Active Area, (mm2) 0.83 3.3 1.2 1.2
PAE / ADC Area (mm2 /mm2) 0.74/0.09 -- -- --
Power (PAE + ADC), (mW) 84 + 22 655 190 395
SFDR / SNDR @250 MHz clk, 45 MHz input, (dB) 45 / 34 59 / 42@Fs
-- 50 / 40@Fs
SFDR / SNDR @400 MHz clk, 124 MHz input, (dB) 37 / 30.2 -- 37 / 31 --
ADC INL /DNL, (LSB) < 0.5 0.8 < 0.5 1.2/0.6
Input Swing, (V) 0.6 1.3 1 1.6
126
127
CHAPTER
6.1 Summary and Conclusions
In this thesis,the ADCs bit requirementsfor wired communicationapplicationswere
investigatedand an efficient partial analogequalization(PAE) approachto improve the
performanceof the front-endADC waspresented.Themotivation for this work wasthat
high-speedhigh-resolutionanalog-to-digitalconverters(ADC) is oneof the major chal-
lengesin thedesignof digital communicationsystems.This is dueto thehigh-speedhigh-
resolutionADCs power andareaconsumptionandthefeasibility of their implementation
in low-voltagestandardCMOStechnology. Thecontributionsof this thesisincludedtwo
majorcomponents.First, throughananalyticalstudythebenefitof partialequalizationin
terms of ADC bit requirementswas elaborated.Second,an implementationof a high
speedPAE / ADC combinedonasingle1.8-V CMOSchipwasdemonstratedandtheben-
efit of 2-3 bits improvement was verified, experimentally.
By studyingtheADC input characteristicsandtheeffect of thequantizationnoiseon a
digital communicationsystem,a formula for the requiredresolutionfor a given system
errorratewasproposed.Differentapproachesto reducetheADC resolutionrequirements
wereinvestigated.A 2-tapPAE wasselectedasanefficient choicefor analogpreprocess-
ing in orderto reducetheADC bit requirements.It wasshown thatthesimilarity between
the2-tapPAE andafirst-orderfeedforwarddecorrelatorcouldbeutilized to determinethe
singlezeroof thePAE. ReplacingtheADC with ananalogdecorrelatorandits inverse,as
a digital postfilter, beforeandafter theADC in a digital communicationsystem,enabled
theuseof a lower resolutionADC with thesameerrorperformance.Theanalogdecorrela-
Summary and
Future Research6
128
tor, or 2-tapPAE, reducesthe ADC input crestfactorand the PAE inverseconverts the
quantizationnoiseto a lowpassshape.Thus, the quantizationnoiseis not enhancedby
digital equalization.The combinationof thesetwo effects reducesthe ADC resolution
requirementconsiderably. Theefficiency of theproposedapproachdependsontheamount
of channellossor inter-symbolinterference(ISI). Thegreaterthe ISI, themoreadvanta-
geous this approach would be.
A combinationof a2-tapPAE anda6-bit 400-MHzADC wasimplementedin standard
digital 0.18-µm CMOS technology. The PAE consistedof two setsof triple-interleaved
sample-and-holds(S/H), two variablegain transconductors,a current-to-voltageconverter
and an ADC input buffer. The circuit designcontributions and the relevant simulation
resultswere reviewed within the thesis.A flash architecturewas utilized for the high-
speed6-bit ADC. Different autozeroingor offset cancellationsand test modesenabled
testingandcharacterizingtheprototypechip experimentally. Apart from themainblocks’
design,theperipheraldesigntechniquescontributionsincludeda non-overlaptriple clock
generator, using master clock for interleaved S/H, adaptive lead compensationsin
transconductors,efficient interdigitatedcapacitorslayout, careful floor planning of the
ADC rows and symmetric clock distribution.
The functionality andperformanceof the chip wastestedandpresentedin Chapter6.
An SNDRof 34dB wasachievedfor a250-MHzsamplingfrequency. In addition,thechip
wasplacedin anexperimental400-Mb/s240-mcoaxialcablecommunicationsystem.In
thisway, theadvantageof having thePAE wasdemonstrated.UsingtheproposedPAE, the
ADC performancewasshown to be improved by morethan2 bits at a costof only 12%
extra area and 17% extra power.
6.2 Suggestions for Future Work
Thereareseveral directionsto focuson for continuationof this work. Extendingthe
applicationof this researchto complex modulationreceiversandfull-duplex transceivers
aretwo areasthatcanbestudied.Moreover, for thecurrentapplication,advancedcircuit
designtechniquescanbeappliedto extendthespeedandefficiency of thedesignin both
PAE and the ADC blocks.
Chapter 6:Summary and Future Research 129
AppendixC shows the preliminarysimulationresultsfor usingpartial equalizationto
reducetheresolutionandsamplingspeedrequirementsof thefront-endADC in a system
with carrierlessamplitudeanda phasemodulationscheme(CAP). CAP is a modulation
scheme[23][68] usedin digital communicationsystemsand can be consideredto be a
bandpassPAM (PulseAmplitudeModulation)[7], in which thecarrierfrequency is near
baseband.Ontheotherhand,it canalsobeviewedasavariationof QuadratureAmplitude
Modulation (QAM) without explicit modulation/demodulationblocks. CAP is usedin
wired applicationsbecauseof its simplicity, bandwidthefficiency andzerodc component.
ConventionalCAP receiversconsistof a relatively high-speedhigh-resolutionfront-end
ADC along with two parallel fractionally-spaced,tapped-delay-linefilters for channel
equalizationandI/Q separation.By usinga low orderpartialanalogequalizer/demodula-
tor theADC requirementcanbereducedto two ADC with onethird of thespeedand1-2
bit lessresolutionfor a 16-CAP1.2 Gb/sover 200-mcoaxialcable.The implementation
issuesof suchanew mixedtopologyandtherelatedcircuit designtradeoffs couldbecon-
sidered as a future research topic.
As mentionedin Chapter3, a2-tapPAE canbeconsideredto befeedforwarddecorrela-
tor. Anothervariationis a feedbackdecorrelator. Underthismethod,eachADC inputsam-
ple is predictedfrom the previous quantizedsampleratherthana non-quantizedanalog
sample(seeFig. 3.20).Theadvantagewould bea further reductionin quantizationnoise
(or reducingtheADC resolutionrequirement).Thedifficulty in this methodis speedlimi-
tationdueto thedelayof thefeedbackloop thatconsistsof theADC, an multiplier and
subtractor. Investigating different circuit techniquesto copewith this loop delay is an
interesting research topic to work on.
It was observed that the signal amplitudedistribution after the PAE had somelocal
peaks.Using a non-uniform quantizationtechnique,the quantizationintervals can be
adjustedsuchthat at thosepeakslessquantizationerror is added.In this way, a further
reductionof averagequantizationnoisecanbe achieved, which is equivalent to a lower
numberof bits requirement.However, a specificnon-uniformquantizationfor an ADC
may not be desirable in some applications.
To improve the speedand performanceof the current design,several other circuit
designtechniquescould be investigated.Using multiple gain stagesin a PAE is a candi-
α
130
date for achieving a higher bandwidth. Using coding schemes, such as gray coding in the
ROM part, is recommended for further ADC error rate reduction. For ADC speed
enhancement, a continuous time comparator with digital calibration could be used. This is
a good approach for low resolution, high speed applications such as back-plane chip to
chip applications [69].
131
APPENDIX
A.1 Transconductor feedback loop analysis and leadcompensation
The linearity of the transconductor blocks in the partial analog equalizer is improved by
placing a feedback loop around the input transistors. To verify the stability performance of
the transconductors, shown in Fig. A.1, the feedback loop is broken at the gate of transis-
tors M3 and M4, and thus, the loop gain transfer function can be evaluated. Note
that the parasitic capacitors and include the loading effect of the gates of M3
and M4 in addition to the total parasitic capacitance at M1 and M2 drains or node 2.
VcnM1
M3
M5R1
R3
R5
R7
R2
M20
M21
M22
R4
R6
Figure A.1: Opening the feedback-loop to characterize the open loop circuit andstability analysis.
Vctrl1
2Rs
vo+
vi+
Lead
compensation
circuit
VcnM2
M4
M6
Vctrl1
vo-
vi-
I1
I2
I1
I2CP2'CP2
Vcn
M7
M9 Vcn
M8
M10
1
2
Y c
vo vi⁄
CP2 CP2'
Transconductor
Circuit AnalysisA
132
To calculatetheloopgain transferfunction , thehalf circuit shown in Fig. A.2 (a)
andits smallsignalequivalentin Fig. A.2 (b) areutilized.As afirst step,thecascodetran-
sistorsM3 and M5 are replacedby a Norton equivalent circuit consistingof a current
sourcewith the value of and an output resistance , as shown in Fig. A.3. The
capacitor representsthetotalparasiticcapacitanceatnode3. To find in Fig. A.3,
node 1 is made short circuit to ground and its current is calculated as
, (A.1)
where is the voltage at node 3 and can be calculated by KCL at node 3 as
. (A.2)
By replacing from (A.2) into (A.1) and considering , we can write:
, (A.3)
where
. (A.4)
It can also be shown that the impedance seen from node 3 in Fig. A.3 is equal to [70]:
, (A.5)
vo vi⁄
Kvi ro5
CP3 Kvi
I eq v3 gm5 gds5+( )–=
v3
v3
gm3vi–
gds3 gds5 gm5 CP3s+ + +-------------------------------------------------------------=
v3 gds3 gds5, gm5«
I eq Kvi
gm3 gm5 gds5+( )gds3 gds5 gm5+ +( )
----------------------------------------------- 1
1 s p3⁄–---------------------
vi gm3
1
1 s p3⁄–---------------------
vi≅= =
p3
gds3 gds5 gm5+ +
CP3
------------------------------------------–g– m5
CP3
------------≅=
ro5 rds3 1 gm5rds5+( ) r+ds5
( )1 s z4⁄–
1 s p4⁄–---------------------
gm5rds3
rds5
1 s z4⁄–
1 s p4⁄–---------------------
≅=
Appendix A: Transconductor Circuit Analysis 133
Figure A.2: (a) The open loop half circuit of the linearized transconductor. (b) Thesmall signal equivalent.
VcnM1
M3
M5
gm1v1
1/gm1 rds1 Kvi ro5 rI1
rI2 CP2Rc
Cc
CP1 Rs
vo
Rs
CP2
CP11
23
CP3
1
2
Rc
Cc
vi
Y2
(a)
(b)
I1
I2
Figure A.3: Replacement of the cascode transistors by the Norton equivalent circuit.
CP3
rds5
1/gm3
rds3vi
Vcn
M3
M5
vi
1
3
CP3
3
gm3vi
1/gm5
gm5v3
Ieq= Kvi ro5
1ro5
ro5
ro5
134
where
, (A.6)
and
. (A.7)
As a secondstepin Fig. A.2 (b), considering , thevoltages
can be approximated as
. (A.8)
To find therelationshipbetween and we canwrit theKCL at node2 canbewritten
as
. (A.9)
A rearrangement of (A.9) gives:
(A.10)
where is the compensationnetwork admittanceaddedto node2. A Combinationof
(A.3), (A.8) and (A.10) results in
. (A.11)
p41–
rds3CP3
-------------------=
z4
rds3 1 gm5rds5+( ) r+ds5
rds5rds3CP3
----------------------------------------------------------–=g– m5
CP3
------------≅
rds1 ro5 rI 1, , 1 gm1⁄« v1
v1
Kvi
gm1 CP1s 1 Rs⁄+ +-----------------------------------------------=
vo v1
vo g I 2 CP2s Y c+ +( ) vo v1–( )gds1 gm1v1–+ 0=
vo
v1
-----gm1 gds1+
g I 2 CP2s Y c gds1+ + +--------------------------------------------------------
gm1
CP2s Y c gds1+ +-----------------------------------------≅=
Y c
vo
gm1gm3vi
gm1 CP1s 1 Rs⁄+ +( ) CP2s Y c gds1+ +( ) 1 CP3 gm5⁄( )s+( )------------------------------------------------------------------------------------------------------------------------------------------------=
Appendix A:Transconductor Circuit Analysis 135
A.1.1 No Compensation
In caseswherethereis no compensationcircuit, i.e. , the open-looptransfer
function becomes:
, (A.12)
where
, (A.13)
, (A.14)
. (A.15)
Notethat is thedominantpoleof the loop transferfunctionbecause .
To find the unity gain frequency , by assuming we can write:
, (A.16)
and thus:
. (A.17)
Therefore,in the design,it is importantto ensurethat the otherpolesare far enough
from in (A.17) in order to have a properphasemargin. Since is muchsmaller
than in Fig. A.1, couldrepresentthesecondpole.Accordingto (A.14), for larger
, falls at a lower frequency. This could affect the phasemargin when a lower
transconductance gain is chosen (by increasing ).
Y c 0=
vo
vi
----- gm3rds1
gm1
gm1 1 Rs⁄+----------------------------
1
1 s p1⁄–---------------------
1
1 s p2⁄–---------------------
1
1 s p3⁄–---------------------
⋅=
p1
gds1
CP2
----------– 1–rds1C
P2
-------------------= =
p2
gm1 1 Rs⁄+
CP2
----------------------------–=
p3
gm5
CP3
---------–=
p1 gds1 gm1 gm5,«
ωu p1 ωu p2 p3,« «
vo
vi
----- gm3
gm1
gm1 1 Rs⁄+----------------------------
1
CP2ωu
---------------- 1= =
ωu g– m3
gm1
gm1 1 Rs⁄+----------------------------
1
CP2
---------=
ωu CP3
CP2 p2
Rs p2
Rs
136
A.1.2 Lead Compensation
In thisdesign,whenthegain is setto its lowestvalue(i.e is setto its largestvalue)a
leadcompensationcircuit, asshown in Fig. A.1 is activatedto improve thephasemargin
of theloop transferfunction.Consideringtheequivalentvalueof from thecompensa-
tion network, the second term in the denominator of (A.11) can be written as
(A.18)
If we write (A.18) in the form of
(A.19)
andassumingits polesarefar from eachother, (i.e. ), thenthepolesandzeros
can be estimated as
, (A.20)
, (A.21)
and
. (A.22)
Therefore, in (A.12) can be rewritten as
. (A.23)
Rs
Y c
1
Y 2
------1
CP2s Y c gds1+ +-----------------------------------------
1
CP2s1
Rc 1 Ccs( )⁄+---------------------------------
1
rds1
---------+ +--------------------------------------------------------------------= =
rds1 1 RcCcs+( )
RcCcrds1CP2( )s2
RcCc rds1CP2 rds1Cc+ +( )s 1+ +-------------------------------------------------------------------------------------------------------------------------------=
rds1 1 s z1⁄–( )1 s p1a⁄–( ) 1 s p1b⁄–( )
----------------------------------------------------------=
p1b p1a»
p1a
1
RcCc rds1CP2 rds1Cc+ +-------------------------------------------------------------–=
p1b
1
rds1CP2
-------------------1
rds1Cc
----------------1
RcCc
------------+ + –=
z11
RcCc
------------–=
vo
vi
-----
vo
vi
----- gm3rds1
gm1
gm1 1 Rs⁄+----------------------------
1 s z1⁄–
1 s p1a⁄–( ) 1 s p1b⁄–( ) 1 s p2⁄+( ) 1 s p3⁄–( )----------------------------------------------------------------------------------------------------------------=
Appendix A:Transconductor Circuit Analysis 137
By comparing and in (A.20) and(A.13), we canseethat thedominantpole is
shiftedto slightly lower frequencies.Meanwhile,althougha new non-dominantpole
is introducedat muchhigherfrequencies,the zero compensatesfor the phasemargin
reduction due to the non-dominant poles. From (A.23) and by assuming
, theopen-loopunity gain frequency canbeestimatedby
. (A.24)
Then, is found as
(A.25)
As expected, has moved to lower frequenciescomparedto in (A.17) before
compensation.This further improves the phasemargin at the cost of lower bandwidth.
However, notethatcompensationis neededwhenwechooselower transconductancegains
or larger . In thiscase,thebandwidthis alreadyincreasedbecauseof thelowergainand
larger (see(A.17)).Thus,reducingthebandwidthby compensationshouldbetolerable
as it might be still higher than when the gain is maximum and is minimum.
In theend,a testcircuit architecturesimilar to Fig. A.1 hasbeensimulatedto evaluate
theeffectof thecompensationnetwork. Fig. A.2 shows themagnitudeandphaseresponse
of the transconductorloop gain, with andwithout compensationcircuits.As we cansee,
while is reducedafter compensation,the addedzerocancelssomeof the phaselag
caused by the non-dominant poles.
p1a p1
p1b
z1
p1a ωu z1 p2 p3 p1b, , ,« «
vo
vi
----- gm3rds1
gm1
gm1 1 Rs⁄+----------------------------
1
ωu p1a⁄( )------------------------ 1= =
ωu
ωu gm3rds1
gm1
gm1 1 Rs⁄+----------------------------
1
RcCc rds1CP2 rds1Cc+ +-------------------------------------------------------------=
gm3rds1
RcCc rds1CP2 rds1Cc+ +-------------------------------------------------------------≅
ωu ωu
Rs
Rs
Rs
ωu
138
103
104
105
106
107
108
109
1010
−30
−20
−10
0
10
20
30
40
Frequency (Hz)
Mag
nitu
de (
dB)
Without compensationWith lead compensation
103
104
105
106
107
108
109
1010
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
Frequency (Hz)
phas
e (d
egre
e)
without compensationwith lead compensation
Figure A.4: Frequency response of the loop gain of the transconductor amplifiers withand without lead compensation. (a) Magnitude Response. (b) Phase response (Phasemargin improvement: 74 to 101 degree).
Appendix A:Transconductor Circuit Analysis 139
A.2 Transconductance Gain Expression and the Effect of theFeedback Loop
Fig. A.5(a) shows thehalf circuit andits small signalequivalentof the transconductor
amplifiershown in Fig. A.1. Hereanexpressionfor transconductancegain , consid-
eringtheeffect of thefeedbackloop aroundinput transistor, is derived.In thesmallsignal
equivalentshown in Fig. A.5(b), thecascodetransistorsM3 andM5 arereplacedby asim-
plified equivalent model, shown in Fig. A.3.
io vi⁄
Figure A.5: (a) The half circuit of the linearized transconductor. (b) The smallsignal equivalent.
gm1v1
1/gm1 rds1
rI2
2Rs
1
2
vi2 Vcn
M1
M3
M5
Rs
1
2
CP3
Vcn
M3
M5
I1
I2
I1-I2-io
io
vi2
gm3v2v2
v1
2
1/gm3
ro5 gm3rds5rds3≅
rI1
(a)
(b)
140
The KCL at node 1 gives:
, (A.26)
or
. (A.27)
Using the approximation and we can simplify (A.27) as
. (A.28)
Also, the KCL at node 2 gives:
(A.29)
or
. (A.30)
Using the approximation , (A.30) can be simplified as
. (A.31)
Now, by combining (A.28) and (A.31) and cancelling, we can write:
, (A.32)
v11
rI 1
-------1
ro5
-------1
Rs
-----+ + gm1 v1
vi
2----–
gds1 v1 v2–( ) gm3v2+ + + 0=
v11
rI 1
-------1
ro5
-------1
Rs
----- gm1 gds1+ + + + v2 gm3 gds1–( )+ gm1
vi
2----=
gds1 gm3«1
rI 1
-------1
ro5
------- gds1, , gm1«
v11
Rs
----- gm1+ v2 gm3( )+ gm1
vi
2----
=
gds1 v2 v1–( ) gm1 v1
vi
2----–
+ 0=
gds1v2 v1 gds1 gm1+( ) gm1 vi 2⁄( )–=
gds1 gm1«
gds1v2 v1gm1 gm1 vi 2⁄( )–=
v2
v11
Rs
----- gm1+ gm3
v1gm1 gm1 vi 2⁄( )–
gds1
---------------------------------------------- + gm1 vi 2⁄( )=
Appendix A:Transconductor Circuit Analysis 141
and it can be simplified as
, (A.33)
or
, (A.34)
where . To find we can write
, (A.35)
in which (seeFig. A.5). Therefore,the final transconductancevalue can be
written as
. (A.36)
As seenin (A.36), comparedto a conventional transconductor, the effect of is
reducedby a factorof where . Note that 2Rs is the total degeneration
resistancebetweenthe sourcenodesof the input transistorsand it determinesthe total
gain.
v1
vi 2⁄-----------
gm1
gm1gm3
gds1
------------------+
1
Rs
----- gm1
gm1gm3
gds1
------------------+ +
-----------------------------------------------=
v1
vi 2⁄-----------
1
11
Rsgm1 A 1+( )----------------------------------+
-------------------------------------------=
Agm3
gds1
----------=io
vi
----
io
vi
----v1
vi 2⁄-----------
1
2---
io
v1
-----××=
io
v1
-----1
Rs
-----=
io
vi
----1
2Rs
2
gm1 1 A+( )---------------------------+
-------------------------------------------=
gm1
1 A+ Agm3
gds1
----------=
142
143
APPENDIX
In this appendix,thealgorithmfor searchingtheoptimumfilter coefficientsby Gradi-
ent Search method in a communicationsystemwith a partial analogequalizer(PAE) is
presented. This communication system is shown in Fig. B.1.
For thecoefficientof filter in Fig. B.1,usingsteepestdescentgradientsearch,we
can write [26]:
, (B.1)
where is theupdatedvalueof for thenext time instantand is thegainconstant
that regulatesthe speedandthe stability of the adaptation.The parameter is the error
between the delayed input signal and the final recovered output signal as
. (B.2)
Therefore we can write:
. (B.3)
G z( )
gk 1+ gk µ ∂e2
∂gk
---------–=
gk 1+ gk µ
e
e n( ) xd n( ) x n( )ˆ–=
∂e2
∂gk
--------- 2e∂e
∂gk
--------- 2– e∂ x
∂gk
---------= =
Global Gradient
Search for PAE
Optimization
B
144
Thus, (B.1) can be rewritten as
. (B.4)
In Fig. B.1, we can write the filtering operations as
(B.5)
where is theconvolution operator. is the addedquantizationnoisecausedby the
ADC and can be written as
, (B.6)
where is a uniformly distributed white noise normalizedwithin the interval
. From (3.9) is approximated as
(B.7)
where
. (B.8)
gk 1+ gk 2µe∂ xk
∂gk
---------+=
xn x * c n+( ) * g * h[ ] n( ) q * h( ) n( )+=
* q n( )
Figure B.1: A communication system with a PAE and a DLE in the receiver.
Channel
R bit
σx
2 σx
2
+a
-3a-a
+3a
ck
Delay
x n( )
xd n( )
DLEPAE
q n( )n n( )
ChannelNoise
hkgk
QuantizerNoise
x n( )
y n( )
e n( )
q n( )y peak
2R
-------------qnorm n( )=
qnorm n( )
1 1,–[ ] y peak
y peak x peak c * g( )ii
∑=
c * g( )i ci k– gk⋅k∑=
Appendix B:Global Gradient Search for PAE Optimization 145
Defining the as the sign operator, Using the equation
(B.9)
( is a sign operator), and (B.8), we can write:
. (B.10)
Using the above expression, we can rewrite (B.7) as
(B.11)
Thecombinationof theabove expressionand(B.6) canbeusedto obtainthegradientof
the second term in (B.5) versus the PAE coefficients .
For thegradientof thefirst term in (B.5), we mustconsidertheeffect of cascadingof
theDLE with thePAE. Thegradientof cascadedfilters werereviewed in Chapter2. The
gradient of the first term in (B.5) versus can be written as
. (B.12)
Using (B.6) and (B.12) for the gradient of (B.5) versus to we can write:
(B.13)
where can be obtained from (B.11).
The gradient of the output versus is the delayed version of input as:
(B.14)
[ ]sgn
f u( ) 0≠∂ f u( )u
--------------- f u( )[ ] ∂f u( )∂u
--------------,⋅sgn=
[ ]sgn
∂c * g( )i
∂gk
-------------------- ci k– c * g( )i( )sgn⋅=
∂ y peak
∂gk
---------------- x peak ci k– c * g( )i( )sgn⋅i
∑=
gk
gk
gk∂∂
x * c n+( ) * g * h[ ] n( ) gk∂∂
x * c n+( ) * h[ ]k∑
n k–( )gk⋅=
x * c n+( ) * h[ ] n k–( )=
gk
gk∂∂
xn x * c n+( ) * h[ ] n k–( )∂ y peak
∂gk
----------------qnorm
2R
------------- * h
n( )
+=
∂ y peak
∂gk
----------------
hk H z( )
hk∂∂
xk x * c n+( ) * g[ ] q+[ ] n k–( )=
146
Fig. B.2 demonstratesthesimulationblock diagramfor implementingtheGlobalGra-
dientSearchalgorithmusing(B.11)and(B.14).Althoughthisalgorithmis relatively com-
plex to implementin hardware,it is usefulfor system-level designandverificationof the
filter coefficients obtained from other suboptimal but practically-efficient methods.
H(z)G(z)
hkgk y n( )
z-1
H(z)
H(z)
Delay
1
2R
------
gk n 1+( )g∆ k n( )g
kn( )
Channelck
x n( )
qnorm n( )
2µ
z-1
z-1
z-1
hk n( )
Figure B.2: The Global Gradient Search algorithm implementation for PAE andDLE coefficients optimization
from (B.11)∂ y peak
∂gk
-----------------from (B.7)y peak
x n( )
xd n( )
e n( )
Estimated ADC quantization noise
nn( )
147
APPENDIX
C.1 Introduction
Carrierlessamplitudeandphasemodulation(CAP) is amodulationscheme[23] in dig-
ital communicationsystemsandcanbe considereda form of bandpasspulseamplitude
modulation(PAM) [7], in whichthecarrierfrequency is nearbaseband.Ontheotherhand,
it canalsobeviewedasavariationof quadratureamplitudemodulation(QAM) with com-
binedin-phase(I) andquadrature(Q) componentsbut withoutexplicit modulation/demod-
ulation blocks. In contrast to uncodedPAM, CAP has zero dc power. This spectral
characteristicmakesit well suitedto ac-coupledchannels.It alsoallows thepossibilityof
leaving a frequency band,neardc, which canbeusedfor othersignals(suchasstandard
telephone signals).
Most CAP systemsaredesignedandimplementedin thedigital domainby applyinga
relatively high-rate high-resolutionanalog-to-digitalconverter (ADC); thereby, taking
advantageof digital signalprocessing.Throughoutthis thesistheadvantageof usingpar-
tial equalizationin a PAM systemwaselaborated.As we shallsee,usinga partialanalog
equalizer/demodulatorin CAP systemsallows theuseof less-costlyADC andlessdigital
filtering complexities for a desirederror performance.As mentionedpreviously, partial
analogequalization,comparedto full-analogequalization,hastheadvantageof a consid-
erablylower orderandfeasibleanalogadaptive filtering. At thesametime, theflexibility
andreliability of a digital receiver is maintainedat a lower costcomparedto conventional
fully digital receivers.
Reduction of ADC
Requirements in
CAP/QAM
Receivers
C
148
Themainapproachin thepresentedtopologyinvolvessplitting the I andQ equalizers
into two low-order fractionally-spacedanalogandbaud-ratedigital cascadedequalizers.
In addition,a low-ordercomplex decisionfeedbackequalizer(DFE) contributesto a fur-
therreductionin theremaininginter-symbol(ISI) andI-Q interferenceerrors.To show the
efficiency of this technique,simulation resultsfor a target applicationof 1.2Gb/sdata
transmissionover 200-mcoaxialcableusing16-CAPfor serialdigital videoapplications
[71] is presented.It is shown that two 6-bit 300-MHz ADC, with two low orderanalog
FIR equalizersandsomelow-orderdigital processing,give thesameerrorperformanceas
a system with an 8-bit 900-MHz ADC with two large order I-Q filters.
C.2 CAP/QAM Modulation
Fig. C.1(a) shows a simpleQAM systemwhere and arelowpassshapingfil-
terssuchasroot raisedcosinepulses[7][72]. In near-basebandwiredapplications rep-
resentsacarrierfrequency which is equalto or slightly greaterthanthebandwidthof ,
i.e. wherefs is thesymbolratefrequency. Notethat,thecarriersignalsin both
the transmitter and receiver must be in phase.
g t( ) f t( )
f c
g t( )
f c f s 2⁄≥
ωct( )cos
ωct( )sin ωct( )sin
ωct( )cos
f t( )
f t( )
g t( )
g t( )
Figure C.1: (a) QAM modulation scheme: transmitter and receiver. (b) CAPModulation scheme: transmitter and receiver.
+
Ak
Bk
Equalizer
SymbolDetector
+
Bk
g t( ) ωc
t( )cosAk
g t( ) ωc
t( )sin
f t( ) ωc
t( )cos
f t( ) ωc
t( )sin
(a)
(b)
&
Ak
Bk
Ak
Bk
Equalizer
SymbolDetector
&
Appendix C:Reduction of ADC Requirements in CAP/QAM Receivers 149
Fig. C.1 (b) shows analternative passbandmodulationscheme,calledcarrierlessAM/
PM or CAP. This schemeconsistsof only I andQ filters.Thesefilters, in contrastto low-
passfilters in QAM systems,arepassbandfilters centeredat and they form Hilbert
pairswhere is larger thanthe largestfrequency of thebasebandenvelopepulses
and (seeFig. C.1) [73][74]. It canbeshown thatby addingcomplex rotatorsof the
form and to the input and output of a CAP transceiver a
QAM transceiver, is obtained[73]. Therefore,it is possibleto usea CAP receiver for a
QAM transmitter. It shouldbenotedthata CAP systemis practicalwhenthecarrierfre-
quency is near-baseband, so that it can be realized by reasonable order of I-Q filters.
C.3 Conventional CAP Receiver
Fig. C.2showsaconventionalCAPreceiver in whichdigital filtersLI(z) andLQ(z) per-
form both the passbandequalizationandI-Q signalsseparation[73][74][23]. The above
taskrequiresa front-endADC with a samplingrateconsiderablylarger thanthe symbol
ratein orderto preventaliasing.TheADC ratedependson thesymbolrate,excessband-
width, carrier frequency and the order of the filters. Using raisedcosineshapingfilters
with 20%excessbandwidthandanear-basebandcarrierfrequency, around0.6fs, theprac-
tical valuefor theADC samplingrateis about3 timesthesymbolrateor 3fs. Accordingto
system-level simulationresultsfor our targetapplication,i.e.1.2Gb/s16-CAPover200-m
coaxialcablewith 300-MHzbaudrate,for asymbolerrorrateof about10-8, theminimum
f c
f c g t( )
f t( )
exp jωc
nT( ) exp j– ωc
nT( )
Figure C.2: Conventional hardware-efficient CAP receiver with passbandequalization.
-
-
I out
Q out FFE Q
FFE I
Error I
Error Q
Analog front-end Digital post processing
A/D
3fs
3
3Slicer
Slicer
Input signal
(15-tap Digital FIR @3fs)
(15-tap Digital FIR @3fs)
Error I
Error Q
LI(z)
LQ(z)
150
hardwarerequirementsfor a conventionalreceiver arean 8-bit 900-MHz front-endADC
alongwith a pair of 15-tapadaptive FIR digital filters.As a result,theconventionaltopol-
ogy is more appropriate for medium speed applications.
C.3.1 Front-end ADC Requirements
TheequivalentI-Q pathof acomplex CAPsystemis shown in Fig. C.3.To maintainan
acceptablesystembit errorrate,theADC hasto meetcertainresolutionandspeedrequire-
ments.To determinethe resolutionrequirement,similar to (3.11) for PAM systemsin
Chapter3, we considerthe varianceof the total remainingerror beforethe slicer in Fig.
C.3, as
(C.1)
where is thequantizationnoisevarianceintroducedby theADC, is thevarianceof
the additive channel noise, is the error enhancementfactor causedby the
feedforward equalizer(FFE), and is the remaininginter-symbol (ISI) and I-Q
interference error variance.
Similar to (3.15),it canbeshown that therequirednumberof bits for the front-end
ADC can be obtained from
, (C.2)
σerr I Q,( )2 σqz
2 σn
2+( )K FFE
2[ ] σISI IQ–2
+=
σqz
2 σn
2
K FFE
2
σISI IQ–2
ADC
ChannelNoise
QuantizerNoise
σx
2
σqz2
σn
2
+a
-3a-a
+3a
_
Figure C.3: The equivalent I-Q path of a complex 16-CAP system.
FFEI,Q
σerr
2
Channel& Filtering
XI
k( ) XI Q,ˆ k( )
XQ
k( )
C z( )
R
R L dB( )2
K FFE dB( )2
– εq dB( )2
–( ) 6.02⁄>
Appendix C:Reduction of ADC Requirements in CAP/QAM Receivers 151
where is proportionalto thecrestfactorof theADC input as .
is relatedto thedesiredsymbolerrorrate(SER)aswell astheparticipationratio of the
enhancedquantizationnoise to the total error as mentionedin (3.14). For
example,for andassuming33% participationof quantizationnoiseto the
total error, dB. Accordingto (C.2), the main approachto reducingthe bit
requirement is to reducethe factors (the crestfactorof the ADC input signal)and
(the amount of noise enhancement by the digital equalizer).
Since dependson theequivalentchannelresponsebeforetheADC and depends
on the existing ISI and I-Q interferencesafter the ADC, by transferring part of
equalizationandI-Q separationfrom digital to theanalogside,thevaluesof and
canbereduced,simultaneously. As aresult,therequiredADC resolutionR canbereduced
as well.
C.4 The Proposed Architecture
Fig. C.4depictstheproposedmixedanalogCAP receiver architecture.In this architec-
ture,partsof thedigital I andQ passbandequalizersaretransferredto theanalogside.In
this topology, anapproximationof thefractionally-spacedI andQ filters aresplit into two
εq
2 εq
21 3⁄( ) xmax σx⁄( )2
=
L
σ'qz
2 σerr
2
SER 109–
=
L dB( )2
32–=
R εq
2
K FFE
2
εq
2K FFE
2
εq
2K FFE
2
Figure C.4: The purposed mixed CAP receiver architecture.
-
-
I out
Q out
A/D
H1(z)
H2(z)
H3(z)
H4(z)
Error I
Error Q
fs
Analog front-end Digital post processing
Error Q
Error I
Error I
Error Q
GI(z)
Inputsignal
Slicer
Slicer
Digital
HI(z)
tap FIR@fs (3-5)-Analog-tap FIR@3fs (3-5)
A/D
fs Digitaltap FIR@fs (3-5)-
Analogtap FIR@3fs (3-5)-
All 3-tap Digital
GI(z) HI(z)
GQ(z) HQ(z)
Error IError I
Error Q Error Q
HQ(z) HQ(z)
152
fractionally spacedandbaud-ratefilters with lower orders,asdemonstratedin Fig. C.5.
For example,a 4-tapanalogFIR filter [6][17] runningat 3fs followedby a down-sampler
anda5-tapFIR filter runningat fs is equivalentto a16-tap((3x(5-1)+4)FIR filter running
Figure C.5: (a) Conventional CAP receiver I-Q path. (b) Splitting of approximatedinto two cascaded filters. (c) The proposed receiver I-Q path with two low-order analogand digital filter and low-rate low-resolution ADC. (d) Simulation results for I-Q pathfilters impulses and their 17-tap equivalent filters.
L z( )
3
GI,Q(z) HI,Q(z)3
ADC
LI,Q(z) 3ADCChannelOutput
X(k)I,Q
X(k)I,Q
9-17 tap
9-15 taps3-5 taps
3-5 tap
ADC
3-5 tapsAnalog FIR
fsDigital FIR
X(k)I,Q
3fs
ChannelOutput
ChannelOutput
(a)
(b)
−2 0 2 4 6 8
−2
0
2
0 5 10 15
−2
0
2
0 10 20−4−2
024
−2 0 2 4 6 8
−2
0
2
0 5 10 15
−2
0
2
0 10 20−4−2
02
GI(z) GQ(z)
HI(z3) HQ(z3)
LI(z) LQ(z)
(d)
L z( ) G z( )H z3( )=
HI,Q(z3)GI,Q(z)
3fs
(c)
Appendix C:Reduction of ADC Requirements in CAP/QAM Receivers 153
at 3fs. In this way, afteradaptationof thecascadedfilters,severaladvantagesarerealized.
First, the secondarydigital I andQ filters will be low orderwhile they run at 1/3 of the
speed.Secondly, theADCsbeforedigital filterswill runatsymbolratefs, ratherthanat3fs
in conventionaltopology. Thirdly, partialequalizationandI-Q separationby analogfilters,
simultaneouslyreducethecrestfactorof theADC input signalandthequantizationnoise
enhancementafter the ADC. This reducesthe bit requirementof the ADC by about1-2
bits.
Although in this architecturethereis a needfor two ADCs, thespeedof eachis about
one third and their resolutionsare 1-2 bits lower. Thus, regarding the power, areaand
designfeasibility of just theADC partof thehardware[2][30], this architecturewould be
a preferredchoiceat high speeds.It shouldbe notedthat sincethe outputof the analog
FIR filters aredownsampledby 3, a polyphaseimplementationof them canbe utilized
[75]. In this way, each tap multiplication is performed with one third of the speed.
To furtherrelaxthecomplexity of analoganddigital I/Q feedforwardfilters,cross-cou-
pled low orderdecisionfeedbackequalizers(DFE) areemployed aswell. They partially
assistthepost-cursorequalizationandI-Q separationwithout noiseenhancement[7]. The
DFEsarechosento be low order(3-tap)to reducepropagation error effect andimprove
the convergence speed of the adaptation algorithm, particularly during initialization.
C.5 Simulation Results
TheproposedCAP receiver, depictedin Fig. C.4, andthe conventionalone,shown in
Fig. C.2, weresimulatedfor performancecomparisons.The generalcriteria usedin this
work is therelative rootmeansquareerror(RRMSE).This is definedasthemaximumI-Q
residualRMS error, beforetheslicers,relative to thedistancebetweenCAP constellation
points.Accordingto thesimulationresults, resultsin a symbolerrorrate
of about 10-8 for our target application.
To achieve RRMSE=0.08,thefilters LIQ(z) in conventionaltopology(Fig. C.2) are15
tapsandthe filters GIQ(z) andHIQ(z) in the proposedoneare5 taps.All DFE filters are
only 3 taps.The filters areadaptedusingleastmeansquarealgorithm(LMS) [26] using
theerrorsignalbetweenthe input andoutputof theslicers.However, a trainingsequence
at thebeginningacceleratestheinitialization.Thetotal numberof digital filter tapsin the
RRMSE 0.08≈
154
proposedarchitectureis 22 (=5x2 + 4x3), while in theconventionalone,it is 30 (=15x 2)
for anequivalentperformance.Notethattheinputsignalof theDFEfiltersare2-bit digital
outputof theslicers.Therefore,they requiremuchsimplermultiplierscomparedto those
in FFEs.
In Fig. C.5(c) the impulsesof the5-tapGIQ(z) andHIQ(z) andtheir equivalent17-tap
filters with the form of
(C.3)
areshown. TableC.1shows thereductionof theADC input crestfactorandthereduction
of quantizationnoise enhancementby the digital equalizersaccordingto the obtained
impulse responsesand expressions(3.10) and (3.16). In total, a potential 12.5 dB
reductionin ADC resolutionrequirementis achievedandthis is equivalentto 2 bits. This
resolutionenhancementis crediblewhentheremainingtotalerroris notsaturatedby other
errorssuchasremainingISI or enhancedchannelnoise.With thechosenfilter ordersthis
is not the caseandthus,the effect of ADCs resolutionsis evident in the resultingerror
performance, as is shown in Fig. C.6.
Table C.1: Comparison of conventional and the proposed 16-CAP topologies simulation results
ConventionalArchitecture
ProposedArchitecture
Improvement
Crest Factor change before
ADC or
12.8 dB 6.4 dB 6.4 dB
Quantization noise
enhancement
5.5 dB -0.6 dB 6.1 dB
Required ADC bits: R
(for SER=10-9, see(C.2))
8.1 bits 6 bits 2.1 bits
RRMSE, 5-bit ADC 0.18 0.09 6 dB
RRMSE, 6-bit ADC 0.11 0.07 3.9 dB
RRMSE, 7-bit ADC 0.08 0.07 1.2 dB
RRMSE, 8-bit ADC 0.07 0.07 0 dB
LI Q, z( ) G
I Q, z( ) H⋅I Q, z
3( )=
εq2∆
K∆FFF2
Appendix C: Reduction of ADC Requirements in CAP/QAM Receivers 155
Fig. C.7 shows the recovered constellations before the slicers for both the conventional
and the proposed topology. As we can see, the proposed system with two 300-MHz 6-bit
ADCs gives the same performance as the conventional system with a 900-MHz 8-bit
ADC.
3 4 5 6 7 8 9 100.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.2
Number of ADC bits
Rel
ativ
e R
MS
E
Proposed MixedConventional
Figure C.6: RRMSE of the recovered 16-CAP data for different ADC resolutionsfor (a) conventional architecture, and (b) proposed mixed architecture.
(a)(b)
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
In−Phase
Qu
ad
ratu
re
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
In−Phase
Qu
ad
ratu
re
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
In−Phase
Qu
ad
ratu
re
Figure C.7: Recovered 16-CAP data constellation before the slicer for different front-end ADC resolution in: (a) conventional architecture with a 900-MHz ADC, and (b)proposed architecture with two 300-MHz ADCs.
(a) Conventional Topology
(b) Proposed Topology
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
In−Phase
Qu
ad
ratu
re
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
In−Phase
Qu
ad
ratu
re
−1.5 −1 −0.5 0 0.5 1 1.5−1.5
−1
−0.5
0
0.5
1
1.5
In−Phase
Qu
ad
ratu
re
4-bit ADCs 5-bit ADCs 6-bit ADCs
4-bit ADC 5-bit ADC 8-bit ADC
156
C.6 Summary
Theapproachof partialequalizationandI-Q separationfor anearbasebandI-Q system
(CAP) receiver in wired applicationswasinvestigated.Accordingto simulationresults,it
was shown that for an applicationof 1.2 Gb/s over 200-m coaxial cable,the proposed
topology with two 300-MHz 6-bit ADCs along with two 3-to-5-tapanalogFIR partial
equalizerfilters gives the sameerror performanceasa conventionalsystemwith a 900-
MHz 8-bit front-endADC. Moreover, the digital filtering complexity, accordingto the
total numberof tapsandmultiplicationsaswell asclock rate,wasconsiderablyreduced.
The implementationandcircuit designissuesof thepurposedarchitectureis a suggested
topic for future research.
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