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Quality and Reliability Challenges for Package‐on‐Package (PoP) iMAPS San Diego
Cheryl Tulkoff
February 18th, 2013
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Agenda
o PoP Background
o Configurations and Examples
o PoP compared to SiP
o Assembly
o Warpage Issues
o Drop Testing Impact
o Thermal Cycles
o Reliability
o Underfill
o Low-k dielectric
• Root Cause
• Next Generation PoP
• TMV
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Benefits of PoP
o The benefits of PoP are well known. They include:
o Less board real estate
o Better performance (shorter communication paths between the micro
and memory)
o Lower junction temperatures (at least compared to stacked die)
o Greater control over the supply chain (opportunity to upgrade
memory and multiple vendors)
o Easier to debug and perform F/A (again, compared to stacked die
or multi-chip module or system in package)
o Ownership is clearly defined: Bottom package is the logic
manufacturer, the top package is the memory manufacturer, and the
two connections (at least for one-pass) are the OEM
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Package on Package (PoP)
o A configuration where two packaged integrated circuits
are placed directly on top of each other
o Also known as stacked packages
o Interconnects are between the top package and the bottom
package and the bottom and the PCB
o Top package traditionally contains multiple or stacked die
o Bottom package traditionally contains smaller / thinner die
4
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Stacked Package
o The concept of stacked
packages has been around
since the 1980’s
o Patent 5,625,221 (1994)
o Stackable BGAs first proposed
in Micron patent
o Patent 6,072,233 (1998)
5
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PoP Chronology
o More recent terminology of package-on-package (PoP)
can be traced back to ECTC 2003 (Nokia / Amkor)
o Refers almost exclusively to stackable BGAs
o Broad implementation in industry by 2005
o Standardized in 2006
o JEDEC JEP95 Section 4.22
o MO-266A: Bottom; MO-273A: Top
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PoP (Stacked BGAs)
o Bottom Package
o Has land pads on top perimeter to allow for top PoP attach
o Molded using special process to keep perimeter clear
o Requires thin die and mold cap to allow for top package clearance
o Top Package
o Based on conventional stacked die BGA but larger ball size and thinner mold body
o Ball pitch and size constrained by need to clear bottom package
o Packages must be capable of being placed on the printed circuit board (PCB) and reflowed simultaneously to each other and to the board
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PoP Stacked BGAs (cont.)
o Both packages are relatively thin o Maximum height typically 1.4 to 1.6 mm
o Focus tends to be on slimming top package
o Thinning of bottom package can be difficult o Thinner substrate can increase warpage
o Smaller ball size can impact drop testing and temp cycle
o Standard package sizes o 15x15 mm, with 14x14 and 12x12 also available
o 0.65mm pitch, with 0.5mm and 0.4mm available
o Ball size can vary from 0.45 to 0.35mm
8
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Source: Mario Bolanos “Packaging Trends Applied Research Opptys at U. of Binghampton CAMM
Reuse of Technology
for uP / Memory
Interface
Flexible Processor &
Memory Architectures:
Bband Modem, Apps uP,
DDR and NVM
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PoP Forecast
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PoP addresses integration challenges to enable
semiconductor advancements . . .
. . . to cost affectively deliver physical
world benefits.
Smartphone advancements aided by PoP technology
and cost of ownership benefits.
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12
PoP Configurations
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13
PoP Examples
o Stacked Package on Package (PoP): The placement is often
arranged through a soldering operation, but can also be
performed with other interconnect technology
Example of
package on
package device
from Samsung
Example of package
on package devices,
with stacked die in
each package, from
Mitsubishi
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PoP Examples (cont.)
14
Texas Instruments
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Why PoP?
o Yield / Flexibility / Ownership
o No issues with known good die (KGD)
o Memory can be easily upgraded
o Also allows for multiple sourcing
o Ownership is clearly defined
o Bottom package: Logic manuf.
o Top package: Memory manuf.
o Board level connection: OEM
15
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Die vs. Package Stack Analysis
(Business model has huge impact on Cost of Ownership)
Vertical Die Qty 2 3 4 5
Cumulative Die Yield High Low
Die / Test Costs Low High
Require burn-in No Yes
Die/Memory Sourcing Simple Complex
Sourcing flexibility No Yes
Design flexibility No Yes
PoP
(Dominant for
Applications
processor +
complex
memory
stacking)
100%
0%
% of Applications
3D SiP
(Dominant
for Combo
Memory & Digital
+ analog)
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17
Thermal Comparison
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PoP Uses
o Dominant use
o Integration of digital logic device in bottom package with combination memory devices (i.e. DRAM and flash) in top package
o Top package typically stacked die
o Some pure memory PoP solutions also available
o Cameras / mobile devices are main users
o Increasing interest from high reliability industries
18
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PoP Assembly Process
o Assembly of PoP can be through
one or two reflows
o Most commonly single
reflow (aka, one-pass)
o Top package is typically
dipped before placement
o Flux (sticky) or solder paste
19
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PoP Assembly (cont.)
o PoP can also be offered
as a two-pass assembly
o IDM assembles top and
bottom package and places
them in a carrier for board-
level assembly
o Other assembly options include use of solder on pad
(SoP) on bottom package
20
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Solder on Pad (SoP)
o Consists of solder balls
on the topside of the
bottom package
o Designed to induce a
larger solder joint collapse
to absorb package warpage
o Difficulties
o Balls must be well aligned
(limited self-alignment)
o Top package can slide off the balls
during placement or reflow,
leading to a poor solder joint or bridging
21
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Warpage
o Many technical challenges present in PoP assembly
o Improper reflow profiles can lead to solder balls dislodging or migrating off the pad
o Excessive warpage can lead to solder ball bridging, solder slumping, head and pillow defects, or open joints
o Number one challenge in assembly is controlling and matching warpage of top and bottom packages
o More than 90% of the defects in PoP assembly are due to package warpage (cit. KIC)
o Minimizing warpage is a trade off between materials, temperature control and time
o The extent and degree of warpage is increasing as substrates become thinner
22
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o Mold
o Material property
o Shrinkage
o Thickness
• Laminate Substrate – Properties
– Thickness
– Cu ratio
– Routing
• Die attach – Material property
– Thickness
• Die – Die size
– Die Thickness
Design Factors Impacting Warpage
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Package Warpage
o Due to mismatch in CTE between the substrate, mold compound and die
o Die attach can also play a role
o High Tg mold compounds are used to balance CTE mismatch between die and substrate
o Effect of mold compound becomes negligible at reflow temperatures
24
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Warpage (cont.)
o General warpage trend at room temp. o Inconclusive
o Some claim bottom is smiling (positive, concave) while top is crying (negative, convex) o Others claim the reverse
o Partially dependent if CTE of mold compound is more / less than substrate
o Example: Periphery of bottom package is devoid of mold compound o At reflow temperature, exposed
substrate could expand more compared to substrate under the mold compound
o Desirable to have matching warpage
25
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Warpage and Yields
26
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Warpage and Yields (cont.)
27
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Warpage Drivers: Die
o Thinner die and smaller die tend to minimize warpage
o Larger / thicker die tend to drive crying at RT
28
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Warpage and Reflow Profile
29
Ramkumar, 2008 European Electronic Assembly Reliability Summit
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Recommendations for improving SMT and Stacking yield
o Warpage data processing methods
o Appropriate methods
A
Package corner to
package corner
B
Array corner to
array corner
C
Inner and outer
corners of ball
matrix (diagonal)
D
Ball matrix corner to
corner (sides)
Top Pkg
Bot Pkg
Top Pkg
Bot Pkg
Use Methods
C & D
Use Methods
B*, C & D * Method B to check for interference
of warped packages at the center
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Reliability: Drop Testing / Warpage
31
Process Development and Reliability Evaluation for Inline Package-on-Package (PoP) Assembly (Flextronics)
Test vehicle was a mechanical dummy of a cell phone
The drop-test was 3 cycles on six sides = 18 drops from 1.5m
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Drop Testing / Warpage (cont.)
32
Four different failure modes observed during drop testing Failure mode 4 was only found
on combination B
Combination B Low yield with ENIG surface
finish
Poor warpage alignment
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Drop Testing (Results)
33
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Underfill
o Typically a filled epoxy
o High modulus (>10 GPa)
o Range of coefficient of thermal expansion (CTE) values
(16ppm – 30ppm)
o Improves drop test performance
o Reduces stress on interconnect due to substrate bending
o Improves thermal cycling robustness
o Reduce shear stress on solder
o Links die and substrate to reduce thermal expansion
mismatch
34
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Underfill Design Considerations
o Design Considerations for Package on Package Underfill
o In PoP, the top and bottom packages are usually the same size.
o Both levels must be underfilled for good reliability. They also must be filled simultaneously.
o The top layer underfills more slowly than the bottom layer because of the thermal delta between the top and bottom levels.
o In order to underfill both levels simultaneously, the fluid must reach the top of the second level gap.
35
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Reliability: Underfill and Thermal Cycling
• Temp cycle
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Underfill and Thermal Cycling (cont.)
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Underfill and Temperature Cycling
• Rapid time to failure for underfills D / F / G
• Best reliability
o No underfill or underfill with Tg > 110C (A and C)
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Reliability
• Underfill is increasingly being considered for PoP
o Improves 2nd level reliability under drop testing
• However, increasing indications that use of underfill
may greatly reduce reliability under temperature cycling
• Case Study (-40 to 125C)
o With underfill: 300 cycles
o Without underfill: >1000 cycles
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Reliability
o From this study, it was understood that underfill material improves the stress distribution in solder joints during temperature cycling test and drop test.
o Lower CTE & higher Tg in underfill were more effective than other factors in the temperature cycle performance.
o Temperature cycling test results show that the filler type underfills provides substantially improved temperature cycling performance over non filler type underfills.
o Underfill A passed 2500 cycles under the JEDEC JESD22-A104C Condition G (– 40 ~ 125’C, 1cycle/hour). Additionally, it exceeded 400 drops as well.
40
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Reliability
o Non filler type underfills which passed the acceptability criteria of 500 temperature cycles and underfill G was shown good drop performances as well.
o Low modulus materials are more rubbery as to absorb the drop impact by way of deformation.
o Non filler type underfill provides process benefits. It was easier to apply the rework process than filler type underfill.
41
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PoP Reliability – Drop Test: Package & Board
o Package level reliability is generally robust and leverages enabling technology developed for stack package
o Materials technology continues to improve
o Board level reliability is key issue
o Drop test is most important for mobile application
o No underfill after board mount is desired
o Correct ball land finish, ball alloy, and design rule for each interface need to be used
o Package construction and warpage control to allow for robust reflow and joint formation
o Development of improved board mount equipment and process
o Good board level reliability and drop test has been demonstrated even for large POP size
42
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Reliability
• Underfill with optimum temperature cycling and drop performance
o A (high Tg and high filler)
• Important note
o Low modulus materials are more rubbery as to absorb the drop impact by way of deformation
o Non filler type underfill provides process benefits; easier to apply than filler type underfill
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Consumer Electronics
o Drivers of technology improvement
o 90nm 65nm 45nm
o Demanded by their customers
(especially users of graphic intensive
applications)
o What has changed in IC technology with smaller
feature sizes?
o Introduction of Low-k Dielectric
44
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Low-k Dielectric
NVIDIA Confidential
Underfill Material: A Balance Between Bump and LowK
Modulus
Tg
Prevent Bump Crack
Prevent LowK Crack
Optimum Underfill Properties
Bump
Crack
LowK
Crack
45
o Defined as dielectric constant < 3.0
o Initiated at 90nm, common in 65nm
o Provides improvement in performance
o Shortens RC delay
o Reduces power consumption (CV2f)
o To lower the dielectric constant below ~2.7, porosity is increased
o Reduces fracture toughness
o Reduces modulus
o Greatly increases likelihood of cracking(especially with certain underfills)
Low-k
SiON
Copper
SiO2 Metal HM
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Industry Response to Low-k Cracking
NVIDIA Confidential
Underfill Material: A Balance Between Bump and LowK
Modulus
Tg
Prevent Bump Crack
Prevent LowK Crack
Optimum Underfill Properties
Bump
Crack
LowK
Crack
46
o IC performance requirements drive all other aspects of electronic packaging
o Improvement in low-k dielectric? No. Change in underfill? Yes.
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Industry Response (cont.)
o A number of IC manufacturers switched from high
Tg (>130C) to low Tg (<80C) underfills
o Drivers: Bottleneck in Electronic Supply Chain
o Die foundry material limitations
o Contract packaging supplier recommendations
o 1st Problem: Violated a cardinal rule of electronic
packaging design
o Never use material that has a transition temperature (Tg,
solidus, etc.) within the expected operating range
47
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Product Qualification
o Flip chip devices with this new, low Tg underfill, passed all industry standard product qualification tests
o -55C or -40C to 125C, 1000 to 3000 cycles
o 2nd problem: Testing through a transition temperature will not necessarily induce relevant failure mechanisms
o Result: High rate of field failures
o Relatively short period of time (within 2-10 months)
o Relatively benign environment
48
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Root Cause of Failure (No. 1)
o If an underfill is used around its glass transition
temperature
o CTE typically changes more rapidly than
Modulus
o This can lead to a large increase in the
expansion with a negligible change in the
modulus
o Can be demonstrated using compatibility
equations
49
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PoP and Temp/Power Cycling
o There are concerns regarding the insufficiency of uniform temperature cycling in PoP o Especially since warpage can be
sensitive to localized temperature gradients
o To overcome this limitation, JESD22-A105C has been developed o Applies temperature excursions and
power cycling o ASE modeled this effect
o PoP test vehicle: VFBGA on SPBGA o Solder: SnPb o Temp cycle: -40C to 125C
o Results: Minimal difference between temp cycling and temp + power cycling o High thermal conductivity likely
minimizes temperature differential o Note: Modeling did not take into
consideration the influence of tensile and compressive stresses
50
Wang, 2007 EPTC Very-thin profile fine-pitch ball grid array (VFBGA)
Stacked package ball grid array (SPBGA)
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Reliability Results
o Reliability is enhanced with:
o Thin die (50 micron vs. 100 micron)
o Thick mold on top package (0.45 vs. 0.35 or 0.25 mm)
o Thick substrate
o Top package (0.21 vs. 0.16 or 0.12 mm)
o Bottom package (0.36 vs. 0.26 or 0.21 mm)
o Large standoff on top package (0.45 vs. 0.40 or 0.35 mm)
o Medium standoff on bottom package (0.23 vs. 0.28 or 0.18 mm)
o Almost all of these parameters move towards minimizing package warpage
o Problem: Except for thin die, PoP design is moving in the opposite direction
51
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52
Typical Test to Spec Results
o Test condition, sample size, and pass/fail
criteria should be shown.
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1st Gen PoP Technologies limit PoP I/O and Bottom Stacked
Die Density – Requiring New Technology
o Die stacking in bottom package requires thicker mold cap
o New memory architectures require higher I/O interfaces
o Higher Semiconductor density requires package size reduction
o Thin form factors and increased battery size require thinner PoP stacks
o Improved warpage control required when go thinner with higher density
o A new bottom PoP technology is needed to continue growth
Multiple die in bottom package0.50mm pitch
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Thru Mold Via Technology (TMV®)
o Enabling technology for next generation PoP reqmts
o Improves warpage control and PoP thickness reduction
o TMV removes bottlenecks for fine pitch memory interfaces
o Increases die to package size ratio (30%)
o Improves fine pitch board level reliability
o Supports Wirebond, FC, stacked die and passive
integration
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Construction and package stack-up for the TMV PoP
Test Vehicle reported at SMTAI 2008
Reference : "Surface Mount Assembly and Board Level Reliability for High
Density PoP (Package on Package) Utilizing Through Mold Via
Interconnect Technology - Joint Amkor and Sony Ericsson", Paper
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TMV® Memory Interface Scaling Benefit
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TMV® Interface Pitch Considerations o 0.5mm TMV pitch
o 12mm 168 2 row In HVM with 0.35mm mold cap (2+0 wirebond
stack)
o 14mm 240 3 row In HVM with 0.28mm mold cap (single die FC
die)
o 0.4mm TMV pitch
o In HVM with 0.25mm mold cap (single die FC)
o TMV solder ball size and hole size is selected for SMT
yield while avoiding solder bridging
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Recommendations for improving TMV® PoP SMT Stacking
yield o Reflow
o Reflow peak temperature: 235 – 245C, Time above Liquidus: 45 – 75 sec
o Avoid long soak time at flux activation temperature, excessive soak time results in flux burn off/dry off causing Head-in-Pillow joints for top to bottom package interconnects:
o Recommendation: Choose flux with recommended pre-heat time of 60 to 75C between 150 – 180C
o Additional Recommendations o Process development on flux or paste
material and dip depth
o Increasing top package ball size to compensate for excessive warpage of top package
Time (sec)
Temp
180’C
150’C
0 110 62
Long
prehea
t
Short
preheat Dried
flux
Flux
Good Joint Non-wet
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Viking RAMStack
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Summary
o 390 million PoP components shipped in 2010 up from < 5 million in 2005. Forecasted to grow at same high rate as Smartphones
o DDR2 2 channel and other new memory architectures driving higher density PoP memory interfaces
o Amkor pioneered 1st Generation PoP (PSvfBGA) and now leading in Next Gen high density PoP with TMV® technology shipping in HVM
o One pass SMT PoP stacking enables optimization of supply / logistics and lowest total cost of ownership
o Amkor and Universal Instruments planning 14mm 620 / 200 TMV PoP SMT stacking study and industry report to facilitate SMT yield / quality optimization
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Who is DfR Solutions
Key Facts
• Founded in 2005 in College Park,
MD
• 20+ Employees
• Multiple US locations
• Offerings
• Research, Lab Services,
Consulting, Software
• 300+ customers, including:
• Dell, HP, Apple, Microsoft, IBM,
Ericsson, Cisco Systems,
Verizon, Huawei, Polycom,
AMD, and Nvidia
Austin, TX
Detroit, MI
Minneapolis, MN
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Tech Insertion
Design
Supply Chain
Test
Warranty
Focus on Quality/Reliability/Durability of Electronics
All levels
of the supply chain
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Expertise in All Technologies
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DfR Solutions – Senior Experts • Dr. Craig Hillman, CEO and Managing Partner
• Expertise: Design for Reliability (DfR), Pb-free Transition, Supplier Benchmarking, Passive Components, Printed Circuit Board
• PhD, Material Science (UCSB)
• Dr. Nathan Blattau, Vice President
• Expertise: Power Devices, DfR, Nonlinear Finite Element Analysis (FEA), Solder Joint Reliability, Fracture, Fatigue Mechanics.
• PhD, Mechanical Eng. (University of Maryland)
• Walt Tomczykowski, Vice President
• Expertise: Life cycle management (including obsolescence), counterfeit mitigation,
• B.S., Electrical Engineering (Rutgers)
• Cheryl Tulkoff, CRE
• Expertise: Pb-Free Transition, PCB and PCBA Fabrication, IC Fabrication, RCA (8D and Red X)
• B.S., Mechanical Engineering (Georgia Tech)
• Dr. Ron Wunderlich
• Expertise: Design for EMI/EMC, Power Supply Design, Analog Circuit Design, Spice Model Development, Monte Carlo Circuit Simulation
• PhD, Electrical Engineering (SUNY – Binghamton)
• Greg Caswell
• Expertise: Nanotechnology CMOS, CMOS/SOS, Input Protection Networks / ESD, SMT, Pb-free
• B.S., Electrical Engineering (Rutgers)
• Dr. Randy Schueller
• Expertise: IC Fabrication, IC Packaging, Pb-Free Transition Activities, Supplier Benchmarking, Corrosion Mechanisms
• PhD, Material Science (University of Virginia)
• Dr. Gregg Kittlesen
• Expertise: LEDs, LCDs, Microprocessors, Memory Components, Photonic and RF Technologies, Supply Chain Management
• PhD, Analytical Chemistry (MIT)
• James McLeish, CRE
• Expertise: FMEA, Root-Cause Analysis, Warranty Analysis, Automotive Electronics, Physics of Failure, Battery Technology
• M.S., Electrical Eng. (Wayne State University)
• Norm Anderson
• Expertise: Avionics, Product Qualification, Safety Criticality Assessment, FTA, FMEA, Component Uprating, Obsolescence
• B.S., Electrical Engineering (Iowa State University)
• Anne Marie Neufelder
• Expertise: Software Reliability Prediction, Best Practices in Software Risk Management
• B.S., Systems Engineering (Georgia Tech)
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