© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-11
0
Bus
SelectS0S1S2
LoadL0L1L2
S0
12–to–1
MUX
n
R0
S0
1
n
R1
S0
1
n
R2
(a) Dedicated multiplexers
n
n
n
LoadL0L1L2
R0
R1
R2
S10
1 3–to–1MUX
S0
Select
n
n
n
n
n
n
n
(b) Single Bus
S10
1
2
2–to–1MUX
2–to–1MUX
Fig. 7-6 Single Bus versus Dedicated Multiplexers
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-12
TABLE 7-6Examples of Register Transfers Using the Single Bus in Figure 7-6(b)
Select Load
Register Transfer S1 S0 L2 L1 L0
1 0 0 0 10 1 1 0 1
Impossible
R0 R2←R0 R1 R2 R1←,←R0 R1← R1 R0←,
Table 7-6 Examples of Register Transfers Using the Single Bus in Figure 7-6(b)
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-13
Bus
Select
n
n
n
n
n
n
n
(b) Multiplexer bus
Bus
LoadL2 L1 L0
EnableE2 E1 E0
LoadL0 L1 L2
R0
R1
R2
3ñtoñ1MUX
(a) Register with bidirectionalinput-output lines and symbol
(c) Three-state bus using registerswith bidirectional lines
R
LOAD
Load
n n
n
En
R
Load
n
En
R0n
En
R1n
En
R2n
En
n
n
2
Fig. 7-7 Three-State Bus versus Multiplexer Bus
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-14
Data busAddress bus
Enable
A0 A1 A2 D2 D1 D0
Addressbusdecoder
0 1 2
0
1
2
3
Load
0
1
2
3
Enable
Read Write
Memory2k x n
nk
Data bussourcedecoder
Data busdestinationdecoder
Timingand
control
Fig. 7-8 Memory Unit Connected to Address and Data Buses
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-15
MD select0 1
MUX D
V
C
N
Z
n
n
n
n
n
n
n
n
n n
n
2 2
n
n
A data B data
Register file
1 0S MUX B
Address Out
Data Out
Bus A
Bus B
n
n
Function unit
A B n
G select4
Zero Detect
MF select
nn
n
F
0 1MUX F
H select2
n
A BS2:0 || Cin
Arithmetic/logicunit (ALU)
G
BS
Shifter
H
MUX
0
1
2
3
MUX
0
1
2
3
0 1 2 3Decoder
Load
Load
Load
Load
Load enable
WriteD data
D address2
Destination select
Constant in
MB select
A select
A address
B select
B address
R3
R2
R1
R0
Bus Dn
Data In
ILIR0 0
Fig. 7-9 Block Diagram of a Datapath
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-16
n-bitarithmetic/logicunit(ALU)
A0
A1
An–1
B0
B1
Cin
S0
S1
S2
Bn–1
Datainput A
Datainput B
Carry input
Operationselect
Mode select
{
G0
G1
Gn–1
Cout
Dataoutput G
Carry output
•••
•••
•••
Fig. 7-10 Symbol for an n-Bit ALU
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-17
S1
S0
Bn
B inputlogic
nA
n
X
Cin
Y
n-bitparalleladder
n G = X + Y + Cin
Cout
Fig. 7-11 Block Diagram of an Arithmetic Circuit
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-18
TABLE 7-7Function Table for Arithmetic Circuit
Select Input
S1 S0 Y
0 0 all 0’s (transfer) (increment)0 1 B (add) 1 0 B (subtract)1 1 all 1’s (decrement) (transfer)
G A Y Cin+ +=
Cin 0= Cin 1=
G A= G A 1+=G A B+= G A B 1+ +=
G A B+= G A B 1+ +=G A 1–= G A=
Table 7-7 Function Table for Arithmetic Circuit
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-19
(a) Truth table
Inputs Output
S1
00
00
11
11
S0
00
11
00
11
Bi
01
01
01
01
Yi
00
01
10
11
Yi = 0
Yi = Bi
Yi = 1
Yi = Bi
0
1
S0
Bi
S1 1 1
00 01 11 10
1
1
(b) Map Simplification: Yi = BiS0 + BiS1
Fig. 7-12 B Input Logic for One Stage of Arithmetic Circuit
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-20
••
•
•
•
Cin
S1
S0
A0B0
A1B1
A2B2
A3B3
C0
G0
X0
Y0
FA
C1
G1
X1
Y1
FA
C2
G2
X2
Y2
FA
C3
G3
X3
Y3
FA
C4Cout
••
•
••
•
••
•
•
Fig. 7-13 Logic Diagram of a 4-Bit Arithmetic Circuit
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-21
S1
0
0
1
1
S0
0
1
0
1
Output
G = A B
G = A B
G = A B
^^
G = A
Operation
AND
OR
XOR
NOT
(b) Function Table
••
•
•
•
S0
S1
AiBi
S0
S1
4–to–1MUX
0
1
2
3
(a) Logic Diagram
•
Gi
Fig. 7-14 One Stage of Logic Circuit
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-22
Gi
•
•
••
Ci
Ai
Bi
S0
S1
S2
Ci + 1
One stage ofarithmetic
circuit
One stage oflogic circuit
2–to–1MUX0
1S
Fig. 7-15 One Stage of ALU
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-23
TABLE 7-8Function Table for ALU
Operation Select
S2 S1 S0 Cin Operation Function
0 0 0 0 Transfer A0 0 0 1 Increment A0 0 1 0 Addition0 0 1 1 Add with carry input of 10 1 0 0 A plus 1’s complement of B0 1 0 1 Subtraction0 1 1 0 Decrement A0 1 1 1 Transfer A1 0 0 X AND1 0 1 X OR1 1 0 X XOR1 1 1 X NOT (1’s complement)
G A=G A 1+=G A B+=G A B 1+ +=G A B+=G A B 1+ +=G A 1–=G A=G A B∧=G A B∨=G A B⊕=G A=
Table 7-8 Function Table for ALU
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-24
B3 B2 B1 B0
Serialoutput R
ILIR
S
H3 H2 H1 H0
Serialoutput L
SMUX
0 1 2S
MUX
0 1 2S
MUX
0 1 2S
MUX
0 1 2
2
•
•
•
•
• • •
Fig. 7-16 4-Bit Basic Shifter
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-25
D3 D2 D1 D0
S0
S1
• • •• •
••
••
••
••
••
3 2 1 0 S1 S0
MUX
Y3
3 2 1 0 S1 S0
MUX
Y2
3 2 1 0 S1 S0
MUX
Y1
3 2 1 0 S1 S0
MUX
Y0
•
Fig. 7-17 4-Bit Barrel Shifter
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-26
TABLE 7-9Function Table for 4-Bit Barrel Shifter
Select Output
S1 S0 Y3 Y2 Y1 Y0 Operation
0 0 D3 D2 D1 D0 No rotation0 1 D2 D1 D0 D3 Rotate one position1 0 D1 D0 D3 D2 Rotate two positions1 1 D0 D3 D2 D1 Rotate three positions
Table 7-9 Function Table for 4-Bit Barrel Shifter
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-27
Address out
Data out
Constant in
MB select
Bus A
Bus B
FS
V
C
N
Z
MD select
n
D dataWrite
D address
A address B address
A data B data
2m x nRegister file
m
m m
n nn
n
n
A B
Functionunit
F
5
MUX B1 0
MUX D0 1
n nData in
Fig. 7-18 Block Diagram of Datapath Using the Register File and Function Unit
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-28
TABLE 7-10G Select, H Select, and MF Select Codes Defined in Terms of FS Codes
s
FSMFSelect
GSelect
HSelect Microoperation
00000 0 0000 0000001 0 0001 0000010 0 0010 0000011 0 0011 0000100 0 0100 0100101 0 0101 0100110 0 0110 0100111 0 0111 0101000 0 1000 001010 0 1010 1001100 0 1100 1001110 0 1110 1010000 1 0000 0010100 1 0100 0111000 1 1000 10
F A=F A 1+=F A B+=F A B 1+ +=F A B+=F A B 1+ +=F A 1–=F A=F A B∧=F A B∨=F A B⊕=F A=F B=F sr B=F sl B=
Table 7-10 G Select, H Select, and MF Select Codes Defined in Terms of FS Codes
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-29
(b) Control word
DA AA BA MB
FS MD
RW
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10
8
16
14
0
13
11
Bus D
Constant inn
n
MUX B1 0
D dataWrite
D address
A address B address
A data B data
8 x nRegister file
A B
Functionunit
n
n
n
MUX D
0 1
n n Data in
Bus A
Bus B
RW
12AA
15DA
n
BA9
Address out
Data out
VCNZ
MB 7
MD 1
6
4 FS
5
32
(a) Block Diagram
Fig. 7-19 Datapath with Control Variables
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-30
TABLE 7-11Encoding of Control Word for the Datapath
DA, AA, BA MB FS MD RW
Function Code Function Code Function Code Function Code Function Code
R0 000 Register 0 00000 Function 0 No write 0R1 001 Constant 1 00001 Data In 1 1Write
1
R2 010 00010R3 011 00011R4 100 00100R5 101 00101R6 110 00110R7 111 00111
01000010100110001110100001010011000
F A=F A 1+=F A B+=F A B 1+ +=F A B+=F A B 1+ +=F A 1–=F A=F A B∧=F A B∨=F A B⊕=F A=F B=F sr B=F sl B=
Table 7-11 Encoding of Control Word for the Datapath
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-31
TABLE 7-12Examples of Microoperations for the Datapath, Using Symbolic Notation
Micro-operation DA AA BA MB FS MD RW
R1 R2 R3 Register Function WriteR4 — R6 Register Function WriteR7 R7 — Register Function WriteR1 R0 — Constant Function Write— — R3 Register — — No WriteR4 — — — — Data in WriteR5 R0 R0 Register Function Write
R1 R2 R3 1+ +← F A B 1+ +=R4 sl R6← F sl B=R7 R7 1+← F A 1+=R1 R0 2+← F A B+=Data out R3←R4 Data in←R5 0← F A B⊕=
Table 7-12 Examples of Microoperations for the Datapath, Using Symbolic Notation
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-32
TABLE 7-13Examples of Microoperations from Table 7-11, Using Binary Control Words
Micro-operation DA AA BA MB FS MD RW
001 010 011 0 00101 0 1100 000 110 0 11000 0 1111 111 000 0 00001 0 1001 000 000 1 00010 0 1000 000 011 0 00000 0 0100 000 000 0 00000 1 1101 000 000 0 01100 0 1
R1 R2 R3–←R4 sl R6←R7 R7 1+←R1 R0 2+←Data out R3←R4 Data in←R5 0←
Table 7-13 Examples of Microoperations from Table 7-11, Using Binary Control Words
© 2001 Prentice Hall, Inc.M. Morris Mano & Charles R. KimeLOGIC AND COMPUTER DESIGN FUNDAMENTALS, 2e, Updated.
7-33 Clock
DA
AA
BA
MB
RW
Constant in
FS
Data in
MD
R0
R1
R2
R3
R4
R5
R6
R7
Status bits
Address out
Data out
1 2 3 4 5 6 7 8
1 4 7 1 0 4 5 ×
2 6 7 0 ×
3 0 ×3 0
2× ×
05 24 01 02 00 0C ×
× 18 ×
00
01 FF 02
02
03
04 0C 18
05 00
06
07 08
4 0 8 ×
0702 00 ×00
03 06 ×03 00
×
×
×
00
Fig. 7-20 Simulation of the Microoperation Sequence in Table 7-13