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HUAWEI TECHNOLOGIES CO., LTD.
System-Level ASIC Algorithm Simulation Platform using Simulink
Dr. Sun, Defu
Huawei Technologies Co., LTD.
2015/11/03
HUAWEI TECHNOLOGIES CO., LTD.
Contents
Page 2
p Background
p System-‐Level Algorithm Simulation Tool Options
p Challenges and Solutions in System-‐Level Simulation
p Future Work
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BackgroundHuawei Technologies Co., LTD.
Global leading supplier of information and communication solutions. Dedicated to Telecom operators, Enterprise and Consumer industries to provide competitive and comprehensive solutions and services. So far, Huawei’s products and solutions are in more than 170 countries and regions, serving more than 1/3 of the world’s population.
l Employees 170K, R&D: 70K+, 150 countries all around the world
l 15 business units, service in 170+ countries and regions
l Patents: 60000+
l Participation in Standards and Open Source Organizations: 170+ (180+ Positions)
l Revenue in 2014 $46B,2015 H1 $28B,YoY Growth 30%
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Presenter
n Dr. Sun, Defu, USTC, Ph.D. of
Communication and Information.
n System Engineer in Huawei
Technologies Co., LTD.
Major focus on Physical Layer
algorithm research including Wireless
LTE, Microwave, Copper DSL/Cable
algorithms and architectures. Dr. Sun
has 7-year experience in baseband and
intermediate frequency physical layer
algorithms.
Background
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Algorithm Simulation/Verification Workflow in ASIC
Floating Point Design/Verification
Fixed Point Design/Verification
Floating/Fixed PointComparison
Algorithm/ASIC Comparison
Sub-module Simulation
Link-Level Simulation/Verification
Floating Point Performance OK
Sub-module Fixed Point Design/Verification
Link-Level Fixed Point Optimization/ Verification
Fixed Point Performance OK
Sub-module Floating/Fixed Point Comparison
Link-Level Floating/Fixed Point Comparison
Comparison OK
Module Level Comparison
Link-Level Comparison
Characteristics of ASIC Algorithm Simulation/Verification
1. System Level Design and Verification of Floating Point Arithmetic
2. Accurate Fixed Point design and Performance Comparison with Floating Point
3. Performance Comparison between Fixed Point Algorithm and RTL in ASIC
Compared to conventional floating point algorithm simulation, for ASIC algorithm verification is more extensive to verify accuracy with high degree of confidence
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DFECAAF Synchronization EQ DMAPCH ESTAlgorithm
Simulation Workflow
ASIC Design
Workflow
ASIC Algorithm Simulation Platform Requirements
uModular Simulation and Visualization.Algorithm structure corresponds to the chip architecture.
Model Based Design:Clear algorithm architecture;Matching algorithm structure and ASIC architecture;Easy comparison between algorithm simulation and chip performance
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u Easy Transformation of Algorithm Timing and Control
Bit Clock
Symbol Clock
TX System Clock
Symbol Clock
Bit Clock
RX System Clock
TX RX
Algorithm Module 1
Sub-module1(System Clock)
Sub-module 2Symbol Clock
Multiple Clocks in different algorithms Single algorithm module may needs multiple clocks
ASIC Algorithm Simulation Platform Requirements
ASIC algorithm simulation involves symbol and system clocks, as well as other clock conversions. Simulation platform must provide convenient clocking scheme.
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DFECSynchronization
EQ DMAPCH ESTTime delay
Time delay
p Time-‐Delay Algorithms:Loop Filter, FEC, software processingp Time-‐Sensitive Algorithms:Phase-‐noise compensation, Algorithmic phase-‐jumps
Time delay
Time delay
DFECSynchronization EQ DMAPCH ESTAlgorithm
Simulation
ASIC Algorithm Simulation
ASIC Algorithm Simulation Platform Requirements
u Algorithm simulation can simulate the real ASIC performance
ASIC algorithm simulation needs to consider the impact of processing delays in ASIC
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ASIC Algorithm Simulation Platform Requirements
u Easy performance comparison between algorithm simulation and ASIC
Sub-Module Comparison
System Comparison
Level-LevelComparison
Algorithm Module
ASIC Module
Fixed point input
outputBitComparison
0101101001101
1-‐1 matching between algorithm and ASIC module; Easy switch between modules and system/link level
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p Comprehensive Toolbox
p Accurate Location of Bugs and Easy Debugging
p High Simulation Efficiency
uOther Requirements
ASIC Algorithm Simulation Platform Requirements
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ASIC Algorithm Simulation Platform Requirements
Visual & Modular
Simple Timing Conversion
Real ASIC Performance
Simple Performance Comparison
Comprehensive Toolbox
Debugging and Localization
Efficient Simulation
MathWorks MATLAB & Simulink is great for algorithm simulation in ASIC
Huawei consider it as important ASIC algorithm verification tool
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Challenge and Solutionsu Efficient ASIC algorithm simulationp ASIC algorithms require execution of a large number of simulations for verification. The
efficiency of simulation is critical, and a big challengep Through fully automated pipelined and parallel simulation, to maximize simulation efficiency.
Manual SimulinkSimulation
Semi-Automatic Simulink to C
Automatic Simulink Simulation
p Manually configure simulation parameters, and simulate
p Manually configure module, organize data and document
p Manually configure Simulink to generate C (Simulink Coder), configure data comparison, organize data and document
p Automatic parameterization and simulation with script
p Automatically generate C from Simulink, script parameters, RM files/code, and generate simulation figures/tables/documents
p Automated comparison of data at any level of modules/system
p Efficient Pipeline Simulation approaches
Phase Ⅰ Phase Ⅱ Phase Ⅲ
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Challenge and Solutions
No. Serial Simulation Time
Pipelined Parallel Simulation Time
Simulation Time Reduction
Module 1 163
/Module 2 407Module 3 812Module 4 1084
Total 2459 1375 44%
p Partition into sub-‐modules, increase pipelining. Higher performance but more resources.
p Due to synchronization of the data, maximum latency of the modules is the bottleneck,
leading to compromise of efficiency.
u High efficiency ASIC algorithm simulation and verification
Example of simulation efficiency improvement
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u Off-‐line ASIC Algorithm Simulation and Verification
Challenge and Solutions
p It is crucial for ASIC algorithm performance verification to integrate real channel models
p Co-‐Simulation between Simulink and channel model simulators improve algorithm’s robustness
Tx Simulink Verification
Platform
Off-line Simulation Platform
Rx SimulinkVerification Platforms
Performance Output
Data Acquisition
Data Acquisition
Tx Simulink Verification Platform
Channel Models
Rx Simulink Verification Platforms
p For ultra high-‐speed signal processing (e.g. WDM transmission) , the symbol rate could be >10Gs/s,where FPGA cannot support verification, so off-‐line verification is the most effective method.
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Future Worku Make full use of existing tools to improve the efficiency of fixed-‐point
algorithm development
p Consider using Fixed-‐Point Designer and automated tools to improve efficiency of
conversion and reduce the risk of human error.
u Improve simulation efficiency for large numbers of simulations
p Further improve efficiency for a single simulation run
p Consider and validate parallel simulations, and leverage computing capability of
multi-‐core computers / clusters.
u Improve off-‐line simulation capability
p Enhance verification through using prototype hardware with test equipment
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