PG24 DECOUPLING TALISE APG23 TALISE BPG22 TALISE APG21 ZYNQ POWERPG20 ZYNQ POWER
PG2 SOM INTERFACE
PG8 PS DDR4PG9 PS DDR4
PG16 HD BANK 88,89PG17 GTH TRANSCEIVERS
PG19 ZYNQ POWER
PG25 DECOUPLING TALISE BPG26 RX, ORX TALISE A
PG28 TX TALISE APG29 TX TALISE BPG30 HMC7044 JESD CLOCK GEN
PG32 POWER MONITRINGPG33 PL_0V85 REGULATORPG34 PS_0V85,1V8 REGULATORSPG35 MGTRAVCC, MGTRAVTT REGULATORSPG36 MGTAVCC, MGTAVTT REGULATORSPG37 3V3, 2V5 REGULATORSPG38 PL_DDR4, PS_DDR4 REGULATORSPG39 RF SWITCHHING REGULATORPG40 RF SWITCHHING REGULATORPG41 RF LDOS
PG31 DECOUPLING HMC7044
PG27 RX, ORX TALISE B
PG18 ZYNQ POWER
PG3 SOM INTERFACEPG4 ETHERNET PHY, USB PHYPG5 SD CARD, QSPI FLASH
PG15 HP BANK 68 - 71PG14 HP BANK 64 - 67PG13 PL DDR4 TERMINATIONS PG12 PL DDR4 PG11 PL DDR4 PG10 PS DDR4 TERMINATIONS
PG7 GTR REFERENCE CLOCK, GTR BANKPG6 BANK 500, 501, 502, 503
1 41
<User Define><User Define><User Define>
: Pitch-pitch StyleVendor StylePACKAGE : N/A-lead N/A N/A-family
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
no_template
ACodeID1:1
02_048949TBD
-
-
-
-
-
<PTD_ENGINEER>
-
-
-
-
REV
2REVISIONS
1
OWNED OR CONTROLLED BY ANALOG DEVICES.THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTSPURPOSE DETRIMENTAL TO THE INTERESTS OF ANALOG DEVICES. JP#USED IN FURNISHING INFORMATION TO OTHERS, OR FOR ANY OTHER
8
CONNECTORFUNCTIONCODE DEVICE
2
2
6JUMPER TABLE
4
7
5
A
3
DATE APPROVED
D
B
DESCRIPTION
34
OFFON
5
57
OEM PART# HANDLER
6
C
B
8
SOCKET OEMBK/BD SPEC.P.O SPEC.
A
1
RELAY CONTROL CHART
3 14
C
NOT TO BE REPRODUCED OR COPIED, IN WHOLE OR IN PART, ORTHIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC. IT IS
CHECKER
DESIGNER
PTD ENGINEER
TEST ENGINEER
DECIMALS
X.XXX +-0.005X.XX +-0.010
MASTER PROJECT TEMPLATE
TOLERANCES
+-1/32FRACTIONS
+-2SIZE
DDDD
SCHEMATIC
DRAWING NO.
SCALE CODE ID NO.SHEET OF
REV.
DA A
ENV C
L GSE
ODATE
ANGLES
UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE IN INCHES
TESTER TEMPLATE
TEMPLATE ENGINEER
HARDWARE SERVICES
HARDWARE SYSTEMS
COMPONENT ENGINEER
TEST PROCESS
HARDWARE RELEASE
* SEE ASSEMBLY INSTRUCTIONS
CONTROL
D
SOM SIGNAL INTERFACE
2 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
ASP-134486-01
ASP-134486-01
ASP-134486-01
ASP-134486-01ASP-134486-01 ASP-134486-01ASP-134486-01ASP-134486-01
ASP-134486-01ASP-134486-01
P2
P2 P2
P2 P2P2P2P2
P2 P2
VCC_PSBATT
SDA_ADM1166_3V3SCL_ADM1166_3V3
S_IN_P
PS_GTR_RX3_505_P
PS_GTR_TX0_505_P
PS_PROG_B
PS_GTR_RX1_505_NIO_L3N_AD13N_89
ETH_MD1_N
IO_L5N_HDGC_89
SDIO_CARRIER_CLK
JTAG_TDIJTAG_TCKSDIO_SELSDIO_CARRIER_CD
PS_MIO22_500_SPI1_SCLK_OUTPS_MIO21_500_SPI1_N_SS_OUT0
PS_ERROR_STATUS
VCCO_89
PS_MIO17_500_UART1_RXD
IO_L3P_AD13P_89
IO_L2N_AD14N_89IO_L1P_AD15P_89IO_L1N_AD15N_89
SDIO_CARRIER_DAT0
PS_MIO23_500_SPI1_MOSI
PS_MIO28_501_DPAUX_HOT_PLUG_DET
JTAG_TDO
PS_MIO34_501_UART0_RXDPS_MIO35_501_UART0_TXD
IO_L19P_T3L_N0_DBC_AD9P_65IO_L19N_T3L_N1_DBC_AD9N_65
IO_L24P_T3U_N10_67
IO_L15N_T2L_N5_AD11N_68IO_L15P_T2L_N4_AD11P_68
IO_L13P_T2L_N0_GC_QBC_68IO_L13N_T2L_N1_GC_QBC_68
IO_L9P_T1L_N4_AD12P_68
IO_L19N_T3L_N1_DBC_AD9N_67IO_L19P_T3L_N0_DBC_AD9P_67
IO_L14N_T2L_N3_GC_67IO_L14P_T2L_N2_GC_67
IO_L8N_T1L_N3_AD5N_67IO_L8P_T1L_N2_AD5P_67
IO_L9N_T1L_N5_AD12N_65
IO_L7P_T1L_N0_QBC_AD13P_65IO_L7N_T1L_N1_QBC_AD13N_65
IO_L17P_T2U_N8_AD10P_67
IO_L17N_T2U_N9_AD10N_65VCCO_67
IO_L17P_T2U_N8_AD10P_65
VREF_67VREF_65
IO_L17N_T2U_N9_AD10N_67
IO_L12N_T1U_N11_GC_67
IO_L5N_T0U_N9_AD14N_67IO_L5P_T0U_N8_AD14P_67
IO_L24N_T3U_N11_65
IO_L1N_T0L_N1_DBC_67
IO_L10N_T1U_N7_QBC_AD4N_65IO_L10P_T1U_N6_QBC_AD4P_65
IO_L2P_T0L_N2_65
IO_L1P_T0L_N0_DBC_67
IO_L9P_T1L_N4_AD12P_65
IO_L12N_T1U_N11_GC_65
VCCO_68
IO_L2P_AD14P_89
IO_L4N_AD12N_89IO_L4P_AD12P_89
IO_L5P_HDGC_89IO_L6N_HDGC_89
IO_L16P_T2U_N6_QBC_AD3P_68IO_L16N_T2U_N7_QBC_AD3N_68
IO_L6P_HDGC_89
VREF_68
PS_MIO77_502_ETH_MDIOPS_MIO18_500_SPI1_MISO
PG_SOM
PS_SRST_B
PG_ALL
VIN
IO_L20N_T3L_N3_AD1N_68
IO_L6P_T0U_N10_AD6P_68
IO_L21N_T3L_N5_AD8N_68
IO_L1N_T0L_N1_DBC_68
IO_L22P_T3U_N6_DBC_AD0P_65
IO_L11P_T1U_N8_GC_65IO_L11N_T1U_N9_GC_65
IO_L1P_T0L_N0_DBC_65IO_L1N_T0L_N1_DBC_65
IO_L4N_T0U_N7_DBC_AD7N_67IO_L14N_T2L_N3_GC_65
IO_L12P_T1U_N10_GC_67
IO_L2N_T0L_N3_67IO_L12P_T1U_N10_GC_65
IO_T2U_N12_65
IO_L20N_T3L_N3_AD1N_65
IO_L13N_T2L_N1_GC_QBC_67
SDIO_CARRIER_DAT1
IO_L2P_T0L_N2_67
IO_L24N_T3U_N11_67
IO_L9N_T1L_N5_AD12N_68
1V8
1V8
3V3
SDIO_CARRIER_DAT3
IO_L20P_T3L_N2_AD1P_68
IO_L3N_T0L_N5_AD15N_68
IO_L6N_T0U_N11_AD6N_68
PS_MIO76_502_ETH_MDC
PS_MIO19_500_SPI1_N_SS_OUT2
PS_MIO37_501
PS_MIO33_501_I2C1_SDA
PS_MIO30_501_DPAUX_DATA_INPS_MIO29_501_DPAUX_DATA_OE
PS_MIO38_501
SDIO_CARRIER_CMD
SDIO_CARRIER_DAT2
PS_MIO27_501_DPAUX_DATA_OUT
PS_MIO36_501
PS_MIO31_501
PS_MIO26_501_ID
PS_MIO16_500_UART1_TXDPS_MIO15_500_I2C0_SDA
PS_MIO20_500_SPI1_N_SS_OUT1
PS_MIO32_501_I2C1_SCL
JTAG_TMS
PS_MIO14_500_I2C0_SCL
IO_L21N_T3L_N5_AD8N_65
IO_L22N_T3U_N7_DBC_AD0N_65
IO_L7P_T1L_N0_QBC_AD13P_67IO_L7N_T1L_N1_QBC_AD13N_67
IO_L6N_T0U_N11_AD6N_67IO_L6P_T0U_N10_AD6P_67
IO_L8P_T1L_N2_AD5P_65IO_L8N_T1L_N3_AD5N_65
IO_L4P_T0U_N6_DBC_AD7P_65IO_L4N_T0U_N7_DBC_AD7N_65
IO_T2U_N12_68IO_T3U_N12_68
IO_L5P_T0U_N8_AD14P_68IO_L5N_T0U_N9_AD14N_68
IO_L22N_T3U_N7_DBC_AD0N_67IO_L22P_T3U_N6_DBC_AD0P_67
IO_L4N_T0U_N7_DBC_AD7N_68IO_L4P_T0U_N6_DBC_AD7P_68
IO_L11P_T1U_N8_GC_67
IO_L15N_T2L_N5_AD11N_65IO_L15P_T2L_N4_AD11P_65
IO_L20P_T3L_N2_AD1P_67IO_L20N_T3L_N3_AD1N_67
IO_L11N_T1U_N9_GC_67
IO_L19P_T3L_N0_DBC_AD9P_68
IO_L23P_T3U_N8_68IO_L23N_T3U_N9_68
IO_L19N_T3L_N1_DBC_AD9N_68
IO_L6P_T0U_N10_AD6P_65
IO_L21P_T3L_N4_AD8P_67
IO_L3P_T0L_N4_AD15P_65IO_L3N_T0L_N5_AD15N_65
IO_L13P_T2L_N0_GC_QBC_65IO_L13N_T2L_N1_GC_QBC_65
IO_L3P_T0L_N4_AD15P_67IO_L3N_T0L_N5_AD15N_67
IO_T3U_N12_67IO_T2U_N12_67
IO_L23P_T3U_N8_I2C_SCLK_65
IO_L11N_T1U_N9_GC_68
IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65
IO_L10P_T1U_N6_QBC_AD4P_67IO_L10N_T1U_N7_QBC_AD4N_67
IO_L15P_T2L_N4_AD11P_67IO_L15N_T2L_N5_AD11N_67
IO_L21N_T3L_N5_AD8N_67
IO_L16P_T2U_N6_QBC_AD3P_67IO_L16N_T2U_N7_QBC_AD3N_67
IO_L8N_T1L_N3_AD5N_68IO_L8P_T1L_N2_AD5P_68
IO_L11P_T1U_N8_GC_68
IO_L14N_T2L_N3_GC_68
IO_L24N_T3U_N11_68
IO_L14P_T2L_N2_GC_68
IO_L24P_T3U_N10_68
IO_T1U_N12_68
IO_T3U_N12_PERSTN0_65
IO_L5N_T0U_N9_AD14N_65
USB_OTG_P
ETH_MD4_NETH_MD4_P
PS_GTR_RX2_505_PPS_GTR_RX2_505_N
IO_L18P_T2U_N10_AD2P_68
PS_MODE3_503
IO_L17N_T2U_N9_AD10N_68
IO_L10N_T1U_N7_QBC_AD4N_68
IO_T0U_N12_VRP_67
IO_L14P_T2L_N2_GC_65IO_L4P_T0U_N6_DBC_AD7P_67
IO_L16P_T2U_N6_QBC_AD3P_65IO_L16N_T2U_N7_QBC_AD3N_65
IO_L23P_T3U_N8_67IO_L23N_T3U_N9_67
IO_L18P_T2U_N10_AD2P_67IO_L18N_T2U_N11_AD2N_67
IO_L7N_T1L_N1_QBC_AD13N_68IO_L7P_T1L_N0_QBC_AD13P_68
IO_L12P_T1U_N10_GC_68IO_L12N_T1U_N11_GC_68
IO_L10P_T1U_N6_QBC_AD4P_68
IO_L22P_T3U_N6_DBC_AD0P_68IO_L22N_T3U_N7_DBC_AD0N_68
IO_L2N_T0L_N3_68
IO_L1P_T0L_N0_DBC_68
IO_L21P_T3L_N4_AD8P_65
IO_L24P_T3U_N10_65
IO_L6N_T0U_N11_AD6N_65
IO_L5P_T0U_N8_AD14P_65
IO_L17P_T2U_N8_AD10P_68
IO_L21P_T3L_N4_AD8P_68
IO_L2P_T0L_N2_68
IO_T0U_N12_VRP_68IO_L18N_T2U_N11_AD2N_68
IO_T1U_N12_67
VCCO_65
IO_L2N_T0L_N3_65
IO_L9N_T1L_N5_AD12N_67
IO_L20P_T3L_N2_AD1P_65
IO_L13P_T2L_N0_GC_QBC_67
IO_L9P_T1L_N4_AD12P_67
IO_T1U_N12_SMBALERT_65IO_T0U_N12_VRP_65
IO_L3P_T0L_N4_AD15P_68
IO_L18P_T2U_N10_AD2P_65IO_L18N_T2U_N11_AD2N_65
PS_DONEPS_INIT_B
PS_ERROR_OUTETH_PHY_LED1
ETH_MD3_P
PS_GTR_RX3_505_N
ETH_MD2_P
PS_GTR_RX1_505_P
ETH_MD2_N
PS_GTR_RX0_505_P
ETH_PHY_LED0
ETH_MD3_N
S_OUT_NS_OUT_P
S_IN_N
PS_MODE0_503
USB_OTG_N
USB_VBUS_OTG
PS_MODE2_503PS_MODE1_503
PS_GTR_TX0_505_N
PS_GTR_TX1_505_P
PS_GTR_TX3_505_N
PS_GTR_TX2_505_N
PS_GTR_TX1_505_N
PS_GTR_TX2_505_P
PS_GTR_TX3_505_P
USB_OTG_CPEN
PS_GTR_RX0_505_N
ETH_MD1_P
USB_ID
PS_GTR_REFCLK0_505_PPS_GTR_REFCLK0_505_N
C37
B30
A19
C27
C30C31
C34
C10
C8 B8C9
D14D13
D11
C16
C13C14
D25
C20
B38
D20
D24D23D22
D5D6
D8
K24 J24J25
J27J28J29J30J31
K5K4
H17H16H15
G9
H20
K8
D21
C1
D10D9
C7
D2
C15
C11
D15
D19
D16
C12
D4
C22
C19
C35
C29
C38
C2C3C4C5C6
C17C18
C21
C23C24C25C26
C28
C32C33
C36
C39C40
D18
K38
D26
B16
K14K15
K13
K16K17
K12K11K10K9
K7K6
K18
H2
D1
B15
D27
B1
F9
F7F6
H3
D29D30
F39
F31
B11
E35
F38E37
E34
F21
E4
E40E39E38
E36
E33E32E31E30E29E28E27E26E25E24E23E22E21E20E19E18E17E16E15E14
E12E11E10E9E8E7E6E5
E3E2E1
E13
G18
F33
F14F13
F28
F30
F40
F37F36F35F34
F32
F29
F27F26F25F24F23F22
F20F19F18F17F16F15
F12F11F10
F8
F5F4F3F2F1
H10H9
G16
G4
G1
G10
G8
G14
G40G39G38G37G36G35G34G33G32G31G30G29G28G27G26G25G24G23G22G21G20G19
G17
G15
G13G12G11
G7G6G5
G3G2
H40H39H38H37H36H35H34H33H32H31H30H29H28H27H26H25H24H23H22H21
H19H18
H14H13H12H11
H8H7H6H5H4
H1
K28
J16J17J18
J8J9
J12
J14
J11
J40J39J38J37J36J35J34J33J32
J26
J23J22J21
J19
J15
J13
J10
J7J6J5J4J3J2J1
J20
K40K39
K37K36K35K34K33K32K31K30K29
K27K26K25
K23K22K21K20K19
K3K2K1
A25A26
A30
B2B3B4B5B6B7
B9B10
B12B13B14
B17B18B19B20B21B22B23B24B25B26B27B28B29
B31B32B33B34B35B36B37
B39B40
D3
D7
D12
D17
D28
D31D32D33D34D35D36D37D38D39D40
A1
A3A4A5A6A7A8A9A10A11A12A13A14A15A16A17A18
A20A21A22A23A24
A27A28A29
A31A32A33A34A35A36A37A38A39A40
A2
GNDGND
GND
GND
GNDGND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
SOM SIGNAL INTERFACE
3 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
ASP-134486-01 ASP-134486-01
ASP-134486-01ASP-134486-01 ASP-134486-01 ASP-134486-01ASP-134486-01
ASP-134486-01
ASP-134486-01 ASP-134486-01
P1P1P1
P1P1P1P1P1P1
P1GPIO_18_B
GPIO_17_BGPIO_16_BGPIO_15_B
RX1_ENABLE_B
GPIO_13_B
GPIO_10_B
GPIO_6_B
GPIO_2_BGPIO_1_BGPIO_0_B
TX2_ENABLE_B
IO_L12P_T1U_N10_GC_64IO_L12N_T1U_N11_GC_64IO_L13P_T2L_N0_GC_QBC_64
IO_L20P_T3L_N2_AD1P_66
GPIO_17_A
GPIO_18_ARX1_ENABLE_A
PWR_FAULT1PWR_FAULT2
GPIO_3P3_10_BGPIO_8_B
CLKIN0_HMC7044_NCLKIN0_HMC7044_P
CLKIN1_HMC7044_NCLKIN1_HMC7044_P
CLKIN3_HMC7044_PCLKIN3_HMC7044_N
IO_L19N_T3L_N1_DBC_AD9N_66IO_L19P_T3L_N0_DBC_AD9P_66
IO_L13N_T2L_N1_GC_QBC_64IO_L14P_T2L_N2_GC_64IO_L14N_T2L_N3_GC_64
TX1_ENABLE_B
RX2_ENABLE_A
TX2_ENABLE_ATX1_ENABLE_A
RX2_ENABLE_B
GPIO_7_B
VDDA3P3GPIO_3P3_3_BGPIO_3P3_4_B
GPIO_3P3_6_BGPIO_3P3_5_B
GPIO_16_AGPIO_15_AGPIO_14_AGPIO_13_AGPIO_12_AGPIO_11_AGPIO_10_AGPIO_9_AGPIO_8_AGPIO_7_AGPIO_6_AGPIO_5_AGPIO_4_AGPIO_3_AGPIO_2_AGPIO_1_AGPIO_0_A
1V8
GPIO_3P3_11_B
GPIO_3P3_8_AGPIO_3P3_7_A
GPIO_3P3_4_A
GPIO_3P3_7_BGPIO_3P3_8_BGPIO_3P3_9_B
AUXADC_3_A
AUXADC_0_ARF_SYNTH_VTUNE_A
AUXADC_2_AAUXADC_1_A
AUX_SYNTH_VTUNE_AAUX_SYNTH_OUT_A
GPIO_3P3_0_A
GPIO_3P3_3_AGPIO_3P3_2_A
GPIO_3P3_1_A
RF_SYNTH_VTUNE_BAUX_SYNTH_VTUNE_B
AUXADC_3_B
AUXADC_1_BAUXADC_0_B
AUXADC_2_B
GPIO_3P3_2_BGPIO_3P3_1_B
AUX_SYNTH_OUT_B
GPIO_3P3_0_B
MGTHRXP3_229
MGTREFCLK1N_228
MGTHTXN3_229MGTHTXP3_229
MGTHRXP1_229MGTHRXN1_229
MGTREFCLK1P_228
MGTHRXN1_228
MGTHRXN3_228
MGTHRXN2_229
GPIO_3P3_11_A
MGTHRXP0_229MGTHRXN0_229
MGTHRXN3_229
MGTHRXP3_228
MGTHTXN0_228
GPIO_5_B
MGTHRXP0_227MGTHRXN0_227
MGTHRXP2_226MGTHRXN2_226
MGTHTXP1_229
MGTHRXP2_229
MGTHTXN2_228
MGTHRXN2_228
MGTHTXN1_229
MGTHTXN1_227
MGTHRXP3_226MGTHRXN3_226
MGTHRXP0_226MGTHRXN0_226
MGTHTXP3_227
MGTREFCLK0N_226
MGTREFCLK0P_227MGTREFCLK0N_227
MGTREFCLK0P_226
MGTHTXN3_227
MGTHTXP1_226
MGTHTXP1_228
MGTREFCLK1P_227
MGTHTXN2_227MGTHTXP2_227
MGTHTXN1_228
MGTREFCLK1P_229
MGTREFCLK0P_228MGTREFCLK0N_228
MGTHTXP2_226
MGTHRXN2_227
MGTHTXN3_228
MGTREFCLK1N_229
MGTHTXP0_228
MGTHRXP2_228
MGTREFCLK1N_226
MGTHTXN3_226
MGTHTXP0_226
MGTHTXN0_227
MGTREFCLK0P_225MGTREFCLK0N_225
MGTHRXN3_224MGTHRXP3_224
MGTHRXP0_228MGTHRXN0_228
MGTHRXP1_226
MGTHRXP1_227
MGTHRXN1_226
MGTHRXN1_227
MGTHRXN2_225MGTHRXP2_225
MGTHRXN3_225MGTHRXP3_225
MGTHRXP0_225MGTHRXN0_225
MGTHRXP1_224MGTHRXN1_224
MGTHTXN0_226
MGTHTXP1_225MGTHTXN1_225
MGTHTXP2_224MGTHTXN2_224
MGTHRXN1_225MGTHRXP1_225
MGTHRXP2_224MGTHRXN2_224
MGTHTXP2_225
MGTREFCLK0P_224
MGTHTXN1_224MGTHTXP1_224
MGTHTXN3_224
MGTHRXP0_224MGTHRXN0_224
MGTHTXP3_224
MGTREFCLK1P_225
MGTHTXN1_226
MGTHTXN2_225
MGTHTXP0_224
MGTHTXP1_227
MGTREFCLK1N_225
MGTHTXN3_225
MGTHTXP0_225
MGTHTXP3_225
MGTHTXN0_225
MGTHTXN0_229
MGTHTXN2_229
MGTHTXP3_228
MGTHTXP0_229
MGTREFCLK1N_227
MGTHTXN2_226
MGTHTXN0_224MGTREFCLK1P_224
MGTREFCLK0N_224
SPI_MOSISPI_MISOSPI_CLK
SYNC_HMC7044
GPIO_14_B
GPIO_12_BGPIO_11_B
GPIO_4_BGPIO_3_B
GPIO_9_B
MGTHTXP2_228
MGTREFCLK1N_224
MGTREFCLK1P_226
MGTHTXP3_226
MGTHRXP1_228
MGTREFCLK0P_229MGTREFCLK0N_229
MGTHTXP2_229
1V8
GPIO_3P3_5_AGPIO_3P3_6_A
GPIO_3P3_9_AGPIO_3P3_10_A
MGTHTXP0_227
MGTHRXN3_227MGTHRXP3_227MGTHRXP2_227
B38A39
D9D10
D20
D13D12
D17D18D19
D11
D23D24D25
D21D22
D15
A32
A29A30
A28
A34A35
A1A2
B1
B3
B19B18
B4
B2
C36
C32
C23C24C25
C20C21C22
C8C7C6
C15C16
C18
C11C12
B26B25
B27
B30
D7
C40C39
B24B23B22
C35
C5
C3
C1
D31D30
C31
D26
K19K20
J27
B6
B15
G38G39
H14H13
H8
H28
G22
G15
G8
G1
F28F27
F25
F22F21F20
B11
C28
D36
A9
F35
A3
E40E39
E37E36
F39
G33
H31H30
H26H27
J36J35J34
J32
D34D33
D37D38D39
D32
C2
F31
G29
H36
J30
K35K34
K32K31K30K29K28K27
J31
K24
G27
F24
E17E16
F18
G20G19
H22
J19 H19
J23
J25
G14
G12
G21
G17G16
H24
H29
J18
J21J22K22
E38
E35E34E33E32E31E30E29E28E27E26E25E24E23E22E21E20E19E18
E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1
F19
H12
H6
F12F13F14
F16F15
G13
H11H10H9
H7
K11J12
J17J16
J4
K7
K17
K12K13
K9
G7
G2
J14J13
K3K4K5
K18
K6
K8
K14
F33
G30
J24
F17
H20
H18
C26
B13
C4
B12
B14C14
C17
C13
C30
B16B17
B34
A25
A23
D4D5
D1
D35
D2D3
D6
D8
D14
D16
D28D29
D40
D27
B31
F38
F1F2F3F4F5F6F7F8F9F10F11
F23
F26
F29F30
F32
F34
F36F37
G4
G6
G10
G5
G9
G11
G18
G23G24G25G26
G28
G31G32
G34G35G36
G40
G37
H33
H21
H5
H1H2H3H4
H15H16H17
H23
H25
H32
H34H35
H37H38H39H40
J5
K2
J6
J1J2J3
J7J8J9
J10J11
J15
J20
J26
J28J29
J33
J37J38J39J40
K1
K10
K15K16
K21
K23
K25K26
K33
K36K37K38K39K40
B40
B35B36
A40
A38A37A36
A33
A31
A27A26
A24
A22A21A20A19A18A17A16A15A14A13A12A11A10
A8A7A6A5A4
B39
B37
B33B32
B29B28
B21B20
B10B9B8B7
B5
C38C37
C34C33
C29
C27
C19
C10C9
G3
F40
GNDGNDGNDGND
GNDGNDGNDGNDGNDGND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
ETHERNET PHY
STANDBY - 1 OR OPEN: OSCILLATION
CONNECTED TO GEM 3: MIO64...75
CONNECTED TO USB0 : MIO52...63
PHY1
USB PHY
4 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
1K
220
BSS138LT1G
1K
1K
BSS138LT1G
1UF
27PF
10
0.1UF
0.1UF
1UF10UF
4.7UF
51
4.7UF
4.7UF
51
1UF
0.1UF
0.1UF 0.1UF
0.1UF 0.1UF
0.1UF 0.1UF
0.1UF 0.1UF 0.1UF
24MEGHZ
L0805
NC7SZ08FHX
100OHM
L0805
100OHM
100OHM
L0805
USB3320C-EZK
0.1UF
NC7SZ08FHX
2.2UF
88E1512-A0-NNP2I000
0.1UF
0.1UF 4.7UF
0.1UF
4127PF
4.7UF
25MEGHZ
0.1UF
8.06K
4.7K
4.99K
0
0
220
39
DNI0
1UF0.1UF0.1UF0.1UF
BSS138LT1G
1K
BSS138LT1GR66
R69
Q4R67
R65
Q2
C201
C196
C191
U32
C214C211
C217C215
C219C216C213C207C205
C220
C222C210C209
E5
E6
C193
U33
C192
U7
Y2
C194
C206 C208
C218
E4
Y3
C223
C212
C198
C224
C203 C204
C221
U34
R63
R64
R59
R61
R70
R62
R60
C195 C197 C199 C200
R58
Q5
Q3
R68
PHY1_LED_0
ETH_PHY_LED1
PHY1_LED_1
PHY1_VDD_3V3
USB_OTG_CPEN
PS_MIO58_502_USB0_STP
ETH_MD1_PETH_MD1_NETH_MD2_P
PS_MIO61_502_USB0_D5
PHY1_LED_0PHY1_LED_1
PS_MIO76_502_ETH_MDCPHY1_DVDD_1V0
S_OUT_N
USB_ID
PS_MIO26_501_ID
1V8
PHY1_1V8
1V8
ETH_MD3_P
PS_MIO71_502_ETH3_RX_D0PS_MIO72_502_ETH3_RX_D1PS_MIO73_502_ETH3_RX_D2PS_MIO74_502_ETH3_RX_D3
ETH_MD2_N
ETH_PHY_LED0
PS_MIO25_500_ETH3_RESET_B
ETH_MD4_PETH_MD3_N
1V8
PG_ALL
PS_MIO70_502_ETH3_RX_CLK
PS_MIO57_502_USB0_D1
3V3
PHY1_AVDD_3V3
1V8
1V8
PS_MIO64_502_ETH3_TX_CLK
PS_MIO66_502_ETH3_TX_D1PS_MIO67_502_ETH3_TX_D2
PS_MIO65_502_ETH3_TX_D0
PHY1_DVDD_1V0
PG_ALL
1V8
PHY1_AVDD_3V3
PHY1_1V8
PHY1_1V8 PHY1_VDD_3V3
PHY1_AVDD_1V8
PS_MIO13_500_USB0_RESET_B
PS_MIO63_502_USB0_D7PS_MIO55_502_USB0_NXT
USB_OTG_NUSB_OTG_P
USB_VBUS_OTG3V3
S_OUT_P
PHY1_AVDD_1V8_OUT
PHY1_AVDD_1V8_OUT
PHY1_AVDD_1V8
1V8
PHY1_AVDD_3V3
PHY1_VDD_3V3
PHY1_VDD_3V3
PS_MIO75_502_ETH3_RX_CTL
PHY1_DVDD_1V0
PS_MIO69_502_ETH3_TX_CTL
PS_MIO68_502_ETH3_TX_D3
PS_MIO60_502_USB0_D4PS_MIO59_502_USB0_D3PS_MIO54_502_USB0_D2
3V3
PS_MIO77_502_ETH_MDIO
PHY1_AVDD_1V8
S_IN_PS_IN_N
PHY1_AVDD_1V8
PS_MIO56_502_USB0_D0
PS_MIO52_502_USB0_CLKPS_MIO53_502_USB0_DIR
PS_MIO62_502_USB0_D6
ETH_MD4_N
PHY1_VDD_3V3
15
3
19
25
3310
52 49
11
55 54 5056 53
45
2
48 47 45 4446
30
16
41
36
PAD
18 22 28
8
17 21 27
7
121314
3231
40
6
15
935
2520
39
2619
21
21
21
31
42
22
2927
1411
826
2
23
18
31
131097654
1
4
1 3
2 12
24
17
21
PAD
43
42
51
3
29
24
34
3738
1
16
32302820
23
GND
GND
PINSPARE
GND
GND
GNDGND
GND
GND
GND
PAD
TX_C
TRL
TXD(
3)TX
D(2)
TX_C
LKVD
DOTX
D(1)
TXD(
0)VD
DORX
D(3)
RXD(
2)RX
_CLK
RXD(
1)RX
D(0)
RX_C
TRL
DVDDREGCAP2
DVDD_OUTAVDD18_OUT
AVDD18REGCAP1
REG_INAVDDC18XTAL_IN
XTAL_OUTHSDACPHSDACN
RSETTSTPT
MDI
P(0)
MDI
N(0)
AVDD
18AV
DD33
MDI
P(1)
MDI
N(1)
MDI
P(2)
MDI
N(2)
AVDD
33AV
DD18
MDI
P(3)
MDI
N(3)
RESE
TNCO
NFIG
LED(0)LED(1)LED(2)/INTNVDDOVDDO_SELCLK125MDIOMDCDVDDS_OUTNS_OUTPAVDD18S_INNS_INP
GND
GND
GNDGNDGND
PINSPARE
PINSPARE
PINSPARE
PINSPARE
PINSPARE
GND
GND
GND
GND
VCC
NC
Y
GNDBA
PINSPARE
GND_FLAG
VDDI
O
DIR
VDD1
8
STP
VDD1
8
RESETB
REFCLK
XO
RBIAS
IDVBUSVBAT
VDD3
3
DMDP
CPEN
SPK_RSPK_L
REFSEL2
DATA7
N/C
REFSEL1
DATA6DATA5
REFSEL0
DATA4DATA3DATA2DATA1DATA0
NXT
CLKOUT
GND
GND
PINSPARE
GNDPIN
SPARE
GND
GND
VCC
NC
Y
GNDBA
GND
GND
VDDSTANDBY
GNDOUTPUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
CONTROLLED BY CARRIER:
SDIO_SEL = OPEN FOR SOM SDSDIO_SEL = GND FOR CARRIER SD
ACTIVE "0"
QSPI FLASH
SD CARD
DAT1
VSS
CD/DAT3
VDD
DAT0
CLK
CMD
DAT2 ZYNQ ULTRASCALE SUPPORTS V3.0 (104MBYTE/S). A 3.0 COMPLIANT TRANSLATOR NEEDS TO BE USED
5 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
ADG849YKSZ
FSA1208BQX
10K
FSA1208BQX
0.1UF
10K 10K
0.1UF
DM3BT-DSF-PEJS
4.7K
0.1UF
MT25QU512ABB1EW9-0SITMT25QU512ABB1EW9-0SIT
IP4856CX25/CZ
0.1UF 0.1UF
0.1UF
1UF 4.7UF
1000PF
1UF
1000PF
0.1UF
4.7K
0
4.7K
4.7K
4.7K4.7K4.7K
4.7K
10K
0 DNI
P3
R74
U37
R75
C227C226U35
R72
R71
C228
U36
U8U9
C231
U10
C235C232
C229
C225
C233 C234
C236
R81
R419
R76
R73
R77R80R79
R78
R82
R418
C230
SDIO_SOM_SEL
SDIO_SEL
SDIO_CARRIER_DAT1SDIO_CARRIER_DAT0
SDIO_SOM_CD
SDIO_CARRIER_CMDSDIO_CARRIER_DAT3
PS_MIO49_501_SDIO_DAT3PS_MIO48_501_SDIO_DAT2PS_MIO47_501_SDIO_DAT1PS_MIO46_501_SDIO_DAT0
PS_MIO42_501_SDIO_DIR_DAT1_3PS_MIO41_501_SDIO_DIR_DAT0PS_MIO50_501_SDIO_CMD
PS_MIO45_501_SDIO_DETECT
SDIO_CARRIER_CD
SDIO_CARRIER_SEL
1V8
1V8
SDIO_CARRIER_CLK
1V8
SDIO_SOM_CMDSDIO_SOM_DAT3SDIO_SOM_DAT2
SDIO_SOM_CLK
SDIO_SOM_DAT0
1V8
SDIO_SOM_DAT1
SDIO_SOM_DAT1
3V3
PS_MIO07_500_QSPI_UPR_SS_B
1V8
PS_MIO10_500_QSPI_UPR_IO2PS_MIO11_500_QSPI_UPR_IO3
1V8
PS_MIO12_500_QSPI_UPR_SCLKPS_MIO08_500_QSPI_UPR_IO0PS_MIO09_500_QSPI_UPR_IO1PS_MIO05_500_QSPI_LWR_SS_B
1V8
PS_MIO04_500_QSPI_LWR_IO0PS_MIO01_500_QSPI_LWR_IO1
1V8
PS_MIO02_500_QSPI_LWR_IO2
1V8
PS_MIO03_500_QSPI_LWR_IO3
3V3
1V8
SDIO_DAT2
3V3
SDIO_SOM_DAT0
3V3
SDIO_SOM_DAT2SDIO_SOM_DAT3SDIO_SOM_CMD
1V8
SDIO_SOM_CD
SDIO_DAT0SDIO_DAT1
SDIO_DAT3
1V8
SDIO_DAT3
PS_MIO51_501_SDIO_CLK
3V3
SDIO_CLKSDIO_CMD
PS_MIO39_501_SDIO_SELSDIO_CLKSDIO_CMD
SDIO_DAT0SDIO_DAT1
PS_MIO40_501_SDIO_DIR_CMD
PS_MIO45_501_SDIO_DETECT
SDIO_SOM_SEL
SDIO_DAT2
PS_MIO00_500_QSPI_LWR_SCLK
SDIO_SOM_CLK
SDIO_CARRIER_DAT2
3V3
SDIO_CARRIER_SEL
8
1516
19
18
SH2
A
6
8
5
SH1
SH3
1
7
4
SH4
B
23
7
652
7
PAD
1
8
4
3 652
7
PAD
1
8
4
3
D3
E2
C1C5
D2
D4
D1 D5E1 E5A1 A5B1 B5
A3E3
A2
C2
C3
B2
B3
B4
C4
A4
E4
23456
89
19
171615141312
1011
20
1
34567
9
1817
141312
PAD10
20
1
11
PAD
2
SHLDPINS
GND
GND
GND
GND
GND
DS2
S1
GND
VDD
IN
PAD
OE_N
B1B2B3B4B5B6B7B8
NC GND
A8A7A6A5A4A3A2A1
VCC
GND
GND
GND
GND
PAD
OE_N
B1B2B3B4B5B6B7B8
NC GND
A8A7A6A5A4A3A2A1
VCC
GND
GND
GND
GNDGND
GND
DIR_1_3
VCCA
DATA3_SD
VLDO
ENABLE
DATA1_SD
GND
VSD_REFSEL
DATA3_HDATA2_SD
VSUPPLY
DIR_0
DIR_CMD
DATA2_H
WP
CLK_FB
DATA1_HDATA0_SD
CMD_SD
CD
CMD_H
DATA0_H
CLK_SDCLK_IN
GND
GND
PAD
VCC
HOLD#/DQ3
CDQ0
VSS
W#/DQ2DQ1
S#PAD
VCC
HOLD#/DQ3
CDQ0
VSS
W#/DQ2DQ1
S#
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
BANK 503
ASSERTED AFTER PG_SOM AND PG_CARRIER
BOOT AND CONFIGURATION
PG_ALL FROM CARRIER, OPEN DRAIN
PS BANK 503 1V8
PS BANK 500 1V8
BANK 502BANK 501BANK 500
PS BANK 502 1V8
PULL-DOWN ON SD WP FOR WRITE ENABLE
PS BANK 501 1V8
KEEP MIO6 UNCONNECTED FOR THE LOOPBACK FEATURE
6 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
100100
30
XCZU11EG-1FFVF1517I
22PF
4.7MEG
20
10KDNI
39
18
30
30
30
30
30
30
30
30
30
30
30
30
30
30
1K
4.7K4.7K
4.7K4.7K4.7K4.7K
4.7K4.7K4.7K4.7K4.7K
22
4.7K
17
10KDNI
16
XCZU11EG-1FFVF1517I
0.032768MEGHZ
22PF
33PF
33.333MEGHZ
0.1UF
XCZU11EG-1FFVF1517IXCZU11EG-1FFVF1517I
100UF100UF 100UF 100UF 100UF100UF 100UF 100UF
0.1UF
4.7UF4.7UF 4.7UF4.7UF
R558R557
R16R7
R411
U21
C1094
R4R2
R3
R9
R8R13
R12
R11
R20
R19
R17
R18
R24
R23
R22
R21
R10
R15R14
R415R414R413R412
R410R409R408R407R6R5
R1
C1095
Y4
C7 Y7
C2
U21U21
C1 C5 C9 C12C3 C6 C10 C13C4 C8 C11 C14
C15
U21
I2C0_SDAPS_MIO15_500_I2C0_SDAI2C0_SCLPS_MIO14_500_I2C0_SCL
PS_MIO52_502_USB0_CLKPS_MIO53_502_USB0_DIR
PS_MIO42_501_SDIO_DIR_DAT1_3PS_MIO41_501_SDIO_DIR_DAT0PS_MIO40_501_SDIO_DIR_CMDPS_MIO39_501_SDIO_SEL
PS_MIO02_500_QSPI_LWR_IO2
PS_ERROR_OUT
PS_MODE2_503
PS_MIO16_500_UART1_TXDPS_MIO15_500_I2C0_SDAPS_MIO14_500_I2C0_SCLPS_MIO13_500_USB0_RESET_BPS_MIO12_500_QSPI_UPR_SCLKPS_MIO11_500_QSPI_UPR_IO3PS_MIO10_500_QSPI_UPR_IO2
PS_MIO20_500_SPI1_N_SS_OUT1
PS_MIO22_500_SPI1_SCLK_OUTPS_MIO19_500_SPI1_N_SS_OUT2
PS_MIO01_500_QSPI_LWR_IO1PS_MIO00_500_QSPI_LWR_SCLK
PS_MIO25_500_ETH3_RESET_BPS_MIO24_500_AD9542_RESET_BPS_MIO23_500_SPI1_MOSI
PS_MIO21_500_SPI1_N_SS_OUT0
PS_MIO64_502_ETH3_TX_CLKPS_MIO63_502_USB0_D7
PS_MIO49_501_SDIO_DAT3PS_MIO50_501_SDIO_CMDPS_MIO51_501_SDIO_CLK
PS_MIO08_500_QSPI_UPR_IO0PS_MIO07_500_QSPI_UPR_SS_B
PS_MIO54_502_USB0_D2
PS_MIO03_500_QSPI_LWR_IO3
PS_MIO05_500_QSPI_LWR_SS_BPS_MIO04_500_QSPI_LWR_IO0
PS_MIO09_500_QSPI_UPR_IO1
PS_MIO17_500_UART1_RXDPS_MIO18_500_SPI1_MISO
PS_MODE3_503
PS_MODE0_503
JTAG_TDO
PS_ERROR_STATUS
1V8
JTAG_TCKJTAG_TDIJTAG_TMS
PS_PROG_BPG_ALL
1V8
PS_SRST_B
1V8
PS_MODE1_503
PS_DONE
1V8
PS_INIT_B
1V8
1V8
PS_MIO34_501_UART0_RXD
PS_MIO27_501_DPAUX_DATA_OUT
PS_MIO46_501_SDIO_DAT0
PS_MIO48_501_SDIO_DAT2PS_MIO47_501_SDIO_DAT1
PS_MIO61_502_USB0_D5
PS_MIO57_502_USB0_D1
PS_MIO59_502_USB0_D3
PS_MIO62_502_USB0_D6
PS_MIO60_502_USB0_D4
PS_MIO58_502_USB0_STP
PS_MIO56_502_USB0_D0
PS_MIO77_502_ETH_MDIOPS_MIO76_502_ETH_MDCPS_MIO75_502_ETH3_RX_CTLPS_MIO74_502_ETH3_RX_D3PS_MIO73_502_ETH3_RX_D2PS_MIO72_502_ETH3_RX_D1PS_MIO71_502_ETH3_RX_D0PS_MIO70_502_ETH3_RX_CLKPS_MIO69_502_ETH3_TX_CTLPS_MIO68_502_ETH3_TX_D3PS_MIO67_502_ETH3_TX_D2PS_MIO66_502_ETH3_TX_D1PS_MIO65_502_ETH3_TX_D0
PS_MIO55_502_USB0_NXT
PS_MIO45_501_SDIO_DETECT
PS_MIO38_501PS_MIO37_501PS_MIO36_501PS_MIO35_501_UART0_TXD
PS_MIO33_501_I2C1_SDAPS_MIO32_501_I2C1_SCLPS_MIO31_501PS_MIO30_501_DPAUX_DATA_INPS_MIO29_501_DPAUX_DATA_OEPS_MIO28_501_DPAUX_HOT_PLUG_DET
PS_MIO26_501_ID
1V8
1V8
1V8
VCC_ADC
1V81V8 1V8
GND_ADC
AE30AH32
Y28
R27
N27
Y30N28
AA30
N33
AB28
W30
V27
T28
P29
L31
K39
AG29
AG31AH31AK30
AH27AH28AJ27AH29
AJ30
AG30AG28
AF29
AJ31
AE29AF31
AF30
AJ29
AJ28
2
1
4
3
P38
P33
R32N32R39P31N34P30R37R34P35R33M30P32R30P36
N36
P37N38N37N39M31R35R38P39P34N31
L34
J38
J36
M39M38
J39J37K33L35L38J34J35L37L36
M33K35K34L32L30M36M35M34K32K38L33K37
Y29R28
U30
W29W27
U29
T30M29R29M28
P27V28V29U28N29T27
AC28
P28
W28
GNDGND
VCCO
_PSI
O3_
503
VCCO
_PSI
O3_
503
PS_SRST_BPS_REF_CLKPS_PROG_BPS_POR_B
PS_PADO
PS_PADI
PS_MODE3PS_MODE2PS_MODE1PS_MODE0
PS_JTAG_TMSPS_JTAG_TDO
PS_JTAG_TDIPS_JTAG_TCK
PS_INIT_BPS_ERROR_STATUS
PS_ERROR_OUTPS_DONE
VCCO
_PSI
O2_
502
VCCO
_PSI
O2_
502
PS_MIO77PS_MIO76PS_MIO75PS_MIO74PS_MIO73PS_MIO72PS_MIO71PS_MIO70PS_MIO69PS_MIO68PS_MIO67PS_MIO66PS_MIO65PS_MIO64
PS_MIO63PS_MIO62PS_MIO61PS_MIO60PS_MIO59PS_MIO58PS_MIO57PS_MIO56PS_MIO55PS_MIO54PS_MIO53PS_MIO52
VCCO
_PSI
O1_
501
VCCO
_PSI
O1_
501
PS_MIO51PS_MIO50PS_MIO49PS_MIO48PS_MIO47PS_MIO46PS_MIO45PS_MIO44PS_MIO43PS_MIO42PS_MIO41PS_MIO40PS_MIO39PS_MIO38
PS_MIO37PS_MIO36PS_MIO35PS_MIO34PS_MIO33PS_MIO32PS_MIO31PS_MIO30PS_MIO29PS_MIO28PS_MIO27PS_MIO26
VCC_
PSAD
CG
ND_P
SADC
VCCO
_PSI
O0_
500
VCCO
_PSI
O0_
500
PS_MIO9PS_MIO8PS_MIO7PS_MIO6PS_MIO5PS_MIO4PS_MIO3
PS_MIO25PS_MIO24PS_MIO23PS_MIO22PS_MIO21PS_MIO20PS_MIO2
PS_MIO19PS_MIO18PS_MIO17PS_MIO16PS_MIO15PS_MIO14PS_MIO13PS_MIO12PS_MIO11PS_MIO10PS_MIO1PS_MIO0
GNDGND
GNDGND
GND
GNDGND
GND
GND
VDDSTANDBY
GNDOUTPUT
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
ADDRESS 0X50 - 0X57
ADDRESS 0X4BI2C
PS_GTR_P/N (BANK 505) 100OHM DIFFERENTIAL
GTR REFERENCE CLOCK
GTR TRANSCEIVERS
M3 = HIGH - LOAD FROM EEPROM
7 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
NC7SZ08FHX
24AA16-I/SN
DNI
0.1UF4.7K
3900PF
49.9
R0402L
R0402L
R0402L
4.7K
0.1UF
DNI1UF
120OHM
0DNI
0
DNI
4.7K
C0603L
4.7K
100K
6.8PF 6.8PF
AD9542BCPZ
100K
100K
R0402L R0402L
4.7K
C0603L
49.9
R0402LR0402LR0402L
49.9
0.1UF
100K0.1UF
C0402LDNI
3900PF0.22UF
0
0
49.9
4.7K
XCZU11EG-1FFVF1517I
0.1UF
R0402L
R0402L
0.01UFR0402L
0.1UF
R0402L49.9
R0402L
0.1UF 0.1UF 0.1UF 1UF 1UF 10UF0.1UF0.1UF
0.1UF
0.1UF
49.152MEGHZR0402L
R0402L
R0402L
R0402L
10
49.9
0.1UF
49.9
49.90.1UF
0.01UF
0.01UF
DNI
24MEGHZ
0.01UF
0.01UF
0.01UF
0.1UF
DNI
0.1UF10UFDNI 120OHM
1UF
DNI C0402L
49.9
49.9
R0402L
R0402L
49.9
R0402L
49.9
49.9
DNI
DNI
49.9
49.9
10
R0402L
R0402L
R564
R566R563
R565R562
R561
R560C1124
U49
R559
C25
R29
U21
R417
U1
R466
R26
R360
C24
R465
R30
C32
C17
C23
C20
U29
C35
C26
R34
C29
C47
C27C46 C30 C31 C37 C38 C39C28
E3
C48
C22
R27
C40
R39
R38
R28
R35
R25
C42
C44
E2
C33
C34
C43
C36
C41
C19C18
Y1
C16
C45
C21
Y5
R32
R37
R36
R33
R31
R416
R40
R41
R421V8_AD95421V8_AD9542
I2C0_SCLI2C0_SDA
I2C_MASTER_SCLI2C_MASTER_SDA
1V8_AD9542
OUT1_B_P
OUT1_B_N
OUT0_C_P
I2C_MASTER_SCL
1V8_VDDIOB
PS_GTR_TX0_505_NPS_GTR_TX1_505_NPS_GTR_TX2_505_N
1V8_AD95421V8_AD9542
1V8_VDDIOB
1V8_VDDIOA
I2C_MASTER_SDA
1V8_VDDIOB
1V8_AD9542
1V8_AD95421V8_AD9542
1V8_VDDIOBRESETB_AD9542
1V8_VDDIOA
OUT0_B_P
1V8_AD9542
1V8_AD9542
1V8_AD9542
RESETB_AD9542
1V8_AD9542
OUT0_C_N
1V8_AD9542
OUT1_A_NOUT1_A_P
1V8_AD9542
OUT0_C_NOUT0_C_P
OUT0_B_NOUT0_B_P
1V8_AD9542
I2C0_SDAI2C0_SCL
1V8
OUT0_A_POUT0_A_N
PS_GTR_TX3_505_NPS_GTR_TX0_505_PPS_GTR_TX1_505_PPS_GTR_TX2_505_P
OUT1_B_N
1V8
OUT1_A_N
OUT1_B_P
PS_GTR_125MHZ_505_P1V8
1V8_AD9542
PS_GTR_27MHZ_505_P
PS_GTR_26MHZ_505_P
PS_GTR_RX1_505_N
PS_GTR_RX1_505_PPS_GTR_RX2_505_PPS_GTR_RX3_505_P PS_GTR_TX3_505_P
PS_GTR_RX3_505_N
PS_GTR_RX0_505_N
PS_GTR_26MHZ_505_N
PS_GTR_125MHZ_505_NPS_GTR_REFCLK0_505_PPS_GTR_REFCLK0_505_N
PS_GTR_RX0_505_P
PS_GTR_RX2_505_N
PS_GTR_27MHZ_505_NPS_GTR_125MHZ_505_P
1V8
1V8_VDDIOB
1V8_VDDIOB
PS_MIO24_500_AD9542_RESET_B
1V8
1V2_PL_DDR4
PL_DDR4_0_CKIN_69_N
PL_DDR4_0_CKIN_69_P
1V2_PL_DDR4PL_DDR4_1_CKIN_71_P
PL_DDR4_1_CKIN_71_N
PS_GTR_27MHZ_505_N
PS_GTR_27MHZ_505_P1V8
PG_ALL
PS_GTR_125MHZ_505_N
OUT0_A_P
OUT0_B_N
OUT1_A_P
1V8
1V8
PS_GTR_26MHZ_505_N
PS_GTR_26MHZ_505_P
OUT0_A_N
25
22
43PAD
3534
2726
36
37
33
46
21191816
929
5
40
13
10
44
32
24
1112
28
42
3130
8
39
34
2
48 38
7
14
6
47 4145
201715
1
23
54
876
123
W39
U34W34Y36AB36U35W35Y37AB37
U38V36W38
AA38U39V37
AA39V32V33Y32Y33
AA34AA35AB32AB33
3
2
1
4
GND
PS_MGTRTXP3_505PS_MGTRTXP2_505PS_MGTRTXP1_505PS_MGTRTXP0_505PS_MGTRTXN3_505PS_MGTRTXN2_505PS_MGTRTXN1_505PS_MGTRTXN0_505
PS_MGTRRXP3_505PS_MGTRRXP2_505PS_MGTRRXP1_505PS_MGTRRXP0_505PS_MGTRRXN3_505PS_MGTRRXN2_505PS_MGTRRXN1_505PS_MGTRRXN0_505PS_MGTREFCLK3P_505PS_MGTREFCLK3N_505PS_MGTREFCLK2P_505PS_MGTREFCLK2N_505PS_MGTREFCLK1P_505PS_MGTREFCLK1N_505PS_MGTREFCLK0P_505PS_MGTREFCLK0N_505
GND
GND
GND
GND
VSS
VCCWP
A2A1A0
SCLSDA
GND
GND
PAD
RESE
TBRE
FARE
FAA
VDD
DNC
XOB
XOA
VDD
VDD
REFB
BRE
FB M4
M3M2
VDDIOBM1M0
VDDLDO1
LF1VDDVDD
OUT1ANOUT1AP
VDD
OUT
1BN
OUT
1BP
DNC
VDD
VDD
OUT
0CN
OUT
0CP
DNC
OUT
0BN
OUT
0BP
VDD
OUT0ANOUT0APVDDVDDLF0LVO0VDDCSB/M6SDIO/SDAVDDIOASCLK/SCLSDO/M5
VCC
NC
Y
GNDBA
GND
GND
GND
GND
GND GND
GND
GND
GND
GNDGNDVDD
STANDBYGND
OUTPUT
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
4GBYTE DDR4 WITH ECCPS DDR
PLACE DIRECTLY UNDERNEATH THE PAD
8 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
100UF 100UF
0.068UF0.068UF0.068UF0.068UF
0.068UF
0.068UF
0.068UF
0.068UF
0.068UF 0.068UF 0.068UF
0.068UF 0.068UF
0.068UF 0.068UF 0.068UF
0.068UF
0.068UF 0.068UF
0.1UF 0.1UF
0.1UF0.1UF
0.01UF 0.01UF 0.01UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
19 13 9
8 1 4 3 10
1814121617
7
11
4.7UF
0.068UF
6
MT40A512M16LY-062E IT:E
MT40A512M16LY-062E IT:E
0.47UF
20
0.47UF
15
0.47UF
2
0.47UF
5
0.47UF 0.47UF
0.47UF0.47UF
0.01UF 0.01UF0.01UF
XCZU11EG-1FFVF1517I
499
499
22
240
240
21
240
C64 C74
C62
C67
C78
C79
C83 C87 C95
C82 C86
C89
C94
C93
C72
C76
C60 C70 C81 C85 C92
C84C80C68C58
C90C88C66
C57C56C55C54C52C50C49
C91
U2
C77
U3
C61 C71
C69C59
C65 C75
C73C63
C51 C53
U21
R45
R44
R43
R46
R47
PS_DDR4_DQ25_504PS_DDR4_DQ31_504
PS_DDR4_DQ28_504
PS_DDR4_DQS2_504_PPS_DDR4_DQS2_504_N
PS_DDR4_DQS3_504_PPS_DDR4_DQS3_504_N
PS_DDR4_DQ24_504
PS_DDR4_DQ49_504PS_DDR4_DQS3_504_N PS_DDR4_A4_504
PS_DDR4_DQ30_504
PS_DDR4_A3_504
PS_DDR4_A11_504PS_DDR4_A12_504PS_DDR4_A13_504
PS_DDR4_BA0_504PS_DDR4_BA1_504PS_DDR4_BG0_504
PS_DDR4_A14_504
PS_DDR4_A15_504
PS_DDR4_CK0_504_PPS_DDR4_CK0_504_N
PS_DDR4_A7_504
PS_DDR4_A9_504PS_DDR4_A10_504
2V5_VP_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
2V5_VP_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
2V5_VP_DDR4
1V2_PS_DDR4
2V5_VP_DDR4 1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
VREF_PS_DDR4
VREF_PS_DDR4
1V2_PS_DDR4
PS_DDR4_DQ8_504
PS_DDR4_DQS1_504_P
PS_DDR4_DQ9_504
PS_DDR4_DQ12_504
PS_DDR4_DQ10_504PS_DDR4_DQ11_504
PS_DDR4_DQ13_504PS_DDR4_DQ14_504PS_DDR4_DQ15_504
PS_DDR4_DM0_504
PS_DDR4_DQS0_504_N
PS_DDR4_DQ1_504PS_DDR4_DQ0_504
PS_DDR4_DQS0_504_P
PS_DDR4_DQ4_504
PS_DDR4_DQ2_504PS_DDR4_DQ3_504
PS_DDR4_DQ5_504PS_DDR4_DQ6_504PS_DDR4_DQ7_504
PS_DDR4_ODT0
PS_DDR4_ACT#
PS_DDR4_CS0#
PS_DDR4_A16_504
VREF_PS_DDR4
PS_DDR4_A4_504
PS_DDR4_RESET#
PS_DDR4_A6_504
PS_DDR4_A0_504PS_DDR4_A1_504
PS_DDR4_A5_504
PS_DDR4_ALERT#
PS_DDR4_A8_504
PS_DDR4_A2_504
PS_DDR4_PARITY
1V2_PS_DDR4
PS_DDR4_DM1_504
PS_DDR4_DQS1_504_N
PS_DDR4_DM3_504PS_DDR4_DM2_504
PS_DDR4_DQ17_504PS_DDR4_DQ16_504
PS_DDR4_DQ20_504
PS_DDR4_DQ18_504PS_DDR4_DQ19_504
PS_DDR4_DQ21_504PS_DDR4_DQ22_504
PS_DDR4_CKE0
PS_DDR4_ODT0
PS_DDR4_CK0_504_PPS_DDR4_CK0_504_N
PS_DDR4_A14_504
PS_DDR4_ACT#
PS_DDR4_CS0#
PS_DDR4_A16_504
PS_DDR4_BG0_504
PS_DDR4_A10_504
PS_DDR4_A12_504
PS_DDR4_A15_504
PS_DDR4_BA0_504
PS_DDR4_A3_504
PS_DDR4_BA1_504
PS_DDR4_RESET#
PS_DDR4_A0_504PS_DDR4_A1_504
PS_DDR4_A5_504
PS_DDR4_ALERT#
PS_DDR4_A8_504
PS_DDR4_A2_504
PS_DDR4_A9_504
PS_DDR4_A11_504
PS_DDR4_PARITY
PS_DDR4_A13_504
VREF_PS_DDR4
PS_DDR4_A6_504PS_DDR4_A7_504
PS_DDR4_CKE0
1V2_PS_DDR4
PS_DDR4_DQ10_504
PS_DDR4_DQ6_504
PS_DDR4_DQ39_504
PS_DDR4_A0_504PS_DDR4_A1_504PS_DDR4_A2_504PS_DDR4_A3_504PS_DDR4_A4_504PS_DDR4_A5_504PS_DDR4_A6_504PS_DDR4_A7_504PS_DDR4_A8_504PS_DDR4_A9_504PS_DDR4_A10_504PS_DDR4_A11_504PS_DDR4_A12_504PS_DDR4_A13_504PS_DDR4_A14_504PS_DDR4_A15_504PS_DDR4_A16_504
PS_DDR4_ACT#PS_DDR4_BA0_504PS_DDR4_BA1_504PS_DDR4_BG0_504
PS_DDR4_CK0_504_P
PS_DDR4_CKE0
PS_DDR4_CK0_504_N
PS_DDR4_CS0#
PS_DDR4_DM0_504PS_DDR4_DM1_504PS_DDR4_DM2_504PS_DDR4_DM3_504PS_DDR4_DM4_504PS_DDR4_DM5_504PS_DDR4_DM6_504PS_DDR4_DM7_504PS_DDR4_DM8_504PS_DDR4_ODT0
PS_DDR4_PARITYPS_DDR4_RESET#
PS_DDR4_DQS0_504_NPS_DDR4_DQS1_504_NPS_DDR4_DQS2_504_N
PS_DDR4_DQS4_504_NPS_DDR4_DQS5_504_NPS_DDR4_DQS6_504_NPS_DDR4_DQS7_504_NPS_DDR4_DQS8_504_NPS_DDR4_DQS0_504_PPS_DDR4_DQS1_504_PPS_DDR4_DQS2_504_PPS_DDR4_DQS3_504_PPS_DDR4_DQS4_504_PPS_DDR4_DQS5_504_PPS_DDR4_DQS6_504_PPS_DDR4_DQS7_504_PPS_DDR4_DQS8_504_P
PS_DDR4_ALERT#
PS_DDR4_DQ1_504PS_DDR4_DQ7_504PS_DDR4_DQ2_504PS_DDR4_DQ5_504
PS_DDR4_DQ4_504PS_DDR4_DQ0_504PS_DDR4_DQ3_504PS_DDR4_DQ12_504PS_DDR4_DQ14_504PS_DDR4_DQ11_504PS_DDR4_DQ9_504PS_DDR4_DQ8_504PS_DDR4_DQ15_504PS_DDR4_DQ13_504
PS_DDR4_DQ19_504PS_DDR4_DQ20_504PS_DDR4_DQ21_504PS_DDR4_DQ18_504PS_DDR4_DQ17_504PS_DDR4_DQ23_504PS_DDR4_DQ22_504PS_DDR4_DQ16_504PS_DDR4_DQ30_504PS_DDR4_DQ31_504PS_DDR4_DQ26_504PS_DDR4_DQ28_504PS_DDR4_DQ25_504PS_DDR4_DQ27_504PS_DDR4_DQ29_504PS_DDR4_DQ24_504PS_DDR4_DQ36_504PS_DDR4_DQ34_504PS_DDR4_DQ38_504
PS_DDR4_DQ33_504PS_DDR4_DQ35_504PS_DDR4_DQ37_504PS_DDR4_DQ32_504PS_DDR4_DQ42_504PS_DDR4_DQ46_504PS_DDR4_DQ40_504PS_DDR4_DQ47_504PS_DDR4_DQ45_504PS_DDR4_DQ43_504PS_DDR4_DQ44_504PS_DDR4_DQ41_504PS_DDR4_DQ53_504
PS_DDR4_DQ61_504PS_DDR4_DQ60_504
PS_DDR4_DQ62_504PS_DDR4_DQ58_504
PS_DDR4_DQ63_504PS_DDR4_DQ59_504PS_DDR4_DQ52_504
PS_DDR4_DQ48_504PS_DDR4_DQ50_504PS_DDR4_DQ54_504PS_DDR4_DQ55_504PS_DDR4_DQ51_504
PS_DDR4_DQ56_504PS_DDR4_DQ57_504PS_DDR4_DQ64_504PS_DDR4_DQ65_504PS_DDR4_DQ66_504PS_DDR4_DQ67_504 PS_DDR4_DQ68_504
PS_DDR4_DQ69_504PS_DDR4_DQ70_504PS_DDR4_DQ71_504
PS_DDR4_DQ23_504
PS_DDR4_DQ29_504PS_DDR4_DQ26_504PS_DDR4_DQ27_504
A7
A3
AG39
G7
B8
J8
A3
A7B7
B8
C2
C3C7
C8
D7
E2E7
F3
F7
F9
G2
G3
H2
H3H7
H8J3J7
K2
K3
K7K8
L2
L3
L7
L8
M1
M2
M3
M7
M8
N2
N3N7
N8
N9
P1
P2
P3P7
P8
P9
R2
R3
R7
R8
T2
T3T7
T8
B3 B9 D1 G7
J1 J9 L1 L9 R1 T9A1 A9 C1 D9 F2 F8 G1
G9
J2 J8B1 R9
B2 E1 E9 G8 K1 K9 M9 N1 T1A2 A8 C9 D2 D8 E3 E8 F1 H1 H9
D3
B7
D3D7
E2E7
F3
F7
F9
G2
H2
H3H7
H8
K3
K7K8
L2
L3
L7M
1
M2
M7
M8
N2
N9
P1
P9
R8
T3T7
T8
B3 B9 D1 J1 J9 L1 L9 R1 T9A1 A9 C1 D9 F2 F8 G1
G9
J2B1 R9
B2 E1 E9 G8 K1 K9 M9 N1 T1A2 A8 C9 D2 D8 E3 E8 F1 H1 H9
K2
L8
N8
T2M3R7R2
P8N3N7R3P7P3
P2
AN38
AL37AN39AP39
AD37
AF33
AK29
AT36AU36AU38AT38AT37AU39AK32AL31AM30AM31AR34AR37AR38AR39AP37AP36AN33AJ32AL33
AM34
AN36
AL32AV37AR35
AV38AP35
AV36AT35
AW36AP34AU30AW32AM29AR30AJ35AE34AJ37AF37AL38
AW30AR29AR28AV29AR27AT28AV28AW29AV31AV32AW34AU34AW31AW35AV34AU31AP29AN27AL28AP27AN29AK28AK27AL27AP31AP32AN31AP30AT33AT32AT31AT30AL35AM36AM35
AK38AK39
AN37
AK37
AU29AV33AN28AR33AK35
AH38AE37AM39AU28AU33AM28
AK34AE33
AM38
AW37AU35AM33
AL30
AL34
AP33
AP38
AT34
AT39
AV35
AN34
AH37
AN32
AF35
AJ34AK33AH33
AH34AL36AE32AF32AD32AG33
AD34AD31AG34AG36
AH39
AE38
AE35
AD36AD35
AF36
AE39AF38AD39
AJ36
AG35
AJ39
AH36
AG38
AR32
J7
C2
G3
C3
C8
C7
J3
GND
VCCO
_PSD
DR_5
04VC
CO_P
SDDR
_504
VCCO
_PSD
DR_5
04VC
CO_P
SDDR
_504
VCCO
_PSD
DR_5
04VC
CO_P
SDDR
_504
PS_DDR_DQ66PS_DDR_DQ65PS_DDR_DQ64PS_DDR_DQ63PS_DDR_DQ62PS_DDR_DQ61PS_DDR_DQ60PS_DDR_DQ59PS_DDR_DQ58PS_DDR_DQ57PS_DDR_DQ56PS_DDR_DQ55PS_DDR_DQ54PS_DDR_DQ53PS_DDR_DQ52PS_DDR_DQ51PS_DDR_DQ50PS_DDR_DQ49PS_DDR_DQ48PS_DDR_DQ47PS_DDR_DQ46PS_DDR_DQ45PS_DDR_DQ44PS_DDR_DQ43PS_DDR_DQ42PS_DDR_DQ41PS_DDR_DQ40PS_DDR_DQ39PS_DDR_DQ38PS_DDR_DQ37PS_DDR_DQ36PS_DDR_DQ35PS_DDR_DQ34PS_DDR_DQ33PS_DDR_DQ32PS_DDR_DQ31PS_DDR_DQ30PS_DDR_DQ29PS_DDR_DQ28PS_DDR_DQ27PS_DDR_DQ26PS_DDR_DQ25PS_DDR_DQ24PS_DDR_DQ23PS_DDR_DQ22PS_DDR_DQ21PS_DDR_DQ20PS_DDR_DQ19PS_DDR_DQ18PS_DDR_DQ17PS_DDR_DQ16PS_DDR_DQ15PS_DDR_DQ14PS_DDR_DQ13PS_DDR_DQ12PS_DDR_DQ11PS_DDR_DQ10PS_DDR_DQ9PS_DDR_DQ8PS_DDR_DQ7PS_DDR_DQ6PS_DDR_DQ5PS_DDR_DQ4PS_DDR_DQ3PS_DDR_DQ2PS_DDR_DQ1PS_DDR_DQ0
PS_DDR_ALERT_N
PS_DDR_ZQ
PS_DDR_DQS_P8PS_DDR_DQS_P7PS_DDR_DQS_P6PS_DDR_DQS_P5PS_DDR_DQS_P4PS_DDR_DQS_P3PS_DDR_DQS_P2PS_DDR_DQS_P1PS_DDR_DQS_P0PS_DDR_DQS_N8PS_DDR_DQS_N7PS_DDR_DQS_N6PS_DDR_DQS_N5PS_DDR_DQS_N4PS_DDR_DQS_N3PS_DDR_DQS_N2PS_DDR_DQS_N1PS_DDR_DQS_N0
PS_DDR_DQ71PS_DDR_DQ70PS_DDR_DQ69PS_DDR_DQ68PS_DDR_DQ67
PS_DDR_RAM_RST_NPS_DDR_PARITY
PS_DDR_ODT1PS_DDR_ODT0
PS_DDR_DM8PS_DDR_DM7PS_DDR_DM6PS_DDR_DM5PS_DDR_DM4PS_DDR_DM3PS_DDR_DM2PS_DDR_DM1PS_DDR_DM0
PS_DDR_CS_N1PS_DDR_CS_N0PS_DDR_CK_N1PS_DDR_CK_N0
PS_DDR_CKE1PS_DDR_CKE0
PS_DDR_CK1PS_DDR_CK0PS_DDR_BG1PS_DDR_BG0PS_DDR_BA1PS_DDR_BA0
PS_DDR_ACT_NPS_DDR_A17PS_DDR_A16PS_DDR_A15PS_DDR_A14PS_DDR_A13PS_DDR_A12PS_DDR_A11PS_DDR_A10
PS_DDR_A9PS_DDR_A8PS_DDR_A7PS_DDR_A6PS_DDR_A5PS_DDR_A4PS_DDR_A3PS_DDR_A2PS_DDR_A1PS_DDR_A0
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GNDGND
GNDGND
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
GND GND
GND
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
4GBYTE DDR4 WITH ECCPS DDR
9 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
39.2
39.2
39.2
240240
240
499
499
499
0.47UF
0.068UF0.068UF 0.068UF
0.47UF 0.47UF
0.47UF 0.47UF
0.47UF
0.47UF
0.47UF 0.47UF
0.47UF 0.47UF
0.47UF
MT40A512M16LY-062E IT:E
MT40A512M16LY-062E IT:EMT40A512M16LY-062E IT:E
0.068UF
4.7UF
4.7UF 4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF 0.1UF
0.068UF 0.068UF 0.068UF
0.068UF 0.068UF 0.068UF 0.068UF
0.068UF
0.068UF0.068UF
0.068UF
0.068UF 0.068UF
0.068UF 0.068UF
0.068UF
0.068UF
0.068UF 0.068UF
0.068UF 0.068UF
0.068UF 0.068UF
0.068UF 0.068UF
0.068UF
R422
R420
R421
R50R53
R51
R48
R49
R52
C107 C117
C103 C113
C101 C111
C97
C140
C137 C142
C99 C108
C106
C135
U5
U6U4
C127
C110
C131
C132C125C120
C133C126C121
C119
C118
C109
C100
C112C102
C105
C128
C129
C124
C122C116
C130C123
C115
C114
C104
C96
C98
C139
C150
C151
C149
C147C145
C152C148C146
C144
C143
C138
C134
C141C136
VREF_PS_DDR4
PS_DDR4_A13_504
PS_DDR4_PARITY
PS_DDR4_A11_504
PS_DDR4_A7_504
PS_DDR4_A9_504
PS_DDR4_A2_504
PS_DDR4_A8_504
PS_DDR4_ALERT#
PS_DDR4_A5_504
PS_DDR4_A1_504PS_DDR4_A0_504
PS_DDR4_A6_504
PS_DDR4_RESET#
PS_DDR4_BA1_504
PS_DDR4_A3_504PS_DDR4_A4_504
PS_DDR4_BA0_504
PS_DDR4_A15_504
PS_DDR4_A12_504
PS_DDR4_A10_504
PS_DDR4_BG0_504
VREF_PS_DDR4
PS_DDR4_A16_504
PS_DDR4_CS0#
PS_DDR4_ACT#
PS_DDR4_A14_504
PS_DDR4_CK0_504_NPS_DDR4_CK0_504_P
PS_DDR4_ODT0
PS_DDR4_CKE0
PS_DDR4_DQ55_504PS_DDR4_DQ54_504PS_DDR4_DQ53_504
PS_DDR4_DQ51_504PS_DDR4_DQ50_504
PS_DDR4_DQ52_504
PS_DDR4_DQS6_504_P
PS_DDR4_DQ48_504PS_DDR4_DQ49_504
PS_DDR4_DQS6_504_N
PS_DDR4_DM6_504PS_DDR4_DM7_504
PS_DDR4_DQ63_504PS_DDR4_DQ62_504PS_DDR4_DQ61_504
PS_DDR4_DQ59_504PS_DDR4_DQ58_504
PS_DDR4_DQ60_504
PS_DDR4_DQ57_504
PS_DDR4_DQS7_504_PPS_DDR4_DQS7_504_N
PS_DDR4_DQ56_504
PS_DDR4_A13_504
PS_DDR4_PARITY
PS_DDR4_A11_504
PS_DDR4_A7_504
PS_DDR4_A9_504
PS_DDR4_A2_504
PS_DDR4_A8_504
PS_DDR4_ALERT#
PS_DDR4_A5_504
PS_DDR4_A1_504PS_DDR4_A0_504
PS_DDR4_A6_504
PS_DDR4_RESET#
PS_DDR4_BA1_504
PS_DDR4_A3_504PS_DDR4_A4_504
PS_DDR4_BA0_504
PS_DDR4_A15_504
PS_DDR4_A12_504
PS_DDR4_A10_504
PS_DDR4_BG0_504
PS_DDR4_A16_504
PS_DDR4_CS0#
PS_DDR4_ACT#
PS_DDR4_A14_504
PS_DDR4_CK0_504_NPS_DDR4_CK0_504_P
PS_DDR4_ODT0
PS_DDR4_CKE0
PS_DDR4_DQ70_504PS_DDR4_DQ69_504
PS_DDR4_DQ67_504PS_DDR4_DQ66_504
PS_DDR4_DQ68_504
PS_DDR4_DQS8_504_P
PS_DDR4_DQ64_504PS_DDR4_DQ65_504
PS_DDR4_DQS8_504_N
PS_DDR4_DM8_504
PS_DDR4_DQ71_504
PS_DDR4_A13_504
PS_DDR4_PARITY
PS_DDR4_A11_504
PS_DDR4_A7_504
PS_DDR4_A9_504
PS_DDR4_A2_504
PS_DDR4_A8_504
PS_DDR4_ALERT#
PS_DDR4_A5_504
PS_DDR4_A1_504PS_DDR4_A0_504
PS_DDR4_A6_504
PS_DDR4_RESET#
PS_DDR4_BA1_504
PS_DDR4_A3_504PS_DDR4_A4_504
PS_DDR4_BA0_504
PS_DDR4_A15_504
PS_DDR4_A12_504
PS_DDR4_A10_504
PS_DDR4_BG0_504
VREF_PS_DDR4
PS_DDR4_A16_504
PS_DDR4_CS0#
PS_DDR4_ACT#
PS_DDR4_A14_504
PS_DDR4_CK0_504_NPS_DDR4_CK0_504_P
PS_DDR4_ODT0
PS_DDR4_CKE0
PS_DDR4_DQ39_504PS_DDR4_DQ38_504PS_DDR4_DQ37_504
PS_DDR4_DQ35_504PS_DDR4_DQ34_504
PS_DDR4_DQ36_504
PS_DDR4_DQS4_504_P
PS_DDR4_DQ32_504PS_DDR4_DQ33_504
PS_DDR4_DQS4_504_N
PS_DDR4_DM4_504PS_DDR4_DM5_504
PS_DDR4_DQ47_504PS_DDR4_DQ46_504PS_DDR4_DQ45_504
PS_DDR4_DQ43_504PS_DDR4_DQ42_504
PS_DDR4_DQ44_504
PS_DDR4_DQ41_504
PS_DDR4_DQS5_504_PPS_DDR4_DQS5_504_N
PS_DDR4_DQ40_504
1V2_PS_DDR4
1V2_PS_DDR4
VREF_PS_DDR4
VREF_PS_DDR4
VREF_PS_DDR4 2V5_VP_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
2V5_VP_DDR4
2V5_VP_DDR4
1V2_PS_DDR41V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
1V2_PS_DDR4
2V5_VP_DDR4 1V2_PS_DDR4
2V5_VP_DDR4 1V2_PS_DDR4
2V5_VP_DDR4 1V2_PS_DDR4
G3
T7
H9H1F1E8E3D8D2C9A8A2 T1N1M9K9K1G8E9E1B2
R9B1 J8J2G9
G1
F8F2D9C1A9A1 T9R1L9L1J9J1G7
D1B9B3
T8
T3
T2
R8
R7
R3
R2
P9
P8
P7P3
P2
P1
N9
N8
N7N3
N2
M8
M7
M3
M2
M1
L8
L7
L3
L2
K8K7
K3
K2
J7J3H8
H7H3
H2
G3
G2
F9
F7
F3
E7E2
D7D3C8
C7C3
C2
B8
B7A7
A3
H9H1F1E8E3D8D2C9A8A2 T1N1M9K9K1G8E9E1B2
R9B1 J8J2G9
G1
F8F2D9C1A9A1 T9R1L9L1J9J1G7
D1B9B3
T8
T7T3
T2
R8
R7
R3
R2
P9
P8
P7P3
P2
P1
N9
N8
N7N3
N2
M8
M7
M3
M2
M1
L8
L7
L3
L2
K8K7
K3
K2
J7J3H8
H7H3
H2
G2
F9
F7
F3
E7E2
D7D3C8
C7C3
C2
B8
B7A7
A3
H9H1F1E8E3D8D2C9A8A2 T1N1M9K9K1G8E9E1B2
R9B1 J8J2G9
G1
F8F2D9C1A9A1 T9R1L9L1J9J1G7
D1B9B3
T8
T7T3
T2
R8
R7
R3
R2
P9
P8
P7P3
P2
P1
N9
N8
N7N3
N2
M8
M7
M3
M2
M1
L8
L7
L3
L2
K8K7
K3
K2
J7J3H8
H7H3
H2
G3
G2
F9
F7
F3
E7E2
D7D3C8
C7C3
C2
B8
B7A7
A3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
PS DDR TERMINATION
10 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
39.239.239.239.239.239.2
1K
39.2
4.7K
36.536.5
39.2 39.2 39.2 39.239.239.239.2 39.239.239.239.239.239.239.239.239.239.239.2
14412131912
3
4.7UF 4.7UF 4.7UF
0.01UF
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
R159R158R157R156R155R154
R149
R153
R148
R151R147
R172 R173 R174 R175R171R170R152 R169R168R167R166R165R164R163R162R161R160R150
C428C427C426C425C423C422C421C420C419
C424
PS_DDR4_A10_504PS_DDR4_A9_504PS_DDR4_A8_504
PS_DDR4_CK0_504_N
PS_DDR4_A15_504
PS_DDR4_A13_504
PS_DDR4_A11_504
PS_DDR4_A6_504
PS_DDR4_A4_504
VTT_PS_DDR4
1V2_PS_DDR4
PS_DDR4_ALERT#
PS_DDR4_CS0#PS_DDR4_ODT0PS_DDR4_PARITYPS_DDR4_ACT#
1V2_PS_DDR4
PS_DDR4_CK0_504_P
VTT_PS_DDR4
PS_DDR4_RESET#
PS_DDR4_CKE0PS_DDR4_BG0_504PS_DDR4_BA1_504
PS_DDR4_A16_504
PS_DDR4_A14_504
PS_DDR4_A12_504
PS_DDR4_A5_504
PS_DDR4_A3_504
PS_DDR4_A1_504PS_DDR4_A0_504
PS_DDR4_A7_504
PS_DDR4_A2_504
PS_DDR4_BA0_504
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
2GBYTE DDR4, X32PL DDR
11 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
240
240
499
499MT40A512M16LY-062E IT:E
0.068UF
0.47UF
0.1UF
0.47UF 0.47UF0.47UF
0.47UF0.47UF 0.47UF0.47UF
MT40A512M16LY-062E IT:E
0.1UF 4.7UF0.1UF
4.7UF4.7UF
4.7UF
4.7UF
4.7UF
0.1UF
0.068UF 0.068UF 0.068UF 0.068UF 0.068UF0.068UF0.068UF
0.068UF0.068UF0.068UF0.068UF0.068UF
0.068UF
0.068UF0.068UF0.068UF0.068UF
0.068UF0.068UF
R57
R56
R55
R54
U31
U30
C162C156 C182C178
C180C159 C176C154
C155 C161
C160
C165
C166 C168 C174
C170 C173
C177 C181
C185
C186 C188 C190
C164
C163
C153
C171C169
C172C167C158
C157
C189C187C184C179
C183
C175
PL_DDR4_0_A13_69
PL_DDR4_0_PARITY_69
PL_DDR4_0_A11_69
PL_DDR4_0_A7_69
PL_DDR4_0_A9_69
PL_DDR4_0_A2_69
PL_DDR4_0_A8_69
PL_DDR4_0_ALERT#_70
PL_DDR4_0_A5_69
PL_DDR4_0_A1_69PL_DDR4_0_A0_69
PL_DDR4_0_A6_69
PL_DDR4_0_RST#_70
PL_DDR4_0_BA1_69
PL_DDR4_0_A3_69PL_DDR4_0_A4_69
PL_DDR4_0_BA0_69
PL_DDR4_0_A15_69
PL_DDR4_0_A12_69
PL_DDR4_0_A10_69
PL_DDR4_0_BG0_69
VREF_PL_DDR4
PL_DDR4_0_A16_69
PL_DDR4_0_CS#_69
PL_DDR4_0_ACT#_69
PL_DDR4_0_A14_69
PL_DDR4_0_CK_69_NPL_DDR4_0_CK_69_P
PL_DDR4_0_ODT_69
PL_DDR4_0_CKE_69
PL_DDR4_0_DQ7_69PL_DDR4_0_DQ6_69PL_DDR4_0_DQ5_69
PL_DDR4_0_DQ3_69PL_DDR4_0_DQ2_69
PL_DDR4_0_DQ4_69
PL_DDR4_0_DQS0_69_P
PL_DDR4_0_DQ0_69PL_DDR4_0_DQ1_69
PL_DDR4_0_DQS0_69_N
PL_DDR4_0_DM0_69PL_DDR4_0_DM1_69
PL_DDR4_0_DQ15_69PL_DDR4_0_DQ14_69PL_DDR4_0_DQ13_69
PL_DDR4_0_DQ11_69PL_DDR4_0_DQ10_69
PL_DDR4_0_DQ12_69
PL_DDR4_0_DQ9_69
PL_DDR4_0_DQS1_69_PPL_DDR4_0_DQS1_69_N
PL_DDR4_0_DQ8_69
2V5_VP_DDR4
PL_DDR4_0_DQ26_70PL_DDR4_0_DQ27_70PL_DDR4_0_DQ28_70
PL_DDR4_0_DQ25_70PL_DDR4_0_DQ24_70PL_DDR4_0_DQ23_70PL_DDR4_0_DQ22_70PL_DDR4_0_DQ21_70
1V2_PL_DDR4PL_DDR4_0_DQ16_70PL_DDR4_0_DQ17_70PL_DDR4_0_DQ18_70
PL_DDR4_0_DQ20_70PL_DDR4_0_DQ19_70
PL_DDR4_0_DQ31_70
PL_DDR4_0_DQ29_70PL_DDR4_0_DQ30_70
PL_DDR4_0_DQS2_70_P
1V2_PL_DDR4
1V2_PL_DDR4
PL_DDR4_0_DQS2_70_NPL_DDR4_0_A15_69PL_DDR4_0_A16_69
PL_DDR4_0_CK_69_P
PL_DDR4_0_A13_69
PL_DDR4_0_PARITY_69
PL_DDR4_0_A11_69
PL_DDR4_0_A7_69
PL_DDR4_0_A9_69
PL_DDR4_0_A2_69
PL_DDR4_0_A8_69
PL_DDR4_0_ALERT#_70
PL_DDR4_0_A5_69
PL_DDR4_0_A1_69PL_DDR4_0_A0_69
PL_DDR4_0_A6_69
PL_DDR4_0_RST#_70
PL_DDR4_0_BA1_69
PL_DDR4_0_A3_69PL_DDR4_0_A4_69
PL_DDR4_0_BA0_69
PL_DDR4_0_A12_69
PL_DDR4_0_A10_69
PL_DDR4_0_BG0_69
VREF_PL_DDR4
PL_DDR4_0_CS#_69
PL_DDR4_0_ACT#_69
PL_DDR4_0_A14_69
PL_DDR4_0_CK_69_N
PL_DDR4_0_ODT_69
PL_DDR4_0_CKE_69PL_DDR4_0_DM2_70PL_DDR4_0_DM3_70
PL_DDR4_0_DQS3_70_PPL_DDR4_0_DQS3_70_N
VREF_PL_DDR4
VREF_PL_DDR41V2_PL_DDR42V5_VP_DDR4
2V5_VP_DDR4
1V2_PL_DDR4
2V5_VP_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
F1
A7B7
B8
C8D3
E2E7
F9
H2
H3H7
K2
K3
K7K8
L3
L7
L8
M1
M2
M3
M7
M8
N2
N3N7
N8
N9
P1
P2
P3P7
P8
P9
R2
R3
R7
R8
T2
T3T7
B3 B9 D1 G7
L1 R1 T9A1 A9 D9 F2 G1
G9
J2 J8B1 R9
B2 E1 E9 G8 K1 K9 M9 N1 T1A2 A8 C9 D2 D8 E3 E8 H1 H9
T8
L2
A3J7J3H8
D7
C2
C3
L9
F7
J9J1C1 F8
G2
C7
F3G3
F7
C2
B9F2
C3
J7
H9H1F1E8E3D8D2C9A8A2 T1N1M9K9K1G8E9E1B2
R9B1 J8J2G9
G1
F8D9C1A9A1 T9R1L9L1J9J1G7
D1B3
T8
T7T3
T2
R8
R7
R3
R2
P9
P8
P7P3
P2
P1
N9
N8
N7N3
N2
M8
M7
M3
M2
M1
L8
L7
L3
L2
K8K7
K3
K2
J3H8
H7H3
H2
G3
G2
F9
F3
E7E2
D7D3C8
C7
B8
B7A7
A3
GNDGND
GND GND
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
PL DDR 2GBYTE DDR4, X32
12 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
240
240
499
499
0.068UF0.068UF0.068UF0.068UF0.068UF0.068UF0.068UF0.068UF
0.068UF 0.068UF0.068UF0.068UF0.068UF0.068UF0.068UF
0.068UF0.068UF
0.068UF
0.1UF0.1UF
0.1UF 0.1UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF0.47UF0.47UF
0.47UF0.47UF
0.47UF0.47UF
0.47UF0.47UF
MT40A512M16LY-062E IT:E
0.068UF0.068UF
MT40A512M16LY-062E IT:E
R222
R221
R220
R219
C655 C661
C660
C666
C663
C668
C685
C674
C670 C673
C677 C681 C686 C688 C690
C683
C653 C658
C657
C664 C667 C672
C669 C671
C675 C679 C684 C687 C689
U41
U42
C682C678
C659C654
C662C656
C680C676
C665PL_DDR4_1_DQ24_71PL_DDR4_1_DQ25_71PL_DDR4_1_DQ26_71PL_DDR4_1_DQ27_71PL_DDR4_1_DQ28_71PL_DDR4_1_DQ29_71PL_DDR4_1_DQ30_71
PL_DDR4_1_DQ23_71
PL_DDR4_1_DQ21_71PL_DDR4_1_DQ22_71
PL_DDR4_1_DQ20_71PL_DDR4_1_DQ19_71PL_DDR4_1_DQ18_71PL_DDR4_1_DQ17_71PL_DDR4_1_DQ16_71
PL_DDR4_1_DQ0_70
PL_DDR4_1_DQ3_70PL_DDR4_1_DQ2_70
PL_DDR4_1_DQ5_70
PL_DDR4_1_DQ1_70
PL_DDR4_1_DQ4_70
PL_DDR4_1_DQ14_70
PL_DDR4_1_DQ10_70PL_DDR4_1_DQ9_70PL_DDR4_1_DQ8_70PL_DDR4_1_DQ7_70
PL_DDR4_1_DQ13_70PL_DDR4_1_DQ12_70PL_DDR4_1_DQ11_70
PL_DDR4_1_DQ6_70
PL_DDR4_1_DQ15_70
PL_DDR4_1_DQS0_70_N
PL_DDR4_1_DQS1_70_PPL_DDR4_1_DQS1_70_N
PL_DDR4_1_DM0_70PL_DDR4_1_DM1_70
PL_DDR4_1_DQS0_70_P
2V5_VP_DDR4
PL_DDR4_1_DQ31_71
PL_DDR4_1_DQS2_71_P
1V2_PL_DDR4
1V2_PL_DDR4
2V5_VP_DDR4
1V2_PL_DDR4
2V5_VP_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
2V5_VP_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
VREF_PL_DDR4
VREF_PL_DDR4
PL_DDR4_1_DQS3_71_N
PL_DDR4_1_DM3_71PL_DDR4_1_DM2_71
PL_DDR4_1_ODT_71
PL_DDR4_1_A14_71
PL_DDR4_1_ACT#_71
PL_DDR4_1_CS#_71
VREF_PL_DDR4
PL_DDR4_1_BG0_71
PL_DDR4_1_A10_71
PL_DDR4_1_A12_71
PL_DDR4_1_BA0_71
PL_DDR4_1_A4_71PL_DDR4_1_A3_71
PL_DDR4_1_BA1_71
PL_DDR4_1_RST#_70
PL_DDR4_1_A6_71
PL_DDR4_1_A0_71PL_DDR4_1_A1_71
PL_DDR4_1_A5_71
PL_DDR4_1_A8_71
PL_DDR4_1_A2_71
PL_DDR4_1_A9_71
PL_DDR4_1_A7_71
PL_DDR4_1_A11_71
PL_DDR4_1_A13_71
PL_DDR4_1_ACT#_71
PL_DDR4_1_BG0_71
PL_DDR4_1_A14_71PL_DDR4_1_A16_71PL_DDR4_1_A15_71
PL_DDR4_1_A15_71PL_DDR4_1_A16_71
PL_DDR4_1_A3_71
PL_DDR4_1_A0_71PL_DDR4_1_A1_71PL_DDR4_1_A2_71
PL_DDR4_1_BA0_71
PL_DDR4_1_A13_71PL_DDR4_1_A12_71PL_DDR4_1_A11_71PL_DDR4_1_A10_71PL_DDR4_1_A9_71PL_DDR4_1_A8_71PL_DDR4_1_A7_71
PL_DDR4_1_A4_71PL_DDR4_1_A5_71PL_DDR4_1_A6_71
PL_DDR4_1_ODT_71PL_DDR4_1_RST#_70
PL_DDR4_1_PARITY_71PL_DDR4_1_ALERT#_70
PL_DDR4_1_ALERT#_70PL_DDR4_1_PARITY_71
PL_DDR4_1_CS#_71
1V2_PL_DDR4
VREF_PL_DDR4
1V2_PL_DDR4
PL_DDR4_1_DQS2_71_N
PL_DDR4_1_CKE_71PL_DDR4_1_CK_71_NPL_DDR4_1_CK_71_P
PL_DDR4_1_CKE_71PL_DDR4_1_CK_71_NPL_DDR4_1_CK_71_P
PL_DDR4_1_BA1_71
PL_DDR4_1_DQS3_71_P
GND
GND
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VPP
VPP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ VD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
DVD
D
A13
NCPAR
A11
A7
A9
A2
A8
ALERT_N
A5
A1A0
A6
RESET_N
TEN
BA1
A3A4
BA0
CAS_N/A15
A12/BC_N
A10/AP
BG0
VREF
CA
RAS_N/A16
CS_N
ACT_N
WE_N/A14
CK_CCK_T
ODT
CKE
DQ7DQ6DQ5
DQ3DQ2
DQ4
DQSL_T
DQ0
ZQ
DQ1
DQSL_C
NF/LDM_N/LDBI_NNF/UDM_N/UDBI_N
DQ15DQ14DQ13
DQ11DQ10
DQ12
DQ9
UDQS_TUDQS_C
DQ8
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
PL DDR TERMINATION
13 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
36.5
0.01UF
39.2 39.2 39.2 39.2 39.2 39.2 39.2 39.2 39.2 39.2 39.2 39.2
1K
4.7K
39.2 39.2 39.2 39.2 39.2 39.2 39.2 39.2
1K
39.2 39.2 39.2 39.2 39.2
36.5
39.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.239.2
36.536.5
4.7K
4.7UF 4.7UF4.7UF 4.7UF4.7UF4.7UF
0.01UF
0.1UF 0.1UF0.1UF 0.1UF 0.1UF 0.1UF0.1UF0.1UF0.1UF 0.1UF 0.1UF 0.1UF
R276R274
C709
R275R273
R224 R226 R228 R230 R232 R234 R236 R238 R240 R242 R244 R246
R280
R279
R248 R250 R252 R254 R256 R258 R260 R262
R278
R264 R266 R268 R270 R272
R271R269R267R265R263R261R259R257R255R253R251R249R247R245R243R241R239R237R235R233R231R229R227R225R223
R277
C710
C700 C704 C705 C706 C707 C708C703C702C701C693 C699C698C697C696C695C694C692C691
PL_DDR4_1_CK_71_P
1V2_PL_DDR4
PL_DDR4_1_A0_71
PL_DDR4_0_BG0_69PL_DDR4_0_BA1_69
PL_DDR4_0_A15_69PL_DDR4_0_BA0_69
PL_DDR4_0_A16_69
PL_DDR4_1_A15_71
PL_DDR4_0_A14_69
PL_DDR4_1_A16_71PL_DDR4_1_A14_71PL_DDR4_1_A13_71PL_DDR4_1_A12_71
PL_DDR4_1_BA0_71
PL_DDR4_1_CKE_71PL_DDR4_1_BG0_71PL_DDR4_1_BA1_71
PL_DDR4_1_ACT#_71PL_DDR4_1_PARITY_71PL_DDR4_1_ODT_71PL_DDR4_1_CS#_71
PL_DDR4_1_A9_71PL_DDR4_1_A8_71
PL_DDR4_1_ALERT#_70
PL_DDR4_1_CK_71_N
PL_DDR4_1_RST#_70
PL_DDR4_0_ALERT#_70
PL_DDR4_0_CK_69_PPL_DDR4_0_CK_69_N
PL_DDR4_0_PARITY_69PL_DDR4_0_ODT_69
PL_DDR4_0_ACT#_69
1V2_PL_DDR4
PL_DDR4_0_RST#_70
VTT_PL_DDR4VTT_PL_DDR4
PL_DDR4_1_A5_71PL_DDR4_1_A4_71
PL_DDR4_1_A1_71
PL_DDR4_1_A11_71
PL_DDR4_1_A6_71
PL_DDR4_1_A3_71PL_DDR4_1_A2_71
PL_DDR4_1_A10_71
PL_DDR4_1_A7_71
PL_DDR4_0_CS#_69
PL_DDR4_0_CKE_69
PL_DDR4_0_A12_69
PL_DDR4_0_A3_69PL_DDR4_0_A2_69
PL_DDR4_0_A0_69
PL_DDR4_0_A4_69
PL_DDR4_0_A1_69
PL_DDR4_0_A5_69PL_DDR4_0_A6_69
PL_DDR4_0_A8_69PL_DDR4_0_A9_69
PL_DDR4_0_A7_69
PL_DDR4_0_A10_69PL_DDR4_0_A11_69
PL_DDR4_0_A13_69
VTT_PL_DDR4
1V2_PL_DDR4
1V2_PL_DDR4
VTT_PL_DDR4
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
UG 583 PLACE NEAR CONNECTOR P1
PL HP BANK 64, 65, 66, 67VCCO 0.95V...1.9
VCCO 0.95V...1.9
14 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
100UF
XCZU11EG-1FFVF1517I
R0402L
XCZU11EG-1FFVF1517I
XCZU11EG-1FFVF1517I
2K
R0402L
R0402L
0.1UF
100UF100UF100UF
2K
240
240
499
R0402L
4.7UF 100UF
499 0.1UF
4.7UF100UF4.7UF100UF100UF4.7UF
XCZU11EG-1FFVF1517I
C296 C300
U21
R525
R523R522
C297
U21
U21 U21
C1112
C303C302C295
TP104 TP124 TP125
R524
R458
R289 C1111
TP126 TP127 TP128 TP129
C301C299C298C294C293C292
VCCO_65
IO_L19N_T3L_N1_DBC_AD9N_66GPIO_17_AGPIO_16_A
IO_L9P_T1L_N4_AD12P_67IO_L9N_T1L_N5_AD12N_67
IO_L19P_T3L_N0_DBC_AD9P_66
IO_L8P_T1L_N2_AD5P_67
JESD_SYSREF_FPGA_B_PJESD_SYSREF_FPGA_B_N
SPI_CSN_ADRV9009_ASYNCINB1_B_PSYNCINB1_B_N
RX2_ENABLE_B
RESETB_BGPIO_3_BGPIO_2_BGPIO_5_BGPIO_4_BGPIO_7_BGPIO_6_BGPIO_8_BGPIO_15_BGPIO_10_BGPIO_9_B
GPIO_18_A
GPIO_18_BGPINT_B
IO_L2N_T0L_N3_67IO_L1P_T0L_N0_DBC_67
IO_L1P_T0L_N0_DBC_65IO_L1N_T0L_N1_DBC_65
IO_L13N_T2L_N1_GC_QBC_64IO_L13P_T2L_N0_GC_QBC_64IO_L12P_T1U_N10_GC_64IO_L12N_T1U_N11_GC_64
SYNC_HMC7044_FPGARESET_HMC7044GPIO_4_HMC7044GPIO_3_HMC7044
GPIO_1_HMC7044
IO_L2N_T0L_N3_65
IO_L24N_T3U_N11_65
IO_L20N_T3L_N3_AD1N_65
IO_L14N_T2L_N3_GC_65
IO_L19P_T3L_N0_DBC_AD9P_67IO_L20N_T3L_N3_AD1N_67
IO_L20P_T3L_N2_AD1P_66
GPIO_15_A
IO_L1N_T0L_N1_DBC_67
GPIO_0_A
TEST_A
SPI_MISO
GPIO_14_AGPIO_13_A
GPIO_12_A
SPI_MISO
1V8
OSCOUT1_POSCOUT1_NSPI_CLKSPI_MOSI
1V8
IO_L14P_T2L_N2_GC_64
SPI_CSN_ADRV9009_B
GPIO_11_BGPIO_12_B
SPI_CSN_HMC7044
TX2_ENABLE_B
GPIO_1_B
SYNCOUTB1_A_N
GPIO_13_BGPIO_14_B
I2C0_SCLI2C0_SDASYNCINB1_A_P
SYNCOUTB0_B_N
SPI_MISOSPI_MOSI
SYNCINB0_A_P
IO_L12N_T1U_N11_GC_65IO_L11P_T1U_N8_GC_65IO_L11N_T1U_N9_GC_65IO_L10P_T1U_N6_QBC_AD4P_65
SYNCINB0_B_N
SYNCOUTB0_B_P
SYNCINB0_B_P
TEST_B
IO_L11P_T1U_N8_GC_67IO_L12N_T1U_N11_GC_67
SYNCOUTB0_A_P
IO_L12P_T1U_N10_GC_65
IO_T0U_N12_VRP_65
IO_T2U_N12_65
IO_L9N_T1L_N5_AD12N_65
IO_L6N_T0U_N11_AD6N_65IO_L5P_T0U_N8_AD14P_65IO_L5N_T0U_N9_AD14N_65
IO_L4N_T0U_N7_DBC_AD7N_65
IO_L3N_T0L_N5_AD15N_65IO_L2P_T0L_N2_65
IO_L24P_T3U_N10_65
IO_L23P_T3U_N8_I2C_SCLK_65
IO_L22P_T3U_N6_DBC_AD0P_65
IO_L21N_T3L_N5_AD8N_65IO_L20P_T3L_N2_AD1P_65
IO_L19P_T3L_N0_DBC_AD9P_65IO_L19N_T3L_N1_DBC_AD9N_65IO_L18P_T2U_N10_AD2P_65IO_L18N_T2U_N11_AD2N_65IO_L17P_T2U_N8_AD10P_65IO_L17N_T2U_N9_AD10N_65IO_L16P_T2U_N6_QBC_AD3P_65IO_L16N_T2U_N7_QBC_AD3N_65IO_L15P_T2L_N4_AD11P_65IO_L15N_T2L_N5_AD11N_65IO_L14P_T2L_N2_GC_65
GPINT_A
SYNCINB0_A_NSYNCOUTB1_A_P
RX2_ENABLE_A
RESETB_A
RX1_ENABLE_A
SYNCOUTB0_A_N
GPIO_16_BGPIO_17_B
IO_L12P_T1U_N10_GC_67IO_L13N_T2L_N1_GC_QBC_67IO_L13P_T2L_N0_GC_QBC_67
IO_T1U_N12_67IO_T2U_N12_67
IO_L17N_T2U_N9_AD10N_67
IO_L15P_T2L_N4_AD11P_67
IO_L14P_T2L_N2_GC_67
IO_L16P_T2U_N6_QBC_AD3P_67
IO_L14N_T2L_N3_GC_67
IO_L16N_T2U_N7_QBC_AD3N_67
IO_L24N_T3U_N11_67IO_L24P_T3U_N10_67IO_T0U_N12_VRP_67
IO_L22N_T3U_N7_DBC_AD0N_67IO_L22P_T3U_N6_DBC_AD0P_67
IO_L3P_T0L_N4_AD15P_67IO_L4N_T0U_N7_DBC_AD7N_67
IO_L6P_T0U_N10_AD6P_67
IO_L7P_T1L_N0_QBC_AD13P_67
IO_L11N_T1U_N9_GC_67IO_L10P_T1U_N6_QBC_AD4P_67
IO_T3U_N12_67
IO_L17P_T2U_N8_AD10P_67IO_L18N_T2U_N11_AD2N_67IO_L18P_T2U_N10_AD2P_67IO_L19N_T3L_N1_DBC_AD9N_67
IO_L21N_T3L_N5_AD8N_67IO_L20P_T3L_N2_AD1P_67
IO_L5N_T0U_N9_AD14N_67IO_L5P_T0U_N8_AD14P_67IO_L6N_T0U_N11_AD6N_67
IO_L2P_T0L_N2_67
IO_L15N_T2L_N5_AD11N_67
IO_L10N_T1U_N7_QBC_AD4N_67
IO_L4P_T0U_N6_DBC_AD7P_67
IO_L8P_T1L_N2_AD5P_65
IO_L4P_T0U_N6_DBC_AD7P_65
GPIO_11_A
IO_L3N_T0L_N5_AD15N_67
IO_L7N_T1L_N1_QBC_AD13N_67
IO_L8N_T1L_N3_AD5N_67
GPIO_2_AGPIO_5_AGPIO_4_A
GPIO_3_A
GPIO_1_A
CORE_CLK_A_N
GPIO_6_A
IO_L23N_T3U_N9_67IO_L23P_T3U_N8_67
IO_L21P_T3L_N4_AD8P_67
IO_L7N_T1L_N1_QBC_AD13N_65
IO_L3P_T0L_N4_AD15P_65
IO_L22N_T3U_N7_DBC_AD0N_65
IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65
IO_T3U_N12_PERSTN0_65
IO_T1U_N12_SMBALERT_65
IO_L21P_T3L_N4_AD8P_65
VREF_67
VCCO_67
VCCO_65
1V8
SYNCINB1_A_N
GPIO_7_A
CORE_CLK_A_P
SPI_CSN_ADRV9009_A
SPI_MOSI
CORE_CLK_B_PCORE_CLK_B_N
SPI_CSN_HMC7044
IO_L13P_T2L_N0_GC_QBC_65
IO_L6P_T0U_N10_AD6P_65
IO_L7P_T1L_N0_QBC_AD13P_65IO_L8N_T1L_N3_AD5N_65
IO_L9P_T1L_N4_AD12P_65IO_L10N_T1U_N7_QBC_AD4N_65
IO_L13N_T2L_N1_GC_QBC_65IO_L14N_T2L_N3_GC_64
GPIO_0_B
TX1_ENABLE_B
JESD_SYSREF_FPGA_A_NJESD_SYSREF_FPGA_A_PTX2_ENABLE_ATX1_ENABLE_A
GPIO_2_HMC7044
1V8
VREF_65
SPI_CSN_ADRV9009_B
GPIO_8_A
VCCO_671V8
SPI_CLK
GPIO_10_AGPIO_9_A
RX1_ENABLE_B
SYNCOUTB1_B_NSYNCOUTB1_B_P
AP20
AM10AR10AR9AP9
AT25
AU26
AL18 AU20
AG18
AU17
AP21
AN19
AW20AH19AH21
AU19
AN18
AL17AL21
AP6
AN11
AT16
AU16AM20
AK15
AU22
AV22
AL10
AT6
AW7
AP11
AK10
AP5AP8
AU9AR4
AR7AP7
AP19AR19
AL11AP10
AL20
AT17
AK19AK18
AV18AU18AW21AV21AW17AV17AW19
AW16AV16AV19
AM18AM19AM21
AN21AP17AN17
AR20
AT20
AG19AG20AJ20
AJ19
AG21
AV11AU11AW14AW15AW10AW11
AV14AU13AU14AW12AV12AU10AT10AT11
AP12AT13AR13AR14AP14AR15AP15AN12AN13 AP16
AN16AM14AL15AN14AM15AM13AL13AM16AL16AK13AK14AK17AJ17AK12AJ12AJ16AH16AJ14AH14
AJ15AU15AT15AL12AH17
AV3AU3AW2AV2AT2AR2AU1AT1AT3AR3AP1AP2AW9AV9AW6
AU4AU5AW4AV4
AU6AV7AV8AT7AT8 AT5
AU8
AP4
AR6
AT9
AW27AW26AW22
AV27AV26AW25AW24AU25AU24AV24AV23
AT26AT22AR22
AR25AT23AR23AP26AP25AR24AP24AN24AN23 AP22
AN22AN26AM26AL23AL22AM25AL25AM24AM23AK25AK24AG23AG22
AJ25AJ22AH22AJ24AH24AK23AK22AU23AT27AL26AH23
AL24
AP23
AG24
AP18
AL19
AU21
AJ26
AK20
AR18
AV13
AT18
AV6
AR12AT12
AR8
AN10
AM11AP3
AJ21
AW5
AK11
AR5
AR17AH18
AK16
AN15
AT14
AG16
AT21
GND
GND
GND
GND
GND
GND
GND
VREF
_67
VCCO
_67
VCCO
_67
VCCO
_67
IO_T3U_N12_67IO_T2U_N12_67IO_T1U_N12_67
IO_T0U_N12_VRP_67
IO_L9P_T1L_N4_AD12P_67IO_L9N_T1L_N5_AD12N_67IO_L8P_T1L_N2_AD5P_67IO_L8N_T1L_N3_AD5N_67IO_L7P_T1L_N0_QBC_AD13P_67IO_L7N_T1L_N1_QBC_AD13N_67IO_L6P_T0U_N10_AD6P_67IO_L6N_T0U_N11_AD6N_67IO_L5P_T0U_N8_AD14P_67IO_L5N_T0U_N9_AD14N_67IO_L4P_T0U_N6_DBC_AD7P_67IO_L4N_T0U_N7_DBC_AD7N_67IO_L3P_T0L_N4_AD15P_67IO_L3N_T0L_N5_AD15N_67IO_L2P_T0L_N2_67IO_L2N_T0L_N3_67
IO_L24P_T3U_N10_67IO_L24N_T3U_N11_67
IO_L23P_T3U_N8_67IO_L23N_T3U_N9_67
IO_L22P_T3U_N6_DBC_AD0P_67IO_L22N_T3U_N7_DBC_AD0N_67
IO_L21P_T3L_N4_AD8P_67IO_L21N_T3L_N5_AD8N_67IO_L20P_T3L_N2_AD1P_67IO_L20N_T3L_N3_AD1N_67
IO_L1P_T0L_N0_DBC_67IO_L1N_T0L_N1_DBC_67
IO_L19P_T3L_N0_DBC_AD9P_67IO_L19N_T3L_N1_DBC_AD9N_67
IO_L18P_T2U_N10_AD2P_67IO_L18N_T2U_N11_AD2N_67IO_L17P_T2U_N8_AD10P_67IO_L17N_T2U_N9_AD10N_67
IO_L16P_T2U_N6_QBC_AD3P_67IO_L16N_T2U_N7_QBC_AD3N_67
IO_L15P_T2L_N4_AD11P_67IO_L15N_T2L_N5_AD11N_67
IO_L14P_T2L_N2_GC_67IO_L14N_T2L_N3_GC_67IO_L13P_T2L_N0_GC_QBC_67
IO_L13N_T2L_N1_GC_QBC_67IO_L12P_T1U_N10_GC_67IO_L12N_T1U_N11_GC_67IO_L11P_T1U_N8_GC_67IO_L11N_T1U_N9_GC_67IO_L10P_T1U_N6_QBC_AD4P_67IO_L10N_T1U_N7_QBC_AD4N_67
VREF
_66
VCCO
_66
VCCO
_66
VCCO
_66
IO_T3U_N12_66IO_T2U_N12_66IO_T1U_N12_66
IO_T0U_N12_VRP_66
IO_L9P_T1L_N4_AD12P_66IO_L9N_T1L_N5_AD12N_66IO_L8P_T1L_N2_AD5P_66IO_L8N_T1L_N3_AD5N_66IO_L7P_T1L_N0_QBC_AD13P_66IO_L7N_T1L_N1_QBC_AD13N_66IO_L6P_T0U_N10_AD6P_66IO_L6N_T0U_N11_AD6N_66IO_L5P_T0U_N8_AD14P_66IO_L5N_T0U_N9_AD14N_66IO_L4P_T0U_N6_DBC_AD7P_66IO_L4N_T0U_N7_DBC_AD7N_66IO_L3P_T0L_N4_AD15P_66IO_L3N_T0L_N5_AD15N_66IO_L2P_T0L_N2_66IO_L2N_T0L_N3_66
IO_L24P_T3U_N10_66IO_L24N_T3U_N11_66
IO_L23P_T3U_N8_66IO_L23N_T3U_N9_66
IO_L22P_T3U_N6_DBC_AD0P_66IO_L22N_T3U_N7_DBC_AD0N_66
IO_L21P_T3L_N4_AD8P_66IO_L21N_T3L_N5_AD8N_66IO_L20P_T3L_N2_AD1P_66IO_L20N_T3L_N3_AD1N_66
IO_L1P_T0L_N0_DBC_66IO_L1N_T0L_N1_DBC_66
IO_L19P_T3L_N0_DBC_AD9P_66IO_L19N_T3L_N1_DBC_AD9N_66
IO_L18P_T2U_N10_AD2P_66IO_L18N_T2U_N11_AD2N_66IO_L17P_T2U_N8_AD10P_66IO_L17N_T2U_N9_AD10N_66
IO_L16P_T2U_N6_QBC_AD3P_66IO_L16N_T2U_N7_QBC_AD3N_66
IO_L15P_T2L_N4_AD11P_66IO_L15N_T2L_N5_AD11N_66
IO_L14P_T2L_N2_GC_66IO_L14N_T2L_N3_GC_66IO_L13P_T2L_N0_GC_QBC_66
IO_L13N_T2L_N1_GC_QBC_66IO_L12P_T1U_N10_GC_66IO_L12N_T1U_N11_GC_66IO_L11P_T1U_N8_GC_66IO_L11N_T1U_N9_GC_66IO_L10P_T1U_N6_QBC_AD4P_66IO_L10N_T1U_N7_QBC_AD4N_66
VREF
_65
VCCO
_65
VCCO
_65
VCCO
_65
IO_T3U_N12_PERSTN0_65IO_T2U_N12_65
IO_T1U_N12_SMBALERT_65IO_T0U_N12_VRP_65
IO_L9P_T1L_N4_AD12P_65IO_L9N_T1L_N5_AD12N_65IO_L8P_T1L_N2_AD5P_65IO_L8N_T1L_N3_AD5N_65IO_L7P_T1L_N0_QBC_AD13P_65IO_L7N_T1L_N1_QBC_AD13N_65IO_L6P_T0U_N10_AD6P_65IO_L6N_T0U_N11_AD6N_65IO_L5P_T0U_N8_AD14P_65IO_L5N_T0U_N9_AD14N_65IO_L4P_T0U_N6_DBC_AD7P_65IO_L4N_T0U_N7_DBC_AD7N_65IO_L3P_T0L_N4_AD15P_65IO_L3N_T0L_N5_AD15N_65IO_L2P_T0L_N2_65IO_L2N_T0L_N3_65
IO_L24P_T3U_N10_65IO_L24N_T3U_N11_65
IO_L23P_T3U_N8_I2C_SCLK_65IO_L23N_T3U_N9_PERSTN1_I2C_SDA_65
IO_L22P_T3U_N6_DBC_AD0P_65IO_L22N_T3U_N7_DBC_AD0N_65
IO_L21P_T3L_N4_AD8P_65IO_L21N_T3L_N5_AD8N_65IO_L20P_T3L_N2_AD1P_65IO_L20N_T3L_N3_AD1N_65
IO_L1P_T0L_N0_DBC_65IO_L1N_T0L_N1_DBC_65
IO_L19P_T3L_N0_DBC_AD9P_65IO_L19N_T3L_N1_DBC_AD9N_65
IO_L18P_T2U_N10_AD2P_65IO_L18N_T2U_N11_AD2N_65IO_L17P_T2U_N8_AD10P_65IO_L17N_T2U_N9_AD10N_65
IO_L16P_T2U_N6_QBC_AD3P_65IO_L16N_T2U_N7_QBC_AD3N_65
IO_L15P_T2L_N4_AD11P_65IO_L15N_T2L_N5_AD11N_65
IO_L14P_T2L_N2_GC_65IO_L14N_T2L_N3_GC_65IO_L13P_T2L_N0_GC_QBC_65
IO_L13N_T2L_N1_GC_QBC_65IO_L12P_T1U_N10_GC_65IO_L12N_T1U_N11_GC_65IO_L11P_T1U_N8_GC_65IO_L11N_T1U_N9_GC_65IO_L10P_T1U_N6_QBC_AD4P_65IO_L10N_T1U_N7_QBC_AD4N_65
VREF
_64
VCCO
_64
VCCO
_64
VCCO
_64
IO_T3U_N12_64IO_T2U_N12_64IO_T1U_N12_64
IO_T0U_N12_VRP_64
IO_L9P_T1L_N4_AD12P_64IO_L9N_T1L_N5_AD12N_64IO_L8P_T1L_N2_AD5P_64IO_L8N_T1L_N3_AD5N_64IO_L7P_T1L_N0_QBC_AD13P_64IO_L7N_T1L_N1_QBC_AD13N_64IO_L6P_T0U_N10_AD6P_64IO_L6N_T0U_N11_AD6N_64IO_L5P_T0U_N8_AD14P_64IO_L5N_T0U_N9_AD14N_64IO_L4P_T0U_N6_DBC_AD7P_64IO_L4N_T0U_N7_DBC_AD7N_64IO_L3P_T0L_N4_AD15P_64IO_L3N_T0L_N5_AD15N_64IO_L2P_T0L_N2_64IO_L2N_T0L_N3_64
IO_L24P_T3U_N10_64IO_L24N_T3U_N11_64
IO_L23P_T3U_N8_64IO_L23N_T3U_N9_64
IO_L22P_T3U_N6_DBC_AD0P_64IO_L22N_T3U_N7_DBC_AD0N_64
IO_L21P_T3L_N4_AD8P_64IO_L21N_T3L_N5_AD8N_64IO_L20P_T3L_N2_AD1P_64IO_L20N_T3L_N3_AD1N_64
IO_L1P_T0L_N0_DBC_64IO_L1N_T0L_N1_DBC_64
IO_L19P_T3L_N0_DBC_AD9P_64IO_L19N_T3L_N1_DBC_AD9N_64
IO_L18P_T2U_N10_AD2P_64IO_L18N_T2U_N11_AD2N_64IO_L17P_T2U_N8_AD10P_64IO_L17N_T2U_N9_AD10N_64
IO_L16P_T2U_N6_QBC_AD3P_64IO_L16N_T2U_N7_QBC_AD3N_64
IO_L15P_T2L_N4_AD11P_64IO_L15N_T2L_N5_AD11N_64
IO_L14P_T2L_N2_GC_64IO_L14N_T2L_N3_GC_64IO_L13P_T2L_N0_GC_QBC_64
IO_L13N_T2L_N1_GC_QBC_64IO_L12P_T1U_N10_GC_64IO_L12N_T1U_N11_GC_64IO_L11P_T1U_N8_GC_64IO_L11N_T1U_N9_GC_64IO_L10P_T1U_N6_QBC_AD4P_64IO_L10N_T1U_N7_QBC_AD4N_64
GNDGNDGNDGND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
PLACE NEAR ZYNQ
PLACE NEAR ZYNQ
BANK 68
100OHM DIFFERENTIAL TRACES
PL HP BANK 68, 69, 70, 71VCCO 0.95V...1.9
BANK 69
PLACE DIRECTLY UNDERNEATH THE PAD
BANK 70
PLACE DIRECTLY UNDERNEATH THE PADPLACE DIRECTLY UNDERNEATH THE PAD
BANK 71
100OHM DIFFERENTIAL TRACES
15 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
0.1UF
XCZU11EG-1FFVF1517I
0.1UF
5
6
XCZU11EG-1FFVF1517I
100UF100UF 100UF
0.01UF 0.01UF
100UF4.7UF
XCZU11EG-1FFVF1517I
100UF
XCZU11EG-1FFVF1517I
0.1UF499
R0402L
499
R0402L
DNI
240240
240
0
DNIDNI
0100
100
0.01UF
100UF
0.01UF
4.7UF
0.01UF
4.7UF
7
100UF
0.01UF
100UF4.7UF
499
DNI
0.1UF
0R0402L
C360
U21U21
C437
C446C445C440C436C433C431
U21
C447
U21
C439 C449R482 R484
R485
R487
R126 R128
R454
R483 R486R456
R457
C430
C429
C432 C435
C434
C443
C438
C441
C444C442
C448
PL_DDR4_1_DQ14_70
PL_DDR4_1_DQ15_70PL_DDR4_1_DQ11_70
PL_DDR4_1_DQ9_70PL_DDR4_1_DQ13_70PL_DDR4_1_DQ12_70PL_DDR4_1_DQ10_70
PL_DDR4_0_DQS3_70_NPL_DDR4_0_DQ31_70
PL_DDR4_0_DQS3_70_PPL_DDR4_0_DQ25_70
PL_DDR4_0_DM0_69PL_DDR4_0_CS#_69PL_DDR4_0_CK_69_PPL_DDR4_0_CK_69_NPL_DDR4_0_CKIN_69_P
PL_DDR4_0_DQ26_70
PL_DDR4_1_DQ8_70
PL_DDR4_1_DM1_70
PL_DDR4_1_DQ6_70
PL_DDR4_1_DQS0_70_PPL_DDR4_1_DQS0_70_NPL_DDR4_0_DQ27_70
PL_DDR4_0_DQ29_70PL_DDR4_0_DQ24_70PL_DDR4_0_DQ28_70
PL_DDR4_0_DQ16_70
PL_DDR4_0_DM3_70
PL_DDR4_0_DQ18_70PL_DDR4_0_DQ21_70PL_DDR4_0_DQ17_70PL_DDR4_0_DQS2_70_PPL_DDR4_0_DQS2_70_NPL_DDR4_0_DQ23_70
PL_DDR4_0_DQ20_70
PL_DDR4_0_DQ4_69
PL_DDR4_0_CKIN_69_NPL_DDR4_0_BA1_69
PL_DDR4_0_A4_69PL_DDR4_0_A7_69PL_DDR4_0_A6_69PL_DDR4_0_A9_69
PL_DDR4_0_A5_69
PL_DDR4_0_A1_69PL_DDR4_0_A0_69
PL_DDR4_0_A10_69PL_DDR4_0_A13_69PL_DDR4_0_A12_69PL_DDR4_0_A16_69PL_DDR4_0_A14_69PL_DDR4_0_BA0_69PL_DDR4_0_A15_69PL_DDR4_0_BG0_69
PL_DDR4_0_DQ12_69PL_DDR4_0_DQ9_69
PL_DDR4_0_DQS1_69_PPL_DDR4_0_DQS1_69_N
PL_DDR4_0_DQ6_69PL_DDR4_0_DQ2_69
PL_DDR4_0_DQ0_69
PL_DDR4_0_DQ1_69
PL_DDR4_0_DQS0_69_N
PL_DDR4_0_DQ3_69
PL_DDR4_0_DQS0_69_P
PL_DDR4_0_DQ5_69PL_DDR4_0_DQ7_69
PL_DDR4_0_DQ10_69PL_DDR4_0_DQ14_69PL_DDR4_0_DQ13_69PL_DDR4_0_DQ11_69
PL_DDR4_0_DQ15_69
PL_DDR4_0_DQ8_69
PL_DDR4_0_ACT#_69PL_DDR4_0_PARITY_69
PL_DDR4_0_ODT_69
VCCO_68
VREF_PL_DDR4
PL_DDR4_1_BA0_71
1V2_PL_DDR4
PL_DDR4_1_RST#_70PL_DDR4_1_ALERT#_70PL_DDR4_0_ALERT#_70
PL_DDR4_1_CKE_71PL_DDR4_1_A10_71PL_DDR4_1_ACT#_71
PL_DDR4_1_CK_71_PPL_DDR4_1_CK_71_NPL_DDR4_1_BG0_71PL_DDR4_1_PARITY_71
IO_L19N_T3L_N1_DBC_AD9N_68
PL_DDR4_0_A8_69
IO_L14N_T2L_N3_GC_68IO_L14P_T2L_N2_GC_68
PL_DDR4_0_CKIN_69_PPL_DDR4_0_CKIN_69_N
PL_DDR4_1_DQS1_70_PPL_DDR4_1_DQS1_70_N
IO_L20N_T3L_N3_AD1N_68IO_L20P_T3L_N2_AD1P_68IO_L21N_T3L_N5_AD8N_68IO_L21P_T3L_N4_AD8P_68IO_L22N_T3U_N7_DBC_AD0N_68
PL_DDR4_1_A16_71PL_DDR4_1_BA1_71
PL_DDR4_1_A15_71PL_DDR4_1_A13_71PL_DDR4_1_A14_71
PL_DDR4_0_A11_69
IO_L13P_T2L_N0_GC_QBC_68IO_L13N_T2L_N1_GC_QBC_68
PL_DDR4_1_A5_71
PL_DDR4_1_A8_71PL_DDR4_1_A9_71
PL_DDR4_1_A7_71PL_DDR4_1_A4_71
PL_DDR4_1_A3_71
PL_DDR4_1_A1_71
PL_DDR4_1_A2_71
PL_DDR4_1_A0_71
PL_DDR4_0_A3_69PL_DDR4_0_A2_69
PL_DDR4_0_CKE_69PL_DDR4_0_DM1_69
1V2_PL_DDR4
IO_L8N_T1L_N3_AD5N_68
IO_L6P_T0U_N10_AD6P_68
IO_L5P_T0U_N8_AD14P_68
IO_L7P_T1L_N0_QBC_AD13P_68
IO_L9N_T1L_N5_AD12N_68IO_L8P_T1L_N2_AD5P_68
IO_L10N_T1U_N7_QBC_AD4N_68
IO_L6N_T0U_N11_AD6N_68
IO_L1N_T0L_N1_DBC_68IO_L1P_T0L_N0_DBC_68
IO_L12N_T1U_N11_GC_68
IO_L10P_T1U_N6_QBC_AD4P_68
IO_T1U_N12_68
IO_L23N_T3U_N9_68IO_L22P_T3U_N6_DBC_AD0P_68
IO_L9P_T1L_N4_AD12P_68
IO_L4N_T0U_N7_DBC_AD7N_68IO_L3P_T0L_N4_AD15P_68
IO_L5N_T0U_N9_AD14N_68IO_L4P_T0U_N6_DBC_AD7P_68
IO_L7N_T1L_N1_QBC_AD13N_68
PL_DDR4_1_A11_71PL_DDR4_1_A12_71
PL_DDR4_1_A6_71
PL_DDR4_1_CKIN_71_P
IO_L18P_T2U_N10_AD2P_68
IO_L19P_T3L_N0_DBC_AD9P_68
IO_L15P_T2L_N4_AD11P_68
IO_L17P_T2U_N8_AD10P_68IO_L17N_T2U_N9_AD10N_68
IO_L16N_T2U_N7_QBC_AD3N_68
IO_L15N_T2L_N5_AD11N_68
IO_L16P_T2U_N6_QBC_AD3P_68
IO_L18N_T2U_N11_AD2N_68
PL_DDR4_1_DQ2_70
VCCO_68
PL_DDR4_1_DM2_71PL_DDR4_1_CS#_71
PL_DDR4_1_DQ16_71PL_DDR4_1_DQ20_71
PL_DDR4_1_DQ21_71
PL_DDR4_1_DQS2_71_NPL_DDR4_1_DQS2_71_P
PL_DDR4_1_DQ23_71
PL_DDR4_1_DQ19_71PL_DDR4_1_DQ17_71
PL_DDR4_1_DQ22_71PL_DDR4_1_DQ18_71
PL_DDR4_1_DQS3_71_NPL_DDR4_1_DQS3_71_P
PL_DDR4_1_CKIN_71_N
PL_DDR4_1_DQ27_71
PL_DDR4_1_DQ26_71
PL_DDR4_0_DQ22_70PL_DDR4_0_DM2_70PL_DDR4_0_RST#_70
IO_T3U_N12_68IO_T2U_N12_68
IO_T0U_N12_VRP_68IO_L24P_T3U_N10_68IO_L24N_T3U_N11_68IO_L23P_T3U_N8_68
VREF_68
IO_L3N_T0L_N5_AD15N_68IO_L2P_T0L_N2_68IO_L2N_T0L_N3_68
PL_DDR4_0_DQ19_70
IO_L11P_T1U_N8_GC_68IO_L11N_T1U_N9_GC_68
VREF_PL_DDR4
1V2_PL_DDR4
IO_L12P_T1U_N10_GC_68
VREF_PL_DDR4
1V2_PL_DDR4
PL_DDR4_1_DM0_70
1V2_PL_DDR41V2_PL_DDR4
1V2_PL_DDR4
PL_DDR4_1_DQ5_70PL_DDR4_1_DQ3_70PL_DDR4_1_DQ4_70
1V2_PL_DDR4
PL_DDR4_0_DQ30_70
PL_DDR4_1_DQ0_70PL_DDR4_1_DQ7_70
PL_DDR4_1_CKIN_71_PPL_DDR4_1_CKIN_71_N
PL_DDR4_1_DQ1_70
1V2_PL_DDR4
PL_DDR4_1_DQ31_71PL_DDR4_1_DQ29_71
PL_DDR4_1_DQ24_71PL_DDR4_1_DQ25_71
PL_DDR4_1_DQ30_71PL_DDR4_1_DQ28_71PL_DDR4_1_DM3_71PL_DDR4_1_ODT_71
E17G19
J19
B24C21
D24F22F21
C17
C19K15
C24
E30
K27J30D31C26M25L25
J26J27
F26H26H27G30G31H28H29
L22
K22
L26M26B30
C22
E33
G23H23
L23
A33D32
K24
D26
F30
J20E22C23N22N23L20K20
M20L21K23
N21M21J22H22J21H21J24H24G20G21G24G25
F23E23
F25E25E24D25B23
A25A26B21A21B25B26
A23
F19
C20
D20D19K18N17B20A20B16A16
A17
C16B19B18
C18
E20
F18
G18F17F16H19H18H17
J16H16K17J17
J15
L18M15L15L17L16N16M16
N18N14
M24
J28
F29
C30
L27L28
K25J25K29K30
G26
G28G29E27E28F27F28
D27D29D30E29
F31C27B28B29
C28C29A30A31A27A28
B31
J31
G32
E36
D33
B36C33
D37A37A38C34B35A35A36C37B38C38C39D36
C32B33B34E32
E34D34E35
D35
F36G35G36F32F33G33G34H31H32J32H33F37E37G38G39E39D39H36H37F38E38
H39
A32C36
J29K28
C31
A22
K19G16
D22D21
M14
A18
M18
H38H34
J18
N19
M19
F35
M23
J23
F24
C25
E18E19D16D17
F20
GND
GND
GNDGND
GND
GND
GND
GND
GNDGNDGND
GND
VREF
_71
VCCO
_71
VCCO
_71
VCCO
_71
IO_T3U_N12_71IO_T2U_N12_71IO_T1U_N12_71
IO_T0U_N12_VRP_71
IO_L9P_T1L_N4_AD12P_71IO_L9N_T1L_N5_AD12N_71IO_L8P_T1L_N2_AD5P_71IO_L8N_T1L_N3_AD5N_71IO_L7P_T1L_N0_QBC_AD13P_71IO_L7N_T1L_N1_QBC_AD13N_71IO_L6P_T0U_N10_AD6P_71IO_L6N_T0U_N11_AD6N_71IO_L5P_T0U_N8_AD14P_71IO_L5N_T0U_N9_AD14N_71IO_L4P_T0U_N6_DBC_AD7P_71IO_L4N_T0U_N7_DBC_AD7N_71IO_L3P_T0L_N4_AD15P_71IO_L3N_T0L_N5_AD15N_71IO_L2P_T0L_N2_71IO_L2N_T0L_N3_71
IO_L24P_T3U_N10_71IO_L24N_T3U_N11_71
IO_L23P_T3U_N8_71IO_L23N_T3U_N9_71
IO_L22P_T3U_N6_DBC_AD0P_71IO_L22N_T3U_N7_DBC_AD0N_71
IO_L21P_T3L_N4_AD8P_71IO_L21N_T3L_N5_AD8N_71IO_L20P_T3L_N2_AD1P_71IO_L20N_T3L_N3_AD1N_71
IO_L1P_T0L_N0_DBC_71IO_L1N_T0L_N1_DBC_71
IO_L19P_T3L_N0_DBC_AD9P_71IO_L19N_T3L_N1_DBC_AD9N_71
IO_L18P_T2U_N10_AD2P_71IO_L18N_T2U_N11_AD2N_71IO_L17P_T2U_N8_AD10P_71IO_L17N_T2U_N9_AD10N_71
IO_L16P_T2U_N6_QBC_AD3P_71IO_L16N_T2U_N7_QBC_AD3N_71
IO_L15P_T2L_N4_AD11P_71IO_L15N_T2L_N5_AD11N_71
IO_L14P_T2L_N2_GC_71IO_L14N_T2L_N3_GC_71IO_L13P_T2L_N0_GC_QBC_71
IO_L13N_T2L_N1_GC_QBC_71IO_L12P_T1U_N10_GC_71IO_L12N_T1U_N11_GC_71IO_L11P_T1U_N8_GC_71IO_L11N_T1U_N9_GC_71IO_L10P_T1U_N6_QBC_AD4P_71IO_L10N_T1U_N7_QBC_AD4N_71
VREF
_70
VCCO
_70
VCCO
_70
VCCO
_70
IO_T3U_N12_70IO_T2U_N12_70IO_T1U_N12_70
IO_T0U_N12_VRP_70
IO_L9P_T1L_N4_AD12P_70IO_L9N_T1L_N5_AD12N_70IO_L8P_T1L_N2_AD5P_70IO_L8N_T1L_N3_AD5N_70IO_L7P_T1L_N0_QBC_AD13P_70IO_L7N_T1L_N1_QBC_AD13N_70IO_L6P_T0U_N10_AD6P_70IO_L6N_T0U_N11_AD6N_70IO_L5P_T0U_N8_AD14P_70IO_L5N_T0U_N9_AD14N_70IO_L4P_T0U_N6_DBC_AD7P_70IO_L4N_T0U_N7_DBC_AD7N_70IO_L3P_T0L_N4_AD15P_70IO_L3N_T0L_N5_AD15N_70IO_L2P_T0L_N2_70IO_L2N_T0L_N3_70
IO_L24P_T3U_N10_70IO_L24N_T3U_N11_70
IO_L23P_T3U_N8_70IO_L23N_T3U_N9_70
IO_L22P_T3U_N6_DBC_AD0P_70IO_L22N_T3U_N7_DBC_AD0N_70
IO_L21P_T3L_N4_AD8P_70IO_L21N_T3L_N5_AD8N_70IO_L20P_T3L_N2_AD1P_70IO_L20N_T3L_N3_AD1N_70
IO_L1P_T0L_N0_DBC_70IO_L1N_T0L_N1_DBC_70
IO_L19P_T3L_N0_DBC_AD9P_70IO_L19N_T3L_N1_DBC_AD9N_70
IO_L18P_T2U_N10_AD2P_70IO_L18N_T2U_N11_AD2N_70IO_L17P_T2U_N8_AD10P_70IO_L17N_T2U_N9_AD10N_70
IO_L16P_T2U_N6_QBC_AD3P_70IO_L16N_T2U_N7_QBC_AD3N_70
IO_L15P_T2L_N4_AD11P_70IO_L15N_T2L_N5_AD11N_70
IO_L14P_T2L_N2_GC_70IO_L14N_T2L_N3_GC_70IO_L13P_T2L_N0_GC_QBC_70
IO_L13N_T2L_N1_GC_QBC_70IO_L12P_T1U_N10_GC_70IO_L12N_T1U_N11_GC_70IO_L11P_T1U_N8_GC_70IO_L11N_T1U_N9_GC_70IO_L10P_T1U_N6_QBC_AD4P_70IO_L10N_T1U_N7_QBC_AD4N_70
VREF
_69
VCCO
_69
VCCO
_69
VCCO
_69
IO_T3U_N12_69IO_T2U_N12_69IO_T1U_N12_69
IO_T0U_N12_VRP_69
IO_L9P_T1L_N4_AD12P_69IO_L9N_T1L_N5_AD12N_69IO_L8P_T1L_N2_AD5P_69IO_L8N_T1L_N3_AD5N_69IO_L7P_T1L_N0_QBC_AD13P_69IO_L7N_T1L_N1_QBC_AD13N_69IO_L6P_T0U_N10_AD6P_69IO_L6N_T0U_N11_AD6N_69IO_L5P_T0U_N8_AD14P_69IO_L5N_T0U_N9_AD14N_69IO_L4P_T0U_N6_DBC_AD7P_69IO_L4N_T0U_N7_DBC_AD7N_69IO_L3P_T0L_N4_AD15P_69IO_L3N_T0L_N5_AD15N_69IO_L2P_T0L_N2_69IO_L2N_T0L_N3_69
IO_L24P_T3U_N10_69IO_L24N_T3U_N11_69
IO_L23P_T3U_N8_69IO_L23N_T3U_N9_69
IO_L22P_T3U_N6_DBC_AD0P_69IO_L22N_T3U_N7_DBC_AD0N_69
IO_L21P_T3L_N4_AD8P_69IO_L21N_T3L_N5_AD8N_69IO_L20P_T3L_N2_AD1P_69IO_L20N_T3L_N3_AD1N_69
IO_L1P_T0L_N0_DBC_69IO_L1N_T0L_N1_DBC_69
IO_L19P_T3L_N0_DBC_AD9P_69IO_L19N_T3L_N1_DBC_AD9N_69
IO_L18P_T2U_N10_AD2P_69IO_L18N_T2U_N11_AD2N_69IO_L17P_T2U_N8_AD10P_69IO_L17N_T2U_N9_AD10N_69
IO_L16P_T2U_N6_QBC_AD3P_69IO_L16N_T2U_N7_QBC_AD3N_69
IO_L15P_T2L_N4_AD11P_69IO_L15N_T2L_N5_AD11N_69
IO_L14P_T2L_N2_GC_69IO_L14N_T2L_N3_GC_69IO_L13P_T2L_N0_GC_QBC_69
IO_L13N_T2L_N1_GC_QBC_69IO_L12P_T1U_N10_GC_69IO_L12N_T1U_N11_GC_69IO_L11P_T1U_N8_GC_69IO_L11N_T1U_N9_GC_69IO_L10P_T1U_N6_QBC_AD4P_69IO_L10N_T1U_N7_QBC_AD4N_69
VREF
_68
VCCO
_68
VCCO
_68
VCCO
_68
IO_T3U_N12_68IO_T2U_N12_68IO_T1U_N12_68
IO_T0U_N12_VRP_68
IO_L9P_T1L_N4_AD12P_68IO_L9N_T1L_N5_AD12N_68IO_L8P_T1L_N2_AD5P_68IO_L8N_T1L_N3_AD5N_68IO_L7P_T1L_N0_QBC_AD13P_68IO_L7N_T1L_N1_QBC_AD13N_68IO_L6P_T0U_N10_AD6P_68IO_L6N_T0U_N11_AD6N_68IO_L5P_T0U_N8_AD14P_68IO_L5N_T0U_N9_AD14N_68IO_L4P_T0U_N6_DBC_AD7P_68IO_L4N_T0U_N7_DBC_AD7N_68IO_L3P_T0L_N4_AD15P_68IO_L3N_T0L_N5_AD15N_68IO_L2P_T0L_N2_68IO_L2N_T0L_N3_68
IO_L24P_T3U_N10_68IO_L24N_T3U_N11_68
IO_L23P_T3U_N8_68IO_L23N_T3U_N9_68
IO_L22P_T3U_N6_DBC_AD0P_68IO_L22N_T3U_N7_DBC_AD0N_68
IO_L21P_T3L_N4_AD8P_68IO_L21N_T3L_N5_AD8N_68IO_L20P_T3L_N2_AD1P_68IO_L20N_T3L_N3_AD1N_68
IO_L1P_T0L_N0_DBC_68IO_L1N_T0L_N1_DBC_68
IO_L19P_T3L_N0_DBC_AD9P_68IO_L19N_T3L_N1_DBC_AD9N_68
IO_L18P_T2U_N10_AD2P_68IO_L18N_T2U_N11_AD2N_68IO_L17P_T2U_N8_AD10P_68IO_L17N_T2U_N9_AD10N_68
IO_L16P_T2U_N6_QBC_AD3P_68IO_L16N_T2U_N7_QBC_AD3N_68
IO_L15P_T2L_N4_AD11P_68IO_L15N_T2L_N5_AD11N_68
IO_L14P_T2L_N2_GC_68IO_L14N_T2L_N3_GC_68IO_L13P_T2L_N0_GC_QBC_68
IO_L13N_T2L_N1_GC_QBC_68IO_L12P_T1U_N10_GC_68IO_L12N_T1U_N11_GC_68IO_L11P_T1U_N8_GC_68IO_L11N_T1U_N9_GC_68IO_L10P_T1U_N6_QBC_AD4P_68IO_L10N_T1U_N7_QBC_AD4N_68
GNDGND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
PL HD BANK 88, 89
VCCO 1.14V...3.4V
16 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
XCZU11EG-1FFVF1517IXCZU11EG-1FFVF1517I
1KR0402L
0.001UF
0.001UFR0402L
1K
1K 0.001UF
R0402L
1K 0.001UFR0402L
499
1K
R0402L
R0402L
R0402L
750
0.001UF
0.001UF
3K
R0402L1K
R0402L
750
1KR0402L
R0402L
R0402L
R0402L
R0402L
R0402L R0402L
R0402L
R0402L
R0402L
3K
3K
750
3K
750
1K
499
1K
1K
499
499
1KR0402L
R0402L
R0402L
R0402L R0402L
1K 0.001UF
0.001UF
47UF
U21
C1103
R437
R430
R434 C1104
C1102R432
C1105
R439
R445
R448
C1110
C1109
R447
R446
R450
R443
R451
R442
R441
R449
R440R428
R436
R431
R438
R429
R433
R435
R444
C1106
C1108
C1107
U21
VCCO_89
IO_L4P_AD12P_89IO_L4N_AD12N_89IO_L3P_AD13P_89
IO_L1P_AD15P_89IO_L1N_AD15N_89
IO_L2N_AD14N_89
IO_L5P_HDGC_89IO_L5N_HDGC_89
IO_L6N_HDGC_89IO_L6P_HDGC_89
IO_L3N_AD13N_89IO_L2P_AD14P_89
VDDA1P3_ANLG_A_SNS_NVDDA1P3_ANLG_A_SNS_P
VDDA3P3_VCXO_SNS_PVDDA3P3_VCXO_SNS_NVDDA3P3_SNS_P
VDDA1P8_B_SNS_PVDDA1P8_B_SNS_NVDDA3P3_VCO_SNS_PVDDA3P3_VCO_SNS_NVDDA3P3_CLK_SNS_PVDDA3P3_CLK_SNS_N
VDDA1P3_ANLG_B_N
VDDA1P3_ANLG_A_N
VDDA1P8_A_SNS_P
VDDA1P8_A_SNS_N
VDDA1P3_ANLG_A_SNS_P
VDDA1P3_ANLG_A_SNS_N
VDDA1P3_ANLG_A_P
VDDA1P8_B_SNS_P
VDDA1P8_B_SNS_NVDDA1P8_B_N
VDDA3P3_VCXO_P
VDDA3P3_CLK_P
VDDA3P3_SNS_P
VDDA3P3_SNS_N
VDDA3P3_VCO_N VDDA3P3_VCO_SNS_N
VDDA3P3_VCO_P
VDDA3P3_N
VDDA1P3_ANLG_B_SNS_N
VDDA1P3_ANLG_B_P
VDDA3P3_P
VDDA1P8_A_P
VDDA1P8_B_P
VDDA1P8_A_N
1V8
VDDA1P3_ANLG_B_SNS_P
VDDA1P8_A_SNS_N
VDDA3P3_VCO_SNS_P
VDDA3P3_CLK_SNS_P
VDDA3P3_VCXO_N
VDDA3P3_CLK_SNS_N
VDDA3P3_VCXO_SNS_P
VDDA3P3_VCXO_SNS_N
VDDA3P3_CLK_N
VDDA3P3_SNS_N
VDDA1P8_A_SNS_PVDDA1P3_ANLG_B_SNS_NVDDA1P3_ANLG_B_SNS_P
C14B14
E15
K12 K13K14H13J14
F13
G14H14
E14
C13D14
J13
F14
A13
E13
D15
B13
B15A15L13
G13
G15
L12
F10 F15
H10
E11
A12A11B10A10C11B11D12C12D11D10F12E12
E10G11F11H11G10J12H12
J11K10J10
VCCO
_89
VCCO
_89
IO_L9P_AD11P_89IO_L9N_AD11N_89IO_L8P_HDGC_89IO_L8N_HDGC_89IO_L7P_HDGC_89IO_L7N_HDGC_89IO_L6P_HDGC_89
IO_L6N_HDGC_89IO_L5P_HDGC_89IO_L5N_HDGC_89IO_L4P_AD12P_89IO_L4N_AD12N_89IO_L3P_AD13P_89IO_L3N_AD13N_89IO_L2P_AD14P_89IO_L2N_AD14N_89IO_L1P_AD15P_89IO_L1N_AD15N_89 IO_L12P_AD8P_89
IO_L12N_AD8N_89IO_L11P_AD9P_89IO_L11N_AD9N_89
IO_L10P_AD10P_89IO_L10N_AD10N_89
VCCO
_88
VCCO
_88
IO_L9P_AD3P_88IO_L9N_AD3N_88
IO_L8P_HDGC_AD4P_88IO_L8N_HDGC_AD4N_88IO_L7P_HDGC_AD5P_88IO_L7N_HDGC_AD5N_88IO_L6P_HDGC_AD6P_88
IO_L6N_HDGC_AD6N_88IO_L5P_HDGC_AD7P_88IO_L5N_HDGC_AD7N_88IO_L4P_AD8P_88IO_L4N_AD8N_88IO_L3P_AD9P_88IO_L3N_AD9N_88IO_L2P_AD10P_88IO_L2N_AD10N_88IO_L1P_AD11P_88IO_L1N_AD11N_88 IO_L12P_AD0P_88
IO_L12N_AD0N_88IO_L11P_AD1P_88IO_L11N_AD1N_88IO_L10P_AD2P_88IO_L10N_AD2N_88
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
FROM ON-BOARD HMC7044
TALISE JESD INTERFACE A
TALISE JESD INTERFACE B
GTH TRANSCEIVERS
FROM ON-BOARD HMC7044
17 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
XCZU11EG-1FFVF1517I XCZU11EG-1FFVF1517I
XCZU11EG-1FFVF1517IXCZU11EG-1FFVF1517I
XCZU11EG-1FFVF1517I
XCZU11EG-1FFVF1517I
XCZU11EG-1FFVF1517I
XCZU11EG-1FFVF1517I
U21
U21
U21
U21
U21
U21
U21
U21
MGTREFCLK0N_224MGTREFCLK1P_228MGTREFCLK1N_228MGTHTXP3_228MGTHTXP2_228MGTHTXP1_228MGTHTXP0_228MGTHTXN3_228MGTHTXN2_228MGTHTXN1_228
MGTHRXP3_228MGTREFCLK0N_228
MGTHRXP2_228
MGTHTXN0_225MGTHTXN1_225MGTHTXN2_225MGTHTXN3_225MGTHTXP0_225
MGTHTXN3_224
MGTREFCLK1P_229
MGTHTXP3_229
MGTHTXP1_229
MGTREFCLK1N_229
MGTHTXP0_229
MGTREFCLK0P_229
MGTHRXN0_225MGTHRXN1_225MGTHRXN2_225MGTHRXN3_225MGTHRXP0_225MGTHRXP1_225MGTHRXP2_225MGTHRXP3_225
MGTHTXP1_225MGTHTXP2_225MGTHTXP3_225
MGTREFCLK0N_225 MGTREFCLK1N_225MGTREFCLK1P_225MGTREFCLK0P_225
MGTHTXN0_229MGTHTXN1_229MGTHTXN2_229
MGTHTXP2_229
MGTHTXN3_229
MGTHTXN0_228
MGTHRXN1_229
MGTHRXN3_228MGTHRXN2_228
MGTHRXP1_228
MGTHRXN1_228
MGTREFCLK0P_228
MGTHRXP0_228
MGTHRXN0_228
MGTHRXN3_229
JESD_SERDOUT0_B_N
MGTHRXP1_229
MGTHRXP3_229MGTHRXP2_229
MGTHRXN2_229
MGTREFCLK0N_229
MGTHRXP0_229
MGTHRXN0_229
JESD_REFCLK_FPGA_B_PJESD_REFCLK_FPGA_B_NJESD_SERDOUT3_B_PJESD_SERDOUT2_B_PJESD_SERDOUT1_B_PJESD_SERDOUT0_B_PJESD_SERDOUT3_B_NJESD_SERDOUT2_B_NJESD_SERDOUT1_B_N
MGTHTXP1_227MGTHTXP2_227MGTHTXP3_227MGTREFCLK1N_227MGTREFCLK1P_227
MGTHTXN3_227MGTHTXN2_227MGTHTXN1_227
MGTHTXP0_227
MGTHTXN0_227 JESD_SERDOUT0_A_N
MGTHTXP2_226MGTHTXP3_226MGTREFCLK1N_226
MGTHTXN3_226MGTHTXN2_226
MGTREFCLK1P_226
MGTHTXP1_226
MGTHTXN1_226
MGTHTXP0_226
MGTHTXN0_226
MGTREFCLK1N_224MGTREFCLK1P_224
MGTHTXP3_224MGTHTXP2_224
MGTHTXN2_224
MGTHTXP1_224
MGTHTXN1_224
MGTHTXP0_224
MGTHTXN0_224
MGTREFCLK0P_226
MGTREFCLK0P_227
MGTHRXP3_224
MGTHRXN3_224
MGTHRXP2_224
MGTHRXN2_224
MGTHRXP1_224
MGTHRXN1_224
MGTREFCLK0P_224
MGTHRXP0_224
MGTHRXN0_224
MGTHRXP3_227
MGTHRXN3_227
MGTHRXP2_227
MGTHRXN2_227
MGTHRXP1_227
MGTHRXN1_227
MGTREFCLK0N_227
MGTHRXP0_227
MGTHRXN0_227
MGTHRXP3_226
MGTHRXN3_226
MGTHRXP2_226
MGTHRXN2_226
MGTHRXP1_226
MGTHRXN1_226
MGTREFCLK0N_226
MGTHRXP0_226
MGTHRXN0_226
JESD_SERDIN3_B_N
JESD_REFCLK_FPGA_A_NJESD_SERDOUT3_A_PJESD_SERDOUT2_A_PJESD_SERDOUT1_A_PJESD_SERDOUT0_A_PJESD_SERDOUT3_A_NJESD_SERDOUT2_A_NJESD_SERDOUT1_A_N
JESD_SERDIN2_B_N
JESD_SERDIN0_B_NJESD_SERDIN1_B_N
JESD_SERDIN0_A_NJESD_SERDIN1_A_NJESD_SERDIN2_A_N
JESD_SERDIN0_A_PJESD_SERDIN1_A_PJESD_SERDIN2_A_PJESD_SERDIN3_A_P
JESD_REFCLK_FPGA_A_P
JESD_SERDIN3_A_N
JESD_SERDIN0_B_PJESD_SERDIN1_B_PJESD_SERDIN2_B_PJESD_SERDIN3_B_P
AH10
T6N7
R7T5
AM6
T10T9
M6
J4K2L4M2
AE12AE11
AF10AF9
AE8AF6AG8AH6AE7AF5AG7AH5
AE4AF2AG4AH2AE3AF1AG3AH1
Y10Y9
AA12AA11
U8V6W8Y6U7V5W7Y5
U4V2W4Y2U3V1W3Y1
AB10AB9
AD10AD9
AA8AB6AC8AD6AA7AB5AC7AD5
AA4AB2AC4AD2AA3AB1AC3AD1
AG12AG11AH9AJ8AK6AL8
AJ7AK5AL7AM5
AJ4AK2AL4AM2AJ3AK1AL3AM1
M10M9
N12N11
A8B6C8D6A7B5C7D5
A4B2C4D2A3B1C3D1
P10P9
R12R11
E8F6G8H6E7F5G7H5
E4F2G4H2E3F1G3H1
U12U11
J8K6L8
J7K5L7M5
J3K1L3M1
V10V9
W12W11
N8P6R8
P5
N4P2R4T2N3P1R3T1
MGTREFCLK1P_227MGTREFCLK1N_227
MGTREFCLK0P_227MGTREFCLK0N_227
MGTHTXP3_227MGTHTXP2_227MGTHTXP1_227MGTHTXP0_227MGTHTXN3_227MGTHTXN2_227MGTHTXN1_227MGTHTXN0_227
MGTHRXP3_227MGTHRXP2_227MGTHRXP1_227MGTHRXP0_227MGTHRXN3_227MGTHRXN2_227MGTHRXN1_227MGTHRXN0_227
MGTREFCLK1P_226MGTREFCLK1N_226
MGTREFCLK0P_226MGTREFCLK0N_226
MGTHTXP3_226MGTHTXP2_226MGTHTXP1_226MGTHTXP0_226MGTHTXN3_226MGTHTXN2_226MGTHTXN1_226MGTHTXN0_226
MGTHRXP3_226MGTHRXP2_226MGTHRXP1_226MGTHRXP0_226MGTHRXN3_226MGTHRXN2_226MGTHRXN1_226MGTHRXN0_226
MGTREFCLK1P_225MGTREFCLK1N_225
MGTREFCLK0P_225MGTREFCLK0N_225
MGTHTXP3_225MGTHTXP2_225MGTHTXP1_225MGTHTXP0_225MGTHTXN3_225MGTHTXN2_225MGTHTXN1_225MGTHTXN0_225
MGTHRXP3_225MGTHRXP2_225MGTHRXP1_225MGTHRXP0_225MGTHRXN3_225MGTHRXN2_225MGTHRXN1_225MGTHRXN0_225
MGTREFCLK1P_224MGTREFCLK1N_224
MGTREFCLK0P_224MGTREFCLK0N_224
MGTHTXP3_224MGTHTXP2_224MGTHTXP1_224MGTHTXP0_224MGTHTXN3_224MGTHTXN2_224MGTHTXN1_224MGTHTXN0_224
MGTHRXP3_224MGTHRXP2_224MGTHRXP1_224MGTHRXP0_224MGTHRXN3_224MGTHRXN2_224MGTHRXN1_224MGTHRXN0_224
MGTREFCLK1P_231MGTREFCLK1N_231
MGTREFCLK0P_231MGTREFCLK0N_231
MGTHTXP3_231MGTHTXP2_231MGTHTXP1_231MGTHTXP0_231MGTHTXN3_231MGTHTXN2_231MGTHTXN1_231MGTHTXN0_231
MGTHRXP3_231MGTHRXP2_231MGTHRXP1_231MGTHRXP0_231MGTHRXN3_231MGTHRXN2_231MGTHRXN1_231MGTHRXN0_231
MGTREFCLK1P_230MGTREFCLK1N_230
MGTREFCLK0P_230MGTREFCLK0N_230
MGTHTXP3_230MGTHTXP2_230MGTHTXP1_230MGTHTXP0_230MGTHTXN3_230MGTHTXN2_230MGTHTXN1_230MGTHTXN0_230
MGTHRXP3_230MGTHRXP2_230MGTHRXP1_230MGTHRXP0_230MGTHRXN3_230MGTHRXN2_230MGTHRXN1_230MGTHRXN0_230
MGTREFCLK1P_229MGTREFCLK1N_229
MGTREFCLK0P_229MGTREFCLK0N_229
MGTHTXP3_229MGTHTXP2_229MGTHTXP1_229MGTHTXP0_229MGTHTXN3_229MGTHTXN2_229MGTHTXN1_229MGTHTXN0_229
MGTHRXP3_229MGTHRXP2_229MGTHRXP1_229MGTHRXP0_229MGTHRXN3_229MGTHRXN2_229MGTHRXN1_229MGTHRXN0_229
MGTREFCLK1P_228MGTREFCLK1N_228
MGTREFCLK0P_228MGTREFCLK0N_228
MGTHTXP3_228MGTHTXP2_228MGTHTXP1_228MGTHTXP0_228MGTHTXN3_228MGTHTXN2_228MGTHTXN1_228MGTHTXN0_228
MGTHRXP3_228MGTHRXP2_228MGTHRXP1_228MGTHRXP0_228MGTHRXN3_228MGTHRXN2_228MGTHRXN1_228MGTHRXN0_228
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
VCCAUX/VCCAUX_IO DECOUPLING VCCINT/VCCINT_IO/VCCBRAM DECOUPLING
PLACE AS MANY 4.7UF AS POSSIBLE UNDERNEATH THE BGAROUTE 0V85_PL_SNS_P/N FROM A CAPAITOR UNDERNEATH THE BGA
ROUTE 0V85_PS_SNS_P/N FROM A CAPAITOR UNDERNEATH THE BGAVCCPSPLL DECOUPLINGPLACE AS MANY 4.7UF AS POSSIBLE UNDERNEATH THE BGA
VCCPSINTFP/LP DECOUPLING
ZYNQ ULTRASCALE POWER
VCCPSAUX DECOUPLING
18 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
470UF470UF
100UF 4.7UF
4.7UF 0.47UF
0.47UF
4.7UF 4.7UF 4.7UF 4.7UF4.7UF 4.7UF
4.7UF
4.7UF 4.7UF
4.7UF
4.7UF 4.7UF 4.7UF
4.7UF4.7UF4.7UF
0.1UF
100UF 100UF
100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF 100UF
100UF
100UF 100UF100UF100UF100UF100UF
100UF
100UF 100UF 100UF 100UF100UF 100UF
470UF 470UF 470UF 470UF 470UF 470UF
120OHM
600OHMS
600OHMSXCZU11EG-1FFVF1517I
C267
C281
C260C257
C241 C248
C243
U21
C244C238 C240 C250 C252
C237 C239 C242 C246 C249 C251 C253 C254 C255
C258 C261
E9
E8
C247
C245
E7
C265C264C263C262C259C256
C270 C273 C276 C291C290C289C288C287
C286C284C278C275C272C269C266
C283C280C277C274C271C268
C285C282C279
1V8_VCCPSAUX
1V8_VCCPSAUX
VCC_PSBATT
1V8_VCCPSAUX
0V85_PSINTFP
0V85_PSINTLP
1V8
0V85_PSINTLP
1V8_VCCAUX
GND_ADC
0V85_PL
0V85_PS_SNS_N
0V85_PS_SNS_P0V85_PSINTFP0V85_PSINTLP
0V85_PL_SNS_P
VCC_ADC
VCC_PSPLL
1V8
1V2_MGTAVTT
VCC_PSPLL
1V8
0V85_PSINTLP
0V85_PSINTFP
VCC_PSPLL
0V85_PL_SNS_N
0V85_PL
0V85_PL
VCC_ADC
0V85_PL1V8_VCCAUX0V85_PSINTFP
0V85_PS
1V8_VCCAUX
V14
AB14
AD29
AB29
T16
AC29 R19R21
AC27AD30
AE25
AA27
AD26
P16
AE21
AD18
AF18
P14
R17
Y14
T14
Y24
Y22
Y18
Y16
W23
W21
W17
V24
V22
V18
V16
U23
U21
U19
U17
T24
T22
T20
T18
R23
R15P24P22P20P18
AF22AF20
AF16AF14
AE19AE17AE15AD22AD20
AD16AD14
AC21
AC19
AC17
AB22
AB20
AB18
AB16
AA21
AA17
W15U15
AC15
AA15
W25U25
R25
P25
Y26
V26
T26
P26
V20
AA26
AA25
AA23AC24AC23AB26AB25AB24AB23AE28AE27
AE24AE23AD27
AD25AD24AC26AA28
VCCI
NT_I
OVC
CINT
_IO
VCCI
NT_I
OVC
CINT
_IO
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NT
VCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINTVCCINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CINT
VCCI
NTVC
CBRA
MVC
CBRA
MVC
CBRA
MVC
CBRA
MVC
CAUX
_IO
VCCA
UX_I
OVC
CAUX
_IO
VCCA
UX_I
OVC
CAUX
VCCA
UXVC
CAUX
VCCA
UXVC
CADC
VCC_
PSPL
LVC
C_PS
PLL
VCC_PSPLLVCC_PSINTLPVCC_PSINTLPVCC_PSINTLPVCC_PSINTLPVCC_PSINTLPVCC_PSINTLPVCC_PSINTFP_DDRVCC_PSINTFP_DDRVCC_PSINTFP_DDRVCC_PSINTFPVCC_PSINTFPVCC_PSINTFPVCC_PSINTFPVCC_PSINTFPVCC_PSINTFPVCC_PSINTFPVCC_PSDDR_PLLVCC_PSDDR_PLLVCC_PSBATTVCC_PSAUXVCC_PSAUXVCC_PSAUXVCC_PSAUX
GNDGND GND
GND
GND
GND
GND
GND
GNDGND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
NEED TO BE CONNECTED TO GND IF NOT USED
DISABLE PULL-UP DURING CONFIG
BANK 227
BANK 226
GT POWER
USE INTERNAL REFERENCE
BANK 228BANK 224
BANK 225
PLACE AS MANY 4.7UF AS POSSIBLE UNDERNEATH THE BGAROUTE 0V85_PS_SNS_P/N FROM A CAPAITOR UNDERNEATH THE BGA
BANK 229
BANK 230
BANK 231
19 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
DNI
0
0
1K
DNI
DNI
0
4.7UF 4.7UF 0.22UF0.22UF 0.47UF
4.7UF
0.22UF 0.47UF 4.7UF 0.22UF4.7UF0.22UF
4.7UF 0.22UF
4.7UF 0.22UF 0.47UF 4.7UF
100UF 100UF
0.22UF
4.7UF
0.22UF 0.47UF 4.7UF
4.7UF0.22UF4.7UF0.22UF 0.47UF
0.47UF
0.47UF
0.47UF
0.47UF 0.47UF0.47UF
0.22UF
4.7UF
100
0.1500
XCZU11EG-1FFVF1517I
DNI DNI100UF 100UF 100UF 100UF100UF 100UF 100UF
100UF
DNI DNI DNI
100UF100UF100UF100UF
100UF
100UF100UF100UF100UF100UF
0.22UF
0.22UF
0.22UF
0.22UF
0.22UF
0.01UF 0.01UF
0.01UF 0.01UF 0.01UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF
4.7UF 4.7UF
4.7UF
4.7UF
R453
R452
R282
R283
R285
R286
C770 C775 C780C724 C732 C742
C747
C748
C755
C756
C719 C727 C735
C718
C723 C731
C746C721C715
C740
U21
C772
C773
C774
C722
C759 C762C752
C782C781C776C771C766
C712 C714 C720 C728 C736 C744 C751 C754 C761 C764
C763C760C753C750C743C713C711
C749
C741 C757 C769 C779 C785
C786 C790
C789
C794
C793
C758
C717
C767
C768
C777
C778 C784
C783
C788 C792
C787 C791
C730C716
C739C729
R284
C738C734C726
C765C745C737C733C725
R281
0V9_MGTAVCC
1V2_MGTAVTT
1V2_MGTAVTTMGTVCCAUX
0V9_MGTAVCC_SNS_N0V9_MGTAVCC_SNS_P
0V9_MGTAVCC 1V2_MGTAVTT
0V9_MGTAVCC
MGTVCCAUX
1V8_MGTRAVTT
0V9_MGTAVCC
1V2_MGTAVTT
VCC_ADC
0V9_MGTAVCC
0V9_MGTAVCC
GND_ADC
1V2_MGTAVTT
1V8_MGTRAVTT
MGTVCCAUX
1V2_MGTAVTT0V9_MGTAVCC 1V2_MGTAVTT
0V9_MGTAVCC
MGTAVTTRCAL
1V8_MGTRAVTT
0V85_MGTRAVCC
MGTVCCAUX
1V8_VCCAUX
0V85_MGTRAVCC
1V2_MGTAVTT
1V2_MGTAVTT
1V2_MGTAVTT
1V2_MGTAVTT
0V9_MGTAVCC
MGTVCCAUX MGTVCCAUX
MGTVCCAUX
MGTVCCAUX
MGTVCCAUX
MGTVCCAUX
0V9_MGTAVCC
0V9_MGTAVCC
0V85_PL
MGTAVTTRCAL
0V9_MGTAVCC GND_ADC
AK8
E6F8
P8N6
AE10
AA10
Y20W19
W20Y19AG15
U33
Y34V34
AA36W32
AB34AA32
AG14
AG26
AG25
AF27
AF26
AF25
AF23
AF12AD12AB12
Y12V12T12
AC12
AC11
Y8W6V8U6
AL6AJ6AG6AF8AE6AD8AC6AB8AA6
T8R6
L6J6G6
D8C6B8A6
AM8
AH8AG10
AC10
W10
U10
R10
P12N10M8K8H8
AA20AA19
GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND GND GND
GNDGNDGND
GND
GND
GND
NCNCNCNCNCNCPS_MGTRAVTTPS_MGTRAVTTPS_MGTRAVTTPS_MGTRAVCCPS_MGTRAVCCPS_MGTRAVCC
MG
TAVT
TRCA
L_R
VREFPVREFN
VPVN
PS_MGTRREF_505POR_OVERRIDE
MGTVCCAUX_RSMGTVCCAUX_RSMGTVCCAUX_RSMGTVCCAUX_RNMGTVCCAUX_RNMGTVCCAUX_RN
MGTRREF_R
MGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RSMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVTT_RNMGTAVCC_RSMGTAVCC_RSMGTAVCC_RSMGTAVCC_RS
MG
TAVC
C_RS
MG
TAVC
C_RS
MG
TAVC
C_RS
MG
TAVC
C_RN
MG
TAVC
C_RN
MG
TAVC
C_RN
MGTAVCC_RNMGTAVCC_RNMGTAVCC_RNMGTAVCC_RNMGTAVCC_RNDXPDXNPUDC_B
GNDGND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
ZYNQ ULTRASCALE POWER
20 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
XCZU11EG-1FFVF1517I
U21B22
B17
B12
B9 B7 B4 B3 AW38
AW33
AW28
AW23
AW18
AW13
AW8
AW3
AV39
AV30
AV25
AV20
AV15
AV10
AV5
AV1
AU37
AU32
AU27
AU12
AU7
AU2
AT29
AT24
AT19
AT4
AR36
AR31
AR26
AR21
AR16
AR11
AR1
AP28
AP13
AN35
AN30
AN25
AN20
AN9
AN8
AN7
AN6
AN5
AN4
AN3
AN2AN1AM37AM32AM27AM22AM17AM12AM9AM7AM4AM3AL39AL29AL14AL9AL5AL2AL1AK36AK31AK26AK21AK9AK7AK4AK3AJ38AJ33AJ23AJ18AJ13AJ11AJ10AJ9AJ5AJ2AJ1AH35AH30AH26AH25AH20AH15AH13AH12AH11AH7AH4AH3AG37AG32
AG27
AG17
AG13
AG9
AG5
AG2
AG1
AF39
AF34
AF28
AF24
AF21
AF19
AF17
AF15
AF13
AF11AF
7AF
4AF
3AE
36AE
31AE
26AE
22AE
20AE
18AE
16AE
14AE
13AE
9AE
5AE
2AE
1AD
38AD
33AD
28AD
23AD
21AD
19AD
17AD
15AD
13AD
11AD
7AD
4AD
3AC
39AC
38AC
37AC
36AC
35AC
34
AC33AC32AC31AC30AC25AC22AC20AC18AC16AC14AC13AC9AC5AC2AC1
AB39AB38AB35AB31AB30AB27AB21AB19AB17AB15AB13AB11AB7AB4AB3
AA37AA33AA31AA29AA24AA22AA18AA16AA14AA13AA9AA5AA2AA1A34A29A24A19A14A9A5A2 G
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
ND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
ZYNQ ULTRASCALE POWER
21 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
XCZU11EG-1FFVF1517I
U21
GND_ADC
V19
Y38
Y35
Y31
Y27
Y25
Y23
Y21
Y17
Y15
Y13
Y11
Y7 Y4 Y3 W37
W36
W33
W31
W26
W24
W22
W18
W16
W14
W13
W9
W5
W2
W1
V39
V38
V35
V31
V30
V25
V23
V21
Y39
V17
V15
V13
V11
V7 V4 V3 U37
U36
U32
U31
U27
U26
U24
U22U20U18U16U14U13U9U5U2U1T39T38T37T36T35T34T33T32T31T29T25T23T21T19T17T15T13T11T7T4T3R36R31R26R24R22R20R18R16R14R13R9R5R2R1P23P21P19P17P15P13P11
P7P4P3N35
N30
N26
N25
N24
N20
N15
N13N9N5N2N1M
37M
32M
27M
22M
17M
13M
12M
11M7
M4
M3
L39
L29
L24
L19
L14
L11
L10L9L5L2L1K36
K31
K26
K21
K16
K11K9K7K4K3J33J9J5J2J1
H35H30H25H20H15H9H7H4H3
G37G27G22G17G12G9G5G2G1
F39F34F9F7F4F3
E31E26E21E16E9E5E2E1
D38D28D23D18D13D9D7D4D3
C35C15C10C9C5C2C1
B39B37B32B27 G
NDAD
CG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
NDG
ND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
(AUXDAC_8)
JESD CAPS CLOSE TO FPGA
(AUXDAC_4)
TALISE A
(AUXDAC_6)
(AUXDAC_7)
(AUXDAC_1/FLASH CS)
(AUXDAC_0/FLASH SO)
(AUXDAC_5)
USE LOW-PROFILE PADS FOR CAPACITORS
(AUXDAC_2) (A
UXDAC_3/FLASH SI)
USE LOW-PROFILE PADS FOR CAPACITORS
(AUXDAC_9/FLASH CLK)
22 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
100
100100
R0201L
R0201L90
1K
59
14.3K
0
0
0
0
0
0
0
0
10K
81
10K
8288
10K
89
10K
DNI26
10K
27
10K
4.7K
1UF
21
58
1UF
100PF
25
1UF
68
0.1UF
0.1UF
37
9
8
11
15
20
0.1UF0.1UF
ADRV9009
0.1UF
0.1UF
0.1UF
0.1UF0.1UF
0.1UF
0.1UF
0.1UF
0.1UF0.1UF
0.1UF
0.1UF
R551
R552R553
R146
R139
R520
R519
R518
R517
R516
R514
R515
R513
R143R142R141R140
R145R144
R527
C416
C400
C413
C399
U14
C418C415
C417C414
C402C407
C412C401
C411C406
C410C405
C409C404
C408C403
SPI_CLK
SPI_MISOSPI_MOSI
GPIO_13_A
VDDA3P3
VDD_INTERFACE_A
VDD_INTERFACE_A
JESD_SYSREF_IN_A_NGPIO_5_AGPIO_4_A
GPIO_14_A
GPIO_3_A
SPI_CSN_ADRV9009_A
RF_EXT_LO_A_PRF_EXT_LO_A_N
SYNCINB1_A_P_ADRV
SYNCOUTB1_A_P_ADRV
SYNCOUTB0_A_P_ADRV
SYNCINB1_A_NSYNCINB1_A_N_ADRV
SYNCINB1_A_PSYNCINB1_A_P_ADRV
SYNCINB0_A_PSYNCINB0_A_P_ADRV
SYNCINB0_A_NSYNCINB0_A_N_ADRV
SYNCOUTB1_A_P
SYNCOUTB0_A_P
SYNCOUTB1_A_NSYNCOUTB1_A_N_ADRV
SYNCOUTB0_A_NSYNCOUTB0_A_N_ADRV
SYNCINB1_A_N_ADRV
VDD1P3_DIG_A
GPIO_15_AGPIO_8_A
SYNCOUTB1_A_N_ADRVSYNCOUTB1_A_P_ADRV
SYNCOUTB0_A_N_ADRV
VDD_INTERFACE_A
GPIO_16_A
GPIO_17_A
RX1_ENABLE_A
JESD_SERDOUT2_A_P
GPIO_6_A
GPIO_9_A
GPIO_7_A
SYNCINB0_A_P_ADRV
SYNCINB0_A_N_ADRV
TX1_ENABLE_A
SYNCOUTB0_A_P_ADRV
VDDA1P3_CLOCK_VCO_LDO_A
VDDA1P8_BB_AGPIO_3P3_6_A
GPIO_3P3_11_A
VDDA1P3_CLOCK_SYNTH_A
JESD_SERDOUT0_A_N
GPIO_3P3_9_A
VDDA1P3_RF_LO_A
RF_SYNTH_VTUNE_A
VDDA1P3_AUX_SYNTH_A
VDDA1P3_BB_A
REF_CLK_IN_A_P
GPIO_3P3_3_AGPIO_3P3_0_A
VDDA1P3_AUX_VCO_LDO_A
AUX_SYNTH_OUT_A
RX2_ENABLE_A
JESD_SERDIN3_A_N
VDDA1P3_RF_SYNTH_A
AUX_SYNTH_VTUNE_A
AUXADC_3_A
VDDA1P8_TX_A
GPIO_3P3_7_A
AUXADC_0_A
JESD_SERDIN0_A_PJESD_SERDIN0_A_NJESD_SERDIN1_A_P
JESD_SERDOUT1_A_PJESD_SERDOUT1_A_N
VDDA1P3_DES_A
JESD_SERDIN3_A_PJESD_SERDIN2_A_NJESD_SERDIN2_A_P
TX2_ENABLE_A
VDDA1P3_RF_VCO_LDO_A
AUXADC_1_A
GPIO_18_A
GPINT_A
GPIO_1_AGPIO_2_A
GPIO_10_A
GPIO_3P3_5_AGPIO_3P3_2_AGPIO_3P3_10_AGPIO_3P3_8_A
GPIO_3P3_4_AGPIO_3P3_1_A
AUXADC_2_A
VDDA1P3_RX_TX_A
VDDA1P3_RX_RF_A
REF_CLK_IN_A_N
TX1_OUT_A_N
JESD_SYSREF_IN_A_P
JESD_SERDOUT3_A_NJESD_SERDOUT3_A_PJESD_SERDOUT2_A_N
JESD_SERDIN1_A_N
JESD_SERDOUT0_A_PVDDA1P3_SER_A
TEST_A
RESETB_A
GPIO_12_AGPIO_11_A
GPIO_0_A
TX2_OUT_A_N
TX1_OUT_A_PTX2_OUT_A_P
ORX2_IN_A_PORX2_IN_A_N
ORX1_IN_A_PORX1_IN_A_N
RX2_IN_A_PRX2_IN_A_N
RX1_IN_A_PRX1_IN_A_N
K9
K3K2
J13J14K1
J10
J8
K11
B5
B3
L2
C12
C8
C10
C14
C6
B14
D1L1
0
L7P1
0
P3 P2 N14
N7 N2 M9
M2
L1K14K13
J2
H13
H10H9H8H7H6H5H4H3H2
G14
G13
G12
G11
G10G
6
G4
G3
G2
G1
F14
F13
F12
F10F9F8F7F6F5F2F1E9E6D12
D11D9D8
D7D6D5D4D3
C11
C9
C4
B13B12B11B10
B9
B6
B4
B2
A14
A11
A8A7
A4
A1
L9 L8
E12E4
P8 N8
C3
B1
C5
G7
P9 N9 N1
G5E5 G8
C7
M1
D10
M12
H1
J1
M8
H14
M6
J6
K4
L13
L14
M13
M14
L3L4
M3
M4
N3N4N5N6P4P5P6P7P11
P12
P13
P14
N10
N11
N12
N13
J9
A6A5
M7
A10A9
M5
G9
B7B8
J4
E8E7
A3A2
A13A12
J3
M10
M11
L11
J11
H11H12
J12
K12
L12
L6L5
K5K6
E14
D14
C13
D13
E13E3E2
D2
C2
E1
C1
K7
J7
K8
J5
K10
E11
F11F4F3
P1
E10
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSA
VSSAVSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSAVSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSAVSSAVSSA
VSSAVSSAVSSAVSSAVSSA
VSSA
VSSA
VSSAVSSA
RX1_IN-RX1_IN+
RX2_IN-RX2_IN+
VDDA1P3_RF_VCO_LDOVDDA1P3_RF_VCO_LDO
ORX1_IN-ORX1_IN+
ORX2_IN-ORX2_IN+
SERD
IN2+
SERD
IN2-
SERD
IN3+
SERD
IN3-
VDDA
1P3_
DES
VDDA
1P3_
SER
SERD
IN0+
SERD
IN0-
SERD
IN1+
SERD
IN1-
VDDA
1P3_
DES
VDDA
1P3_
SER
SYNC
OUT
B0+
SYNC
OUT
B0-
TX2_
ENAB
LE
TX1_
ENAB
LE
SYNC
OUT
B1+
SYNC
OUT
B1-
TX1_OUT-
TX2_OUT+TX1_OUT+
TX2_OUT-
VDDA
1P8_
TX
VDDA1P3_RX_TX
VSSA
GPIO_18
AUX_
SYNT
H_O
UT
VDDA
1P1_
AUX_
VCO
VDDA1P3_AUX_VCO_LDO
AUX_
SYNT
H_VT
UNE
VDDA
1P3_
CLO
CK_V
CO_L
DO
VDDD
1P3_
DIG
VDDD
1P3_
DIG
GP_INTERRUPT
VDDA
1P3_
AUX_
SYNT
H
RF_EXT_LO_I/O+RF_EXT_LO_I/O-
SERD
OUT
0+SE
RDO
UT0-
SERD
OUT
1+SE
RDO
UT1-
SERD
OUT
2+SE
RDO
UT2-
SERD
OUT
3+SE
RDO
UT3-
VDD_
INTE
RFAC
EG
PIO
_16
GPI
O_1
7
RX2_
ENAB
LE
RX1_
ENAB
LESY
NCIN
B0+
SYNC
INB0
-
VDDA
1P1_
CLO
CK_V
CO
GPI
O_8
GPI
O_1
5VS
SD
VSSDGPIO_7GPIO_6
SYNCINB1+SYNCINB1-
GPIO_9GPIO_14
CSBSCLK
GPIO_0GPIO_3GPIO_4GPIO_5
SYSREF_IN-SYSREF_IN+
GPIO_10GPIO_13
SDOSDIO
GPIO_1GPIO_2
TEST
RESETB
GPIO_11GPIO_12
RF_S
YNTH
_VTU
NE
VDDA
1P3_
RF_S
YNTH
VDDA
1P3_
CLO
CK_S
YNTH
AUXA
DC_2
AUXA
DC_1
AUXA
DC_0
GPI
O_3
p3_1
1G
PIO
_3p3
_7
AUXA
DC_3
REF_
CLK_
IN-
REF_
CLK_
IN+
VDDA
1P3_
BBVD
DA1P
8_BB
GPI
O_3
p3_6
GPI
O_3
p3_5
GPI
O_3
p3_2
GPI
O_3
p3_1
0G
PIO
_3p3
_8
GPIO_3p3_4GPIO_3p3_1RBIASGPIO_3p3_9VDDA_3P3
VDDA1P3_RF_LOVDDA1P1_RF_VCO
GPIO_3p3_3GPIO_3p3_0
VDDA1P3_RX_RF
VSSA
GNDGND
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
TALISE B
JESD CAPS CLOSE TO FPGA
USE LOW-PROFILE PADS FOR CAPACITORS
USE LOW-PROFILE PADS FOR CAPACITORS
(AUXDAC_3/FLASH SI)
(AUXDAC_8)
(AUXDAC_9/FLASH CLK)
(AUXDAC_4)
(AUXDAC_5)
(AUXDAC_1/FLASH CS)
(AUXDAC_6)
(AUXDAC_2)
(AUXDAC_0/FLASH SO)
(AUXDAC_7)
23 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
100
10K
4.7K
100100ADRV9009
10K
25 DNI
R0201L
R0201L
1K
23
14.3K
27
0
0
0
0
0
0
0
0
24
10K
21
10K
20
10K
7
10K
6
22
100PF
1UF
26
1UF
29
1UF
28
0.1UF
0.1UF0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF0.1UF
4
3
2
15
14
10
8
1
13
12
11
9
19
18
17
16
5
R548
R549R550 R88 R89
R90
R83
R505
R498
R499
R500
R501
R502
R503
R504
R84 R85 R86 R87
R526
U38
C318
C321
C304
C305
C306
C307C312
C311
C310
C309
C308
C317
C315
C316
C313
C314
C323C320
C319C322
SPI_CLK
GPIO_14_BGPIO_9_B
SYNCINB1_B_N_ADRV
SYNCINB1_B_P_ADRV
SYNCINB0_B_P_ADRV
GPIO_3_B
GPIO_5_BGPIO_4_B
SPI_MISO
RESETB_B
GPIO_1_BSPI_MOSI
GPIO_13_BGPIO_10_B
TX1_OUT_B_N
JESD_SYSREF_IN_B_PJESD_SYSREF_IN_B_N
GPINT_B
VDD_INTERFACE_B
VDD_INTERFACE_B
SPI_CSN_ADRV9009_B
RF_EXT_LO_B_PRF_EXT_LO_B_N
SYNCINB1_B_N_ADRV
SYNCINB0_B_P_ADRV
GPIO_6_BSYNCINB1_B_P_ADRV
SYNCOUTB1_B_N_ADRV
GPIO_7_B
SYNCOUTB1_B_P_ADRV
GPIO_8_B
SYNCINB0_B_N_ADRV
VDD_INTERFACE_B
SYNCOUTB0_B_N_ADRV
SYNCOUTB0_B_P_ADRV
VDDA1P3_CLOCK_VCO_LDO_B
GPIO_17_B
RX1_ENABLE_BTX1_ENABLE_B
GPIO_16_B
SYNCOUTB0_B_P_ADRV
SYNCOUTB0_B_N_ADRV
ORX2_IN_B_N
RF_SYNTH_VTUNE_B
VDDA1P3_CLOCK_SYNTH_B
VDDA1P3_RF_SYNTH_B
AUXADC_3_B
VDDA1P8_TX_B
GPIO_3P3_7_B
GPIO_3P3_11_B
VDDA1P3_AUX_VCO_LDO_B
GPIO_3P3_5_BGPIO_3P3_6_B
VDDA1P3_BB_BVDDA1P8_BB_B
VDD1P3_DIG_B
AUXADC_2_B
ORX1_IN_B_NORX1_IN_B_P
VDDA1P3_RX_TX_B
GPIO_0_B
GPIO_2_B
AUXADC_1_B
AUXADC_0_B
GPIO_3P3_4_B
VDDA3P3
GPIO_3P3_3_BGPIO_3P3_0_B
VDDA1P3_RF_VCO_LDO_B
AUX_SYNTH_VTUNE_B
VDDA1P3_DES_B
VDDA1P3_SER_B
TX2_ENABLE_B
GPIO_15_B
RX2_IN_B_P
RX1_IN_B_NRX1_IN_B_P
VDDA1P3_RF_LO_B
TEST_B
GPIO_12_BGPIO_11_B
TX2_OUT_B_PTX1_OUT_B_P
TX2_OUT_B_N
RX2_ENABLE_B
JESD_SERDIN2_B_N
JESD_SERDOUT0_B_N
JESD_SERDIN3_B_N
JESD_SERDIN2_B_P
JESD_SERDOUT0_B_P
JESD_SERDIN1_B_P
JESD_SERDIN0_B_PJESD_SERDIN0_B_N
JESD_SERDIN1_B_N
JESD_SERDIN3_B_P
JESD_SERDOUT2_B_N
JESD_SERDOUT3_B_NJESD_SERDOUT3_B_P
JESD_SERDOUT2_B_P
GPIO_18_B
VDDA1P3_RX_RF_B
ORX2_IN_B_P
RX2_IN_B_N
GPIO_3P3_1_B
GPIO_3P3_9_B
JESD_SERDOUT1_B_NJESD_SERDOUT1_B_P
VDDA1P3_AUX_SYNTH_B
REF_CLK_IN_B_PREF_CLK_IN_B_N
GPIO_3P3_2_BGPIO_3P3_10_BGPIO_3P3_8_B
AUX_SYNTH_OUT_B
SYNCOUTB0_B_N
SYNCOUTB0_B_P
SYNCOUTB1_B_N
SYNCOUTB1_B_P
SYNCINB0_B_N
SYNCINB0_B_P
SYNCINB1_B_P
SYNCINB1_B_N
SYNCOUTB1_B_N_ADRV
SYNCOUTB1_B_P_ADRV
SYNCINB0_B_N_ADRV
K10K11
J9J10
M1
M2
B6B5
E10
P1
F3 F4 F11
E11
J5
K8
J8J7
K7
C1
D1
E1
C2
D2
E2 E3 E13
D13
C13
D14
E14
K6K5
L5L6
L12
K12
J12
H12H11
J11
L11
M11
M10
J3
A12A13
A2A3
C14
E7 E8
J4
B8B7
G9
M5
A9A10
M7
A5A6
K9N1
3N1
2N1
1N1
0
P14
P13
P12
P11
P7 P6 P5 P4 N6 N5 N4 N3 M4
M3
L4L3
M14
M13
L14
L13
K3K4
J6
M6
H14
J14
M8
J1
H1
M12
D10
C7
G8
C10
E5 G5
N1N9P9
C8
G7
C5C6
B1
C3
N8P8
E4 E12
C12
L8L9
A1
A4
A7A8
A11
A14
B2B3B4
B9B10B11B12B13B14
C4
C9
C11
D3D4D5D6D7
D8 D9 D11
D12 E6 E9 F1 F2 F5 F6 F7 F8 F9 F10
F12
F13
F14
G1
G2
G3
G4
G6
G10
G11
G12
G13
G14
H2H3H4H5H6H7H8H9H10
H13
J2
J13
K1K2
K13K14L1L2
M9
N2N7N14
P2P3P10
L7
L10
GND
GND
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSA
VSSAVSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSAVSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSAVSSA
VSSA
VSSA
VSSA
VSSAVSSAVSSAVSSAVSSAVSSA
VSSAVSSAVSSAVSSAVSSA
VSSA
VSSA
VSSAVSSA
RX1_IN-RX1_IN+
RX2_IN-RX2_IN+
VDDA1P3_RF_VCO_LDOVDDA1P3_RF_VCO_LDO
ORX1_IN-ORX1_IN+
ORX2_IN-ORX2_IN+
SERD
IN2+
SERD
IN2-
SERD
IN3+
SERD
IN3-
VDDA
1P3_
DES
VDDA
1P3_
SER
SERD
IN0+
SERD
IN0-
SERD
IN1+
SERD
IN1-
VDDA
1P3_
DES
VDDA
1P3_
SER
SYNC
OUT
B0+
SYNC
OUT
B0-
TX2_
ENAB
LE
TX1_
ENAB
LE
SYNC
OUT
B1+
SYNC
OUT
B1-
TX1_OUT-
TX2_OUT+TX1_OUT+
TX2_OUT-
VDDA
1P8_
TX
VDDA1P3_RX_TX
VSSA
GPIO_18
AUX_
SYNT
H_O
UT
VDDA
1P1_
AUX_
VCO
VDDA1P3_AUX_VCO_LDO
AUX_
SYNT
H_VT
UNE
VDDA
1P3_
CLO
CK_V
CO_L
DO
VDDD
1P3_
DIG
VDDD
1P3_
DIG
GP_INTERRUPT
VDDA
1P3_
AUX_
SYNT
H
RF_EXT_LO_I/O+RF_EXT_LO_I/O-
SERD
OUT
0+SE
RDO
UT0-
SERD
OUT
1+SE
RDO
UT1-
SERD
OUT
2+SE
RDO
UT2-
SERD
OUT
3+SE
RDO
UT3-
VDD_
INTE
RFAC
EG
PIO
_16
GPI
O_1
7
RX2_
ENAB
LE
RX1_
ENAB
LESY
NCIN
B0+
SYNC
INB0
-
VDDA
1P1_
CLO
CK_V
CO
GPI
O_8
GPI
O_1
5VS
SD
VSSDGPIO_7GPIO_6
SYNCINB1+SYNCINB1-
GPIO_9GPIO_14
CSBSCLK
GPIO_0GPIO_3GPIO_4GPIO_5
SYSREF_IN-SYSREF_IN+
GPIO_10GPIO_13
SDOSDIO
GPIO_1GPIO_2
TEST
RESETB
GPIO_11GPIO_12
RF_S
YNTH
_VTU
NE
VDDA
1P3_
RF_S
YNTH
VDDA
1P3_
CLO
CK_S
YNTH
AUXA
DC_2
AUXA
DC_1
AUXA
DC_0
GPI
O_3
p3_1
1G
PIO
_3p3
_7
AUXA
DC_3
REF_
CLK_
IN-
REF_
CLK_
IN+
VDDA
1P3_
BBVD
DA1P
8_BB
GPI
O_3
p3_6
GPI
O_3
p3_5
GPI
O_3
p3_2
GPI
O_3
p3_1
0G
PIO
_3p3
_8
GPIO_3p3_4GPIO_3p3_1RBIASGPIO_3p3_9VDDA_3P3
VDDA1P3_RF_LOVDDA1P1_RF_VCO
GPIO_3p3_3GPIO_3p3_0
VDDA1P3_RX_RF
VSSA
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
PLACED
1.3VDC
DECOUPLING TALISE A
SHARE PADSPLACED
PLACED
PLACED
PLACED
POSSIBLE INDUCTOR
PLACED
PLACED
PLACED
PLACED
0201 FOOTPRINT
PLACED
PLACED
PLACED
PLACED
PLACED
PLACED
PLACED
PLACED
PLACED
OVERLAP PADS
24 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
111
0
0
84
10UF470UF
0.01UF
1.8K OHM AT 100MEGHZ
102
100UF
0
114
0
118
0
108
107
0
121
0
0
113
0
79
0
95
0
33
0
52
0
120
0.1
115
1UF
42OHM AT 100MEGHZ
0.1UF
0.1UF 1UF 10UF
103
10UF
1UF 0.1UF
10UF0.01UF
106
DNI
0.01UF
43
1UF 10UF
32
0.01UF
31
0.1UF
0.01UF
0.01UF 0.1UF 0.1UF 1UF
100UF
10UF
80
0.01UF
91 87
1UF
53
77
0.01UF
116
470UF 100UF
69
10UF
75
71
10UF
0.01UF
0.01UF 0.1UF
112
101
0.1UF
0.1UF
1UF
10UF
34
93 9485
73
606162 38 35
86
100117
7283
98122
109110
747870
67
6463
44 42 4041
464547
28 29 30
4849
104105 55
9297
76
1UF
1UF
65
0.01UF
0.1UF96
119
1UF
51
0.01UF0.1UF
0.01UF
5756
100UF
54
30OHM
1UF
1UF0.1UF0.01UF
36
100UF 100UF 100UF 100UF
39
1UF
1UF0.1UF 10UF
1.8KOHM AT 100MEGHZ
470UF 100UF 100UF
50
0.1UF0.01UF
0.01UF 10UF0.1UF 1UF
99
DNI
10UF1UF0.1UF
66
R372
R362
TP93
TP91
C898 C899
E29
C903
TP89
C954
TP10
1
R365
R364
R374
R373R363
R370
R369
R368
R367
R361
R366
R371
TP12
3
C1099
TP98
TP90
C904
TP92
TP95
TP96
TP97
TP94
TP99
C913
C911
C957
C1098
C953
C963
E30
C906
C932
C915
E1
C907 C916 C925
C908
C924 C938
C930
C929
C923
C935
C902 C919 C928
C934C918 C939C927
C914C905
L16
E28
C948 C949
C901
C946
C909
C926C917
C931
C962
C966
C951
C960
C961
C952
TP87
TP88
TP102TP103
C933
C921C964 C968TP100
C967C959C955C950
C943 C945 C947C941
C912 C922
C958 C965
C956
C940 C942 C944
C937
C920C910 C936
C900
VDDA1P3_ANLG_SNS_A
VDDA1P3_CLOCK_VCO_LDO_A
VDDA1P3_AUX_SYNTH_A
VDDA1P3_ANLG_A
VDDA3P3
VDD_INTERFACE_A
VDDA1P3_RF_LO_A
VDDA1P3_DES_A
VDDA1P3_SER_A
VDDA1P3_RF_VCO_LDO_A
VDDA1P3_CLOCK_SYNTH_A
VDDA1P3_BB_A
VDDA1P8_BB_A
1V8
VDDA1P8_TX_A
VDDA1P3_AUX_VCO_LDO_A
VDDA1P3_RF_SYNTH_A
VDDA1P3_RX_RF_A
VDDA1P3_RX_TX_A
VDD1P3_DIG_A
VDD1P3_DIG_A
VDDA1P8_A
21
1
21
2
GND
GND
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
OVERLAP PADS
0201 FOOTPRINT
POSSIBLE INDUCTOR
1.3VDC
SHARE PADS
DECOUPLING TALISE B
25 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
470UF
0
10UF
0
0
0.1
0
0
0
0
0
0
0
0
0
0
1UF0.1UF0.01UF
10UF1UF0.01UF
10UF
DNI
0.1UF
1.8K OHM AT 100MEGHZ
100UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
1UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
100UF 100UF
100UF
100UF100UF100UF100UF
100UF100UF
470UF1.8KOHM AT 100MEGHZ
30OHM
DNI
42OHM AT 100MEGHZ
470UF
C970
R386
R385TP11
5
C969
TP11
8
R388
R387
R381
R375
R380
R379
R378
R377
R376
R384
R383
R382
TP105
TP11
0
C1015 C1017C1011
C994C975
TP10
9
L17
C984C972
TP12
0
TP11
7
TP11
3TP
116
TP11
4TP
112
TP11
1TP
108
TP10
7
TP122TP121
TP119
TP106
C988
C1028
C1101C1100
E32
E34
E33E31
C1031 C1035
C1036
C1027
C1030C1026
C1022 C1038C1034
C1039C1037
C1032
C1033C1029C1025
C1024C1023
C1021
C1020C1019C1018C1016C1014C1012
C993
C1006
C983C974
C1013
C1010
C985C976
C1007C1000C991
C1008C1001C992
C981
C982
C1009
C1005C998
C999
C1004C997
C989
C990C980
C979
C1002C995
C1003C996
C986C977
C987C978
C971
C973
VDDA1P3_ANLG_B
VDDA1P3_RX_RF_B
VDDA1P3_CLOCK_VCO_LDO_B
1V8VDD_INTERFACE_B
VDDA1P3_AUX_SYNTH_B
VDDA1P3_RF_SYNTH_B
VDD1P3_DIG_B
VDD1P3_DIG_B
VDDA1P8_BB_B
VDDA3P3
VDDA1P8_TX_BVDDA1P8_BVDDA1P3_RX_TX_B
VDDA1P3_DES_B
VDDA1P3_SER_B
VDDA1P3_RF_VCO_LDO_B
VDDA1P3_RF_LO_B
VDDA1P3_AUX_VCO_LDO_B
VDDA1P3_CLOCK_SYNTH_B
VDDA1P3_BB_B
VDDA1P3_ANLG_SNS_B
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GNDGNDGND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
ORX2 ARX2 A
RX1 A ORX1 A
RX, ORX, LO TALISE A
LO IN/OUT
26 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
0
00
0
00
00
0
2
0
9
0
3
0
0
DNIDNI HHM1595A1
100PF
100PF
TCM1-83X+
DNI
DNI
6
1
7
4
5
1112
810
10PFDNI
27PF27PF
18PF 18PF
10PF 27PF
18PF
27PF
18PF
DNIDNI
10PFDNI
DNIDNI
10PFDNI
DNIDNI
DNIDNIDNI
DNI
TCM1-83X+
TCM1-83X+ TCM1-83X+
4.7UFDNI
DNIDNI
DNI
R102
R101R98
R96
R95R92
R99R97
R100
R93R91
R94
R506J13
C364
C365
T13
C363C202
C344
T1
T4T3 C343C329
C345C333
C331
C341C339C337C327C325
J2
J9J1
C350
C342T2
C346
C340C338C336
C328
C332C330
C326C324
C351C349
C348C334
C335
C347
J10RX2_UNBAL_A
RX1_UNBAL_A
RF_EXT_LO_A_N
RF_EXT_LO_A_P
RX1_BAL_A_P
RX2_BAL_A_PRX2_IN_A_P
ORX2_UNBAL_A
RX2_IN_A_N
RX1_IN_A_P
RX1_IN_A_NRX1_BAL_A_N
RX2_BAL_A_N
ORX1_UNBAL_AORX1_IN_A_P
ORX1_BAL_A_NORX1_IN_A_N
ORX1_BAL_A_P
ORX2_IN_A_NORX2_BAL_A_N
ORX2_IN_A_PORX2_BAL_A_P5
4
3
2
6 1
32
1
32
1 5
4
3
2
6 1
5
4
3
2
6 1
GND
GNDGND
GND
GND
GND
GNDGNDGND
GND
GND
GNDGND
NCNC
GNDGND
GNDGND
GNDGNDNCBALBAL
UNBAL
NC NCGND
GND GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
RX, ORX, LO TALISE B
LO IN/OUT
RX1 B ORX1 B
ORX2 BRX2 B
27 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
DNI
DNI
0
TCM1-83X+
TCM1-83X+
TCM1-83X+
DNI
DNIDNI
DNI DNI
DNI DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
10PFDNI
DNI10PF
18PF
18PF
18PF
18PF
27PF
27PF
27PF
27PF
DNI
DNI10PF
TCM1-83X+
100PF
DNIDNI
100PFHHM1595A1
0
0
0 0
0
0
0
0
0
0
0
010PF
C107
2
J8 J12
J11J7
C1091
C1090
T9
T10
T11
C1066
C1067
C1068 C1076
C1077
C1078
C1079
C1080
C1081
C1082
C1083
C1092
C107
3
C107
4C1
075
C1086
C1087
C108
8C1
089
C1070
C1071
C1084
C1085
C1093
T12
J15
C1114 C1115
T15
C1117
C1116
R521
R395 R397
R399
R398
R400
R401
R402
R403
R405
R404
R406
C1069
R396 RX2_IN_B_P
RX1_BAL_B_NRX1_IN_B_N
RX1_IN_B_PRX1_BAL_B_P
RX2_BAL_B_P
RX2_IN_B_N
ORX1_UNBAL_B
ORX2_UNBAL_B
ORX1_IN_B_P
ORX1_IN_B_NORX1_BAL_B_N
ORX1_BAL_B_P
ORX2_IN_B_P
ORX2_IN_B_NORX2_BAL_B_N
ORX2_BAL_B_P
RF_EXT_LO_B_P
RF_EXT_LO_B_N
RX2_UNBAL_B
RX1_UNBAL_B
RX2_BAL_B_N
1
2 3
1
2 3
GND
NC
NC
NC
NC
GND
GND
GND
GND
GND
GND
GND
GND
GNDGND
GNDGND
GND
GNDGNDNCBALBAL
UNBAL
GNDGND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
TX1 A
TX2 A
TX CHANNELS TALISE A
28 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
0
0
0
0
0
0
43NHDNI
DNI
0.1UF
DNI
51PF
27PF
10PF
43NH
75PF
51PF
10PF
0.1UF
0.1UF
0.1UF
75PF
DNI
DNI
18PF
27PF
DNIDNI
DNIDNI
DNI
DNIDNI
DNI18PF
TCM1-83X+
DNI
TCM1-83X+
43NH
43NH
DNI
DNI
R203
R201
R200
R202
R198
R199
C577
C572
L5
C585
C584
C583
C582
L6
C588
C579
C586
L8
L7
L4
L3
C589
C587
C581C571
C591
C578
C595C593
C575
C574
T5
T6 J4
J3
C594C592
C590C580
C576
L1
C570
L2
C573
TX2_BAL_A_P
TX2_BAL_A_N
TX1_BAL_A_N
TX1_BAL_A_P
TX2_OUT_A_P
TX2_OUT_A_N
TX1_OUT_A_P
TX1_OUT_A_N
RFO1_A
VDDA1P8_TX_A
RFO2_A
VDDA1P8_TX_A
VDDA1P8_TX_A
VDDA1P8_TX_A
3 2
1
3 2
1
NC
NC
GND
GND
GND
GND
GND
GND GNDGND
GNDGNDGND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
TX2 B
TX CHANNELS TALISE B
TX1 B
29 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
0
1
0
0
0
0
0
DNI
18PF
10PF6
8
7
5
2
93
410
0.1UF
0.1UF
0.1UF
0.1UF
DNI
DNI
DNI
DNI
18PF
10PF
27PF
27PF
51PF
51PF
75PF
75PF
DNI
DNI
DNI
DNI
DNI
DNI
DNI
TCM1-83X+
TCM1-83X+
43NH
43NH
43NH
43NH
DNI
DNI
DNI
DNI
R394
R393
R392
R390
R391
R389
C1051
C1049
C1056
C1062
C1065
C1052
C1053
C1055
L25
L23
L24
L22
L21
L19
L20
L18
C1059
C1058
C1054
C1057
C1050
C1041
C1040
C1061
C1060
C1047
C1048
C1046
C1064
C1063
C1045
C1043
C1044
C1042
T8
T7
J6
J5
TX2_BAL_B_P
TX1_BAL_B_P
TX2_BAL_B_N
TX1_BAL_B_N
TX2_OUT_B_P
TX2_OUT_B_N
TX1_OUT_B_N
TX1_OUT_B_P
RFO1_B
VDDA1P8_TX_B
VDDA1P8_TX_B
RFO2_B
VDDA1P8_TX_B
VDDA1P8_TX_B
3 2
1
3 2
1
GND
NC
NCGND
GNDGND
GND
GNDGNDGND
GND
GND
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
PLACE TERMINATION CLOSE TO TALISE
LVDS
MATCH LENGTH ON ALL CLOCKS FROM HMC7044 TO AC CAP OR 0 OHM RESISTORS
PLACE 0 OHM RESISTORS CLOSE TO FPGA
LVDS
REF CLK
PLACE O OHM RESISTORS CLOSE TO HMC7044
HMC7044 JESD CLOCK GENERATOR
LVDS
LVDS
LVDS
PLACE TERMINATIONS CLOSE TO TALISE
LVDS HIGHPOWER OR CML 50OHM ZOUT
LVDS
LVDS HIGHPOWER OR CML 50OHM ZOUT
USE LOW-PROFILE PADS FOR CAPACITORS
PLACE NEAR OSCILLATOR
LAYOUT NOTES:
LVDS OR CML
USE LOW-PROFILE PADS FOR CAPACITORSPLACE TERMINATIONS CLOSE TO TALISE
PLACE DECOUPLING CPAS CLOSE TO FPGA/TALISE
PLACE TERMINATION CLOSE TO TALISE
PLACE CAPACITORS CLOSE TO FPGA
LVDS OR CML
PLACE CAPACITORS CLOSE TO FPGA
30 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
0
0
0.1UF0.1UF4700PF160PF
DNI
0
0
00
00
0
100
R0201L
DNI
100PF
100
0
0
100
DNI
0
0
MABA-007159-000000
4.7UF 4.7UF
0.1UF
49.9
R0402L
24.9
R0402L
R0201L
100
0.1UF
DNI
0
DNI
24.9
R0201L
DNI100
0.1UF
0.01UF
0.01UF
100PF
DNI
1UF
1UF
4.7UF4.7UF4.7UF
4700PF
120OHM
122.88MEGHZ
120OHM2200PF
24
HMC7044LP10BE
DNI
CVHD-950X-122.880
10UF 0.1UF
2.2UF
82PF
0.1UF0.01UF
0.01UF
10K
10K
DNI
R0402L
4.7K4.7K
0
0
0
0
DNI
430
DNI
0
11K
0
0
0
0
0
0
DNI
49.9
R0402L
DNI100
100
100
100
100100
100
100
DNI
R0201L
R0201L
R0201L
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
R474
C387
U11
C374
R470
R473
R472
R467
R468
R469
R471
C381
R528
R529
R477
R122
R478
C378
TP3
C376
C358
R113
R507
R509
R511
R118
C379C377C375
TP2
T14
R512
C384
C382
C369
C370C368C356C353C352
C373
J14
E11
Y6
C354 C357
E10
C380
C371C359
C372
TP1
C355
C383
R114
R115
R510
R112R423
R464
R462
R463
R461
R111
R110
R119
R116
R117
R460
R459
R475
R476
R508
R121
R120
R109
R108R105
R104
R103R107
R106
R123
C366
C385
C388
C386
C367
C821
JESD_SYSREF_FPGA_B_N
CORE_CLK_B_NCORE_CLK_B_P
CORE_CLK_A_N
JESD_REFCLK_FPGA_B_N
JESD_SYSREF_FPGA_B_P
JESD_SYSREF_FPGA_A_P
JESD_SYSREF_IN_B_P
REF_CLK_IN_B_N
JESD_REFCLK_FPGA_B_P
JESD_REFCLK_FPGA_A_P
JESD_SYSREF_IN_B_N
OSCOUT1_N
OSCOUT1_P
JESD_REFCLK_FPGA_A_N
VCC6_OSCOUT
VCC7_PLL2
VCC8_OUT
VCC9_OUT
JESD_SYSREF_FPGA_A_N
CORE_CLK_A_P
OSCIN_EXT
CLKIN3_HMC7044_N
CLKIN2_HMC7044_N
CLKIN2_HMC7044_P
OSCIN_EXT
RESET_HMC7044
CLKIN2_HMC7044_P
CLKIN2_HMC7044_N
VCXO_GND
1V8
SYNC_HMC7044_FPGA
VCC1_VCO
CLKIN1_HMC7044_N
CLKIN3_HMC7044_PVCC2_OUT
VCC3_SYSREF
VDDA3P3_VCXO
SYNC_HMC7044
CPOUT1
VCC4_OUT
VCC5_PLL1
VCXO_GND
CPOUT1
JESD_SYSREF_IN_A_P
JESD_SYSREF_IN_A_N
REF_CLK_IN_B_P
CLKIN0_HMC7044_N
CLKIN1_HMC7044_P
SPI_CLK
GPIO_3_HMC7044GPIO_4_HMC7044
GPIO_1_HMC7044GPIO_2_HMC7044
SPI_MOSI
SPI_CSN_HMC7044
CLKIN0_HMC7044_P
REF_CLK_IN_A_P
REF_CLK_IN_A_N
32
4544
57 68
15
50
40
4243
4748
33
7
34
12
16
2425
2728
5556
5859
66
315262
89
11124649
PAD
5
35
19
34
13
2223
2930
5354
6061
65
20
18
617 26 38 41 51
6310
39
216764
14
3637
GND
GND
GND
GND
GND
GND
GND
GND
VDDOUTCONTROL
GND
GND
GND
GND
GND
GNDGND
SECPRI
PAD
VCC9
_OUT
CLKOUT12_NCLKOUT12
SCLKOUT13_NSCLKOUT13
GPIO4GPIO3 SCLKOUT11_N
SCLKOUT11CLKOUT10_N
CLKOUT10
VCC8
_OUT
CLKOUT8_NCLKOUT8
SCLKOUT9_NSCLKOUT9
GPIO2
VCC7
_PLL
2
CPOUT2
LDOBYP7
OSCIN_NOSCIN
LDOBYP6
OSCOUT1_N
OSCOUT1
CLKIN2_N/OSCOUT0_NCLKIN2/OSCOUT0
VCC6
_OSC
OUT
CLKIN0_N/RFSYNCIN_NCLKIN0/RFSYNCIN
VCC5
_PLL
1
CLKIN1_N/FIN_NCLKIN1/FIN
RSV
CLKIN3_NCLKIN3
CPOUT1
GPIO1
SCLKOUT7_NSCLKOUT7
CLKOUT6_NCLKOUT6
VCC4
_OUT
CLKOUT4_NCLKOUT4
SCLKOUT5_NSCLKOUT5
VCC3
_SYS
REF
SDATASCLKSLEN
VCC2
_OUT
CLKOUT2_NCLKOUT2
SCLKOUT3_NSCLKOUT3
LDOBYP5LDOBYP4
VCC1
_VCO
LDOBYP3LDOBYP2
BGABYP1
SYNCRESET
SCLKOUT1_NSCLKOUT1
CLKOUT0_NCLKOUT0
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
DECOUPLING HMC7044
31 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
1000PF120OHM
0.1UF 4.7UF4.7UF
1000PF 4.7UF
4.7UF4.7UF
4.7UF
4.7UF
1UF
1UF
0.01UF
1000PF
1000PF
1000PF
1000PF
1000PF1000PF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
120OHM
120OHM120OHM
120OHM
120OHM
120OHM
120OHM
E12
TP49
C561 C564 C568
TP48
TP47
TP46
TP45
TP44
TP43
TP42
E16
C546 C552 C558
E15
C545
C544
C551 C557
C550 C556
E14
C543
E13
C542
C549 C555
C548 C554
E19
E18
C560
C559
C563 C567
C562 C566
C541 C547 C553
E17VDDA3P3_CLK
VCC7_PLL2
VDDA3P3_CLK
VDDA3P3_VCO VCC1_VCO
VCC6_OSCOUT
VCC5_PLL1
VCC8_OUT
VCC4_OUT
VCC3_SYSREF
VCC9_OUT
VCC2_OUT
GND
GND
GND
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
OUTPUT PUSH-PULLOUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UP
OUTPUT PUSH-PULL
OUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UP
OUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UP
PROGRAM INTERBAL TPOR DELAY 65MS
OUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UP
OUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UPOUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UPOUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UP
OUTPUT PUSH-PULLOUTPUT OPEN-DRAIN WITH EXTERNAL PULL-UP
1MS DELAY BETWEEB EN_VIN_SW AND EN_0V85_PL
OUTPUT PUSH-PULL
INPUT, INTERNAL PULL-UP
INPUT POWER MONITORING
INPUT
ADDRESS 0X48
INPUT, INTERNAL PULL-UP
ADDRESS 0X68
ADDRESS 0XB0
1MICROAMP/KELVIN, 2.32 MILLIVOLT/KELVIN
OPEN-DRAIN SIGNALS. PULL-UPS ARE ON THE SOM.
PG_ALL HAS ALREADY A PULL-UP ON PAGE 6
32 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
10UF
10UF
0.1UF
2.2UF
1000PFADP7118ACPZN3.3
DNI
(C0603L)
DNIDNI
R0402L
4.7K4.7K4.7K4.7K
BAT54XV2T1G
100
100
2.2UF
DNI
4.7K
00
4.7K
DNIBAT54XV2T1G
PCA9517DP,118
ADM1266-R
LTST-C191KSKT
100
12.7K
470
100
PCA9517DP,118
0.1UF
LTST-C194KGKT
100
100100100
2.2K0.1UF
0
470 470
R0402L
ADM1177-1ARMZ
100
0.1UF
2.2UF
2.2K
BSZ065N03LS
0.1UF
0.1UF
(C0603L)
0.1UF
0.1UF
0.01
100
100
100UF
0.1UF
0.1UF
0.1UF
100
100
100
100
4.7K
100
R0402L
2.32K
AD590JCPZ
2.2K2.2K
LTST-C191KRKT
R0402L
10UF
DNI
4.7K
DNI
BSS138LT1G BSS138LT1G BSS138LT1G
C393
C391
C1097
C1118 C1123
U48
C569
Q8
R481
TP26
TP25
R547R546
R136R532
C398
C1096
R424 R425
D1
U39
C389
Q6DS4
R132
DS3
TP11
TP13
C396
TP19
TP10
TP8
TP7
R134
TP4 TP5
R135
C397
R138
U12
DS2
R480
TP9
TP12
C394
C392
TP18
TP15
TP14
TP6
R137
U47
C1113
U13
R540TP16R539
R538R537
R534R535
R545
R426
R533
R536
C395
C390
C1122
C565
R427
R131
R542
R543
R541
R544
D2
R130
R455
R479
U46
R133
C1121
Q9 Q10
R124 R125 R127 R129
VIN
12V0
1V8_MGTRAVTT
EN_VIN_SW
1V8
VIN
1V8
I2C0_SCL
I2C0_SDA
1V8
PWR_FAULT1PWR_FAULT2PG_3V3_2V5
12V0
VIN
VDD1P3_DIG_A
0V85_PL0V85_PS
PG_DDR4
PG_3V3_2V5
EN_VIN_SW
EN_1V2_DDR4
EN_3V3_2V5
3V3
EN_MGTAVTT
EN_RF
I2C0_SCL
I2C0_SDA
3V3
12V0
3V3
3V3
EN_MGTAVCC
EN_1V8
EN_0V85_PL
EN_0V85_PS
EN_VIN_SW
PG_ALL
PG_SOM
3V3
1V8
EN_1V8
PG_SOM
PG_DDR4
VIN
VDDA1P8_A
3V3_I2C
VDDA1P3_ANLG_A
VIN
1V2_MGTAVTT
VDDA3P3_CLK
1V8
3V3_I2C
SCL_ADM1166_3V3
PG_ALL
3V3
VTEMPERATURE
0V85_MGTRAVCC
VTEMPERATURE
EN_0V85_PL
EN_MGTAVCCEN_MGTAVTTEN_3V3_2V5
SDA_ADM1166_3V3
EN_RFEN_1V2_DDR4
EN_0V85_PS
PS_DONE PG_SOM PG_ALL
PG_DDR4
PWR_FAULT2PWR_FAULT1PG_ALLPG_SOM
PG_3V3_2V5
VDDA1P8_B
VDDA1P3_ANLG_B
VDD1P3_DIG_B
0V9_MGTAVCC
1
5
92
64 7
8
10
3
GND
VCCB VCCA
GND
SCLB
SDAB
EN
SCLA
SDAA
GND GND
S
GD
GND
GND
GATESS
ADRSDASCLTIMER
GNDONSENSEVCC
GNDGND
GND
GND
PAD
VIN
SS
EN
GND
SENSE/ADJVOUT
GND GND
GND
GND
GND
VCCBVCCA
GND
SCLB
SDAB
EN
SCLA
SDAA
GND
GND
GND
GND
GND
GND
GPIO9GPIO8
GPIO7GPIO6GPIO5GPIO4
FWD/XTAL1REV/XTAL2
EPAD
VP8VP9VP10VP11VP12VP13
PDIO6PDIO7PIDO8PDIO9
PDIO10PDIO11PDIO12PDIO13PDIO14PDIO15PDIO16
SCLSDASYNCID_SCLID_SDA
DVDD
_CAP
GPIO3GPIO2GPIO1
PDIO1PDIO2PDIO3PDIO4PDIO5
VP1VP2VP3VP4
AVDD
_CAP
GND
VH1
VH2
VH3
VH4
ADDR
DAC9DAC8DAC7DAC6DAC5DAC4DAC3DAC2DAC1
REFG
ND
REFOUT
VP5VP6VP7
GNDGNDGND
GND
GND
PAD NCNC V-
V+
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
FORCED CONTINUOUS MODE
400KHZ
60DEG PHASE
0V85 PL
0.85V, 40A
33 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
22UF 22UF
22UF
22UF22UF22UF22UF 22UF
0
0
DNI
10K
10K
15K
DNI
37.4K
0
0
30.1K
22PF
DNI
100PF
4.7UF
100UF
2200PF2.2
LTM4636-1IY#PBF
0.1UF
100UF
12K
100UF 100UF 100UF 100UF 100UF 100UF 100UF
C452
C460
C459C458C457C450 C454C451
R554
R179
R177
R181
R178
R184
R176
R186
R185
R183
R182
C467
C453
C455
C461
C463
C456R180
TP27 TP28
C466
TP29
C462
R187
C464 C465 C468 C469
U15
C470 C471 C472
TP3012V0
12V0
INTVCC_LTM4636
EN_0V85_PL
PVCC_LTM4636
0V85_PL_FB
CLKOUT_400K_1
0V85_PL_FB
PVCC_LTM4636 INTVCC_LTM4636
0V85_PL_SNS_P
0V85_PL_SNS_N
0V85_PL
J11
G12
M3
H4
C12D6
H8
H10
H11
H12
F5H2H9
D7 D8 D9 E6 E7
H3
G11G9
F1F2
G8G7
E11
F3F11D10
E12
E10
E5D5E2E4
L11
G5K11
M7M8
M6
L7L8M4M5
L6
K6K7K8L4L5
J5J6J7K4K5
J4H6H5
E8 E9 F7 F8 F10
F12
G1
G2
G6
G10 H1 J1 J2 J3 J8 J9 J1
0
J12 K1 K2 K3 K9 K10
K12 L1 L2 L3 L9 L10
L12
M1
M2
M9
M10
M11
M12 F4 G4
H7G3E3
D3D4
E1
D12D11D2D1
C11C10C9C8C7C6C5C4C3C2C1B12B11B10B9B8B7B6B5B4B3B2B1A12A11A10A9A8A7A6A5A4
F9 F6
A3A2A1
GND
GND
GNDGND
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VINVINVINVINVIN
GND
GND
GND
GND
SW_2
GND
GND
VINVINVINVINVIN
GND
GND
GND
GND
SW_1
GND
GND
VINVINVINVINVIN
GND
GND
GND
GND
GND
GND
GND
GND
VINVINVINVIN
GND
GND
GND
GND
GND
GND
GMONTMON
PWN
VINVIN
TEST1
MODE/PLLIN
TEST3
GND
TEMP+TEMP-
GND
BIASRUNPPHMODE
GND
FREQ
SGND
CLKOUT
GND
GND
GND
OTP_SET
GND
PVCC
GND
GND
INTVCC
TEST2
SGND
HIZREG
SNSP1SNSP2
OVP_SET
CROWBAROVP_TRIP
GND
GND
GND
GND
COMPA
VFB
TRACK/SS
RUNC
PGOOD
VOUTVOUT
OVER_TEMP
GND
GND
GND
GND
COMPB
VOUTS1+VOUTS1-
VOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUTVOUT
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
0V85 PS, 1V8
INTERNAL PULL-UP
400KHZ
60DEG PHASE
1.8V, 4A
0.85V, 6A
34 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
22UF
40
22UF
41
22UF
39
22UF
37 36
22UF
38
22UF 22UF
42
11
143K
26
30.1K
68PF25
17
DNI
68PF
15
23
100K
0
12
DNI
17
DNI
DNI
14
44
2200PF10
2200PF
LTM4628IY#PBF
0.1UF0.1UF
24
9
2.2
2.2
13
100UF
43
100UF 100UF
22 19
21
100UF 100UF
31
28
33DNI
16
4.7UF
1
45
100UF
35
100UF
30
100UF
29
100UF
46
DNI
100UF
34
20
27
C485C483C473 C474 C475 C478 C484
C476
C482
R191
R555
R190
C497
C481
R193
R194C477
C479
C480
C498
C486
R189
R188
C488 C490 C492 C494 C496
TP32
U16
C487 C489 C491 C493
TP31
C495
TP33
R192
0V85_PS_SNS_P
1V8
12V0
0V85_PS
CLKOUT_400K_2
EN_0V85_PSEN_1V8
CLKOUT_400K_1
0V85_PS_SNS_N
12V0
1V8
0V85_PS
E9E3 E1
2
G9
D5
G11
F9G2
F5F4
E8E7E6D7
C6
M11M10M9M8M7M6M5M4M3M2
L11L10L9L8L7L6L5L4L3L2
K11K10K9K4
A6 B6A7 D1B7 D2 D4D3 D9 D11
D10 E1D12 E2 E4 E11
E10 F2F1
K3
J11K2
J10J9J4J3J2
F10F3 F11
G1
F12
G12
G10G3 H2H1 H3 H5H4 H7H6 H9 H11
H10 J1
H12 J5 J12J8 K5K1 K6 K8K7 L12L1K12
M12M1 D6C7 F6 G7
G6F7
G4
J6
G8
G5
D8E5
F8
C5C8
C12
C9
C11C10
B12B11
B9B8
B10
A12A11
A9
C4
A8
A10
C3
C1C2
B4B5
B3
H8 J7
B1B2
A4A5
A3A2A1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VINVINVINVINVINVINVINVINVINVIN
GND
GND
VINVINVINVINVINVINVINVINVINVIN
GND
GND
VINVINVIN
GND
GND
GND
GND
VINVINVIN
GND
GND
VINVINVIN
GND
EXTVCC
TEMP
GND
VINVINVIN
GND
GND
GND
GND
GND
ITNVCC
GND
GND
GND
GND
GND
GND
GND
GND
SW2
GND
PGOOD1PGOOD2
SGND
SGND
CLKOUT
PHASMD
GND
SW1
GND
GND
GND
GND
RUN2
DIFFOUT
SGND
SGND
RUN1MODE_PLLIN
GND
GND
GND
GND
GND
GND
DIFFNDIFFPCOMP2COMP1
TRACK1
GND
GND
GND
GND
GND
GND
GND
GND
TRACK2VFB2
SGND
VFB1
GND
GND
GND
GND
VOUT2VOUT2VOUT2VOUT2
VOUTS2
SGND
FSET
VOUTS1
VOUT1VOUT1VOUT1VOUT1
VOUT2VOUT2VOUT2VOUT2VOUT2
GND
GND
VOUT1VOUT1VOUT1VOUT1VOUT1
VOUT2VOUT2VOUT2VOUT2VOUT2
GND
GND
VOUT1VOUT1VOUT1VOUT1VOUT1
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
0.85V, 1A
1.8V, 1A
MGTRAVCC, MGTRAVTT
35 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
22UF
17
10UF
1DNI
2
10UF
16
10UF
30.1K
143K
10PF
10PF14
20
47UF
4
47UF
DNI
47UF
47UF
LTM4622IY#PBF
3
8
5
1315
6
DNI
11
DNI
22
DNI
21
DNI7
DNI
0.1UF
47UF
47UF
0.1UF
9
12
2.2UF
C636 C637 C641C638
R216
C640
R215
C639
C648
C644 C647
TP57
TP58
C645C642
R218
U20
C650
C646C643
C651
R217
C649
C652
1V8_MGTRAVTT
0V85_MGTRAVCC
1V8_MGTRAVTT
0V85_MGTRAVCC
EN_MGTAVTT
12V0
INTVCC_LTM4622_1
EN_MGTAVCC
INTVCC_LTM4622_1
A3E3
A2
E5A5
E4A4
C4
B5 C1 C2 D5
C3
D4B4
D2B2
C5
B3
E2
D1E1
B1D3 A1
GND
GND
GND
GND
GND
GND
GND
GND
GND
COMP1
FB1
TRACK/SS1
VIN
VOUT1
GND
PGOOD1
VIN
RUN1
VOUT1
SYNC/MODE
FREQ
INTVCC
GND
GND
GND
PGOOD2
VIN
RUN2
VOUT2
COMP2
FB2
TRACK/SS2
VIN
VOUT2
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
60DEG PHASE
INTERNAL PULL-UP
1.2V, 6A
0.9V, 6A
MGTAVCC, MGTAVTT
400KHZ
36 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
4
22UF 22UF
9 2
22UF22UF
3 6
22UF 22UF
7
22UF
8
17
DNI
DNI
29
LTM4628IY#PBF
36DNI
100UF
R0402L
121K
21
68PF11
60.4K
R0402L
68PF
2200PF13
100UF 100UF
2737
32
DNI
100UF100UF
33
100UF
16
2200PF2.2
2.212
14
31
26
0.1UF
19
34
15
4.7UF
5
10 17
30
0.1UF
DNI
DNI
24
22
20
23
25
100K
18
100UF100UF 100UF
1
28
100UF
35C611 C612 C615C610 C620 C621 C622
R556
R213
C633
C632
R209
R211
R212
C613
C626 C628C624
C629
TP54
TP53
C616
C617R210
C625
C634
C623
U19
TP55 TP56
C635C614
C618
C619
R214
C627 C631
C630
12V0
12V0
0V9_MGTAVCC_SNS_P0V9_MGTAVCC_SNS_N
CLKOUT_400K_2
1V2_MGTAVTT
EN_MGTAVCCEN_MGTAVTT
1V2_MGTAVTT
0V9_MGTAVCC
0V9_MGTAVCC
H7 J1
J6
G4
G8G9
E5
G6K8
F9G2
F5
D7
M1 C7M
12
C8C5
F8
L11
B3
A10
G11
F4
E6E7E8
C6
M10M11
M9
A7A6 B6 D1B7 D3D2 D4 D10D9
M7M6M5M4
M2
L10L9L8L7L6L5L4L3L2
K11K10K9K4K3K2
J11J10J9J4
J2J3
D12
D11 E1 E3E2 E11
E10E4 F1E12 F2 F10F3 F12
F11
G1
G10G3 H1G
12 H2 H4H3 H6H5 H10H9 H12
H11 J8J5 J12 K5K1 K7K6 L1K12
L12 D6 F7F6 G7
D8
G5
C12C11C10C9B12B11B10B9B8A12A11
A9A8
C4C3C2
B5B4
H8 J7
B2
A4A3
A1A2
M3
D5
M8
A5B1
E9
C1
GND
GND
GNDGND
GND
VINVINVINVINVINVINVINVINVINVIN
GND
GND
VINVINVINVINVINVINVINVINVINVIN
GND
GND
VINVINVIN
GND
GND
GND
GND
VINVINVIN
GND
GND
VINVINVIN
GND
EXTVCC
TEMP
GND
VINVINVIN
GND
GND
GND
GND
GND
ITNVCC
GND
GND
GND
GND
GND
GND
GND
GND
SW2
GND
PGOOD1PGOOD2
SGND
SGND
CLKOUT
PHASMD
GND
SW1
GND
GND
GND
GND
RUN2
DIFFOUT
SGND
SGND
RUN1MODE_PLLIN
GND
GND
GND
GND
GND
GND
DIFFNDIFFPCOMP2COMP1
TRACK1
GND
GND
GND
GND
GND
GND
GND
GND
TRACK2VFB2
SGND
VFB1
GND
GND
GND
GND
VOUT2VOUT2VOUT2VOUT2
VOUTS2
SGND
FSET
VOUTS1
VOUT1VOUT1VOUT1VOUT1
VOUT2VOUT2VOUT2VOUT2VOUT2
GND
GND
VOUT1VOUT1VOUT1VOUT1VOUT1
VOUT2VOUT2VOUT2VOUT2VOUT2
GND
GND
VOUT1VOUT1VOUT1VOUT1VOUT1
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
3V3, 2V5 VPP_DDR
2.5V, 0.75A
3.3V, 0.75A
REPLACE 0.1%
37 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
10UF
21DNI
8
10UF10UF
10PF
19.1K
13.3K
10PF
DNI
2.2UF
216
6
100K
20
DNI22
649K
12
DNI
19
DNI
15
11
13
4
7
5
0.1UF 0.1UF
47UF 47UF
DNI
47UF 47UF
DNI
LTM4622IY#PBF
C596 C600C597
R206
C599
R205
C598
R204
C609
R207
R208
C604C601
TP52
TP51
C608C607
C605C602
C606C603U40
2V5_VP_DDR4
PG_3V3_2V5
2V5_VP_DDR4
3V3
3V3
EN_3V3_2V5
12V0
INTVCC_LTM4622_2
12V0
INTVCC_LTM4622_2
COMP1
FB1
TRACK/SS1
VIN
VOUT1
GND
PGOOD1
VIN
RUN1
VOUT1
SYNC/MODE
FREQ
INTVCC
GND
GND
GND
PGOOD2
VIN
RUN2
VOUT2
COMP2
FB2
TRACK/SS2
VIN
VOUT2
GND
GND
GND
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
0.6V, 3A
1.2V, 3A
1.2V, 3A
DDR4 SUPPLIES
0.6V, 3A
38 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
22UF
36
32
22UF22UF
8
22UF
5
22UF
2
22UF
9
10UF
26
10UF
10UF10UF
1UF
0.1UF
4.7UF
100UF
100UF
15
4.7UF
100K
LTM4632IY#PBF
LTM4632IY#PBF
100UF
100UF
100UF
100UF
100UF
0.1UF
1UF
1UF
4.7UF
4.7UF4.7UF
4.7UF
DNIDNI 4700PF
4700PFDNIDNI
37
19 20
17
2 313
2322 18
8
5
24
6
1
25
DNI21
100UF
4.7UF
100UF
412
4.7UF
1614
1UF
60.4K
0.1UF
100UF
7
R0402L
60.4K
0.1UF
100PF
100PF
C503
C504C500 C502
C501C499 C505 C509
C510C507
C1119 C515
C514 C523
C535C528
TP37
C539
C513
C1120
U17
C527 C533
C536
C522
C516C511 C521
C537
C540C538C532C526
C517
C518
C530
C524
C519
C520C512
TP35
R195
R196
TP40 TP41
C531
TP38
C525
C529
TP34
TP36
C534
R197
C508
U18
C506
TP39
1V2_PS_DDR4
1V2_PS_DDR4
VREF_PS_DDR4
12V0
1V2_PL_DDR4
PG_DDR4
12V0
VTT_PS_DDR4
1V2_PS_DDR4
EN_1V2_DDR4
PG_DDR4
VTT_PL_DDR4
VREF_PL_DDR4
12V0
1V2_PL_DDR4
1V2_PL_DDR4
EN_1V2_DDR4
E4A4
E3
A1E1
E5A5
B5 C4
C3
D4B4
D2B2
C5
A2B3D3E2
D1
B1
A3
E5A5
B5
C4D5
C3
D4B4
D2B2
C5
E3
A4
D3E1A1B1
A3
D1
E4
B3
E2
A2
C1 C2
D5C2C1
GND
GND
GND
GND
GND
GND
COMP1
FB1
TRACK/SS1
VIN
VOUT1
GND
PGOOD1
VIN
RUN1
VOUT1
SYNC/MODE
GND
INTVCC
GND
GND
GND
PGOOD2
VIN
RUN2
VOUT2
COMP2
VDDQIN
VTTR
VIN
VOUT2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
COMP1
FB1
TRACK/SS1
VIN
VOUT1
GND
PGOOD1
VIN
RUN1
VOUT1
SYNC/MODE
GND
INTVCC
GND
GND
GND
PGOOD2
VIN
RUN2
VOUT2
COMP2
VDDQIN
VTTR
VIN
VOUT2
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
CLKOUT ON SYNC/MODE
RF SUPPLIES
WITH LDOSWITHOUT LDOS
R350 | R348 | R34910.7K | 38.3K | 23.2K6.34K | 31.6K | 12.7K
1.65V, 3A
2.65V, 1A
1.3V, 3A
3.8V, 2.5A
39 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
10UF
1
10UF
68
10UF
27
10UF
2
ADP5054ACPZ
10.2K
0
37
0.1
47UF
48
470OHM AT 100MEGHZ
23.2K
56
38.3K
10.7K
42
DNI37.4K
0
27.4K DNI
55
54
0
46
6.34K
63
33
47K DNI
DNI32
47K
10.7K
DNI
43
23
0
22.1K
14
20K
61
20K
16
10K
66
10K
26
DNI
7147K
64
100K
65
DNI
70100K
73
47K
72 10K
22
DNI
5267
0
100K
59
604K
60
100K
74
DNI
47
10K
10K
53
10K
44
19
2.2UH
2.2UH
17
21
0.1UF
6.8UH
470OHM AT 100MEGHZ
SIA906EDJ-T1-GE3
0.01UF
47UF
28
47UF
47UF
470OHM
47UF
9
8
47UF5
62
38
34
45
470OHM AT 100MEGHZ
47UF40
47UF
39
41
1UF
13
1UF
12
0.01UF
0.01UF
51
0.01UF
24
0.0033UF
58
0.0033UF
15
0.0027UF
69
0.0027UF
25
6
47UF
0.1
0.1
3
11
0.1UF
0.47
6.8UH
10
0.1UF
47UF
22UF
57
47UF
47UF
47UF
0.1UF
7
20
75
30 31
35
36
50
29
49
4
18
C868
C869
C866
C867
R357C896
R349
R348
R350
R354
R346
R355
R347
R353
R345
R341
R340
R351
R344
R337
R335
R334
R333
R332
R322
R324 R328
R323
R329R325
R339
R331R327
R330R326
R336
R352
R343
R342
R338
L13
L12
L15
TP84
L14
E27
C893
R356
C894
C888
E25
C895
C891
C889
C890
C886
E24
C870
C875
C882
C883
C881
C880
C874
C873
C872
C871
R358
C897
C876
C878
U45
R359
C877
E26
TP82
TP85
TP83
TP86
TP66TP65
C885
C879TP64
TP63
C884
C887
C892
Q1
VDDA3P8
CLK_ADP5054
VDD1P3_DIG_A
VDDA2P65_A
VDDA1P65_ANLG_A
VREG_ADP5054_A
VDDA1P3_ANLG_A
VREG_ADP5054_A
EN_RF
VDD1P3_DIG_A
12V0
EN_RF
EN_RF
VREG_ADP5054_A
2726
PAD1
45
37
47
3
29
6
4
25
14
17
3
PAD2
2 51
4
32
28
1
12
18
13
40
20
15
3139
21
48
41
19
46
16
30
2
1011
36
38
222324
6
7
42
333435
5
89
44
43
PAD
GND
EPAD
EN3
COMP3
FB3
VREG SYNC/MODE
VDD RT
FB1
COMP1
EN1
PVIN1PVIN1PVIN1
SW1SW1SW1
BST1
DL1
PGND
DL2
BST2
SW2SW2SW2
PVIN2PVIN2PVIN2
EN2
COMP2
FB2
CFG12
PWRGD
FB4COMP4
EN4
CFG34
BST4
PGND4PGND4
SW4SW4
PVIN4
PVIN3
SW3SW3
PGND3PGND3
BST3
D2
D1
S2G2
D2
S1G1
D1
GNDGND
GNDGND
GNDGNDGND
GND GND GND GNDGND
GNDGNDGNDGND
GND
GND
GND
GND
GND
GND
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
CLKIN ON SYNC/MODE
RF SUPPLIES
WITH LDOSWITHOUT LDOS
10.7K | 23.2K6.34K | 12.7K 1.65V, 3A
R314 | R313
1.3V, 3A
1500MA
2.65V, 1A
40 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
10UF
6
11
10UF
10
10UF
32
10UF
0.0033UF
0.0033UF
ADP5054ACPZ
13
23.2K
10.7K
55
2
499K
23
200K
10.7K
62
DNI
35
0
27.4K DNI
14
26
0
30
0
10K
34
DNI60
47K
47K59
DNI
42
22.1K
33
10K
10K
19
40
20K
DNI
24
100K
1817
47K
16
0
22
100K47K
21
28
20K
49
6.34K
15
DNI
20
DNI
10K
45
DNI
25
10K
10.2K
44 2.2UH
50
54
2.2UH
470OHM
48
0.01UF
22UF
52
470OHM AT 100MEGHZ
47UF
51
47UF
0.1UF
0.1
43
47UF
470OHM AT 100MEGHZ
67
56
47UF0.01UF
36
27
31
0.01UF
0.0027UF
41
12
0.0027UF
37
29
38
1UF
1UF
39SIA906EDJ-T1-GE3
0.1UF
0.1UF1
47UF
63
0.1
4
7372
68
69
61
6665
57
64
47
53
7
8
46
5
9
58
3
47UF
47UF47UF
47UF 47UF
0.47
6.8UH
C839
C840
C841
C842
R313
R314
R298R294
R315
R310
R317
R311
R312
R306
R307
R308
R304
R300
R301
R302
R299
R296R292
R295
R297R293
R303
R316
R290
R291
R318
R309
R305
L10
C853
L9
C859
C849
C862
R320C858
E22
E23
C861
E21
C852
C854
C844
C845
C846
C847
C843
C848
C850 TP79
TP81
TP80
C865C855
R319
U44
TP62TP61
TP59
TP60
Q7
C863
C860
C856
C864C857
R321
L11
C851
VDDA2P65_B
VDDA1P65_ANLG_B
CLK_ADP5054
VREG_ADP5054_B
VDD1P3_DIG_B
VDDA1P3_ANLG_B
12V0
VREG_ADP5054_B
EN_RF
EN_RF
VDD1P3_DIG_B
EN_RF
VREG_ADP5054_B
6
4
152
PAD2
3
PAD1
GND GNDGNDGNDGND
GND
GND
GNDGND
GND
GND
GNDGND
GND
GND
GND
EPAD
EN3
COMP3
FB3
VREG SYNC/MODE
VDD RT
FB1
COMP1
EN1
PVIN1PVIN1PVIN1
SW1SW1SW1
BST1
DL1
PGND
DL2
BST2
SW2SW2SW2
PVIN2PVIN2PVIN2
EN2
COMP2
FB2
CFG12
PWRGD
FB4COMP4
EN4
CFG34
BST4
PGND4PGND4
SW4SW4
PVIN4
PVIN3
SW3SW3
PGND3PGND3
BST3
GNDGND
GND
D2
D1
S2G2
D2
S1G1
D1
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE
1.8V, 0.6A
1.3V, 3A
3.3V, 2A
3.3V, 0.4A
3.3V, 0.4A
1.3V, 3A
1.8V, 0.6A
3.3V, 0.4A
RF SUPPLIES - LDO
41 41
<DESIGN_VIEW>
: NAProduct(s): ADRV9009HW TYPE : Customer Evaluation
1:1
A02_048949
<PTD_ENGINEER>
4.7UF 4.7UF
ADM7154ACPZ-1.8
0.01UF1UF
10UF 1UF
0
0
10UF 1UF
10UF 1UF
10UF
R0402L
10UF
ADP124ACPZ-3.3
ADP1763ACPZ-1.3
22UF
ADM7154ACPZ-3.3
ADP7158ACPZ-3.3-R7
10UF
R0402L
1
0.1UF 1UF
TBD0402
0.01UF DNI
10UF TBD0402
1UF
DNI
1UF
10UF 1UF
22UF
0.1UF
7
0
ADM7154ACPZ-1.8
R0402L
R0402L
R0402L
TBD0402
TBD0402
TBD0402
8.66K
8.66K
0
0
0
0
1UF0.1UF
0.1UF
ADM7154ACPZ-3.3
1UF 1UF
10UF
22UF 22UF
10UF
1UF0.1UF
ADP1763ACPZ-1.3
1UF
22UF 22UF
2
10UF
2
10UF
10UF
3
10UF
5
10UF
6
1UF
1
1UF
3
5
6
JP8
TP71
C797
JP7
JP6
JP5
TP50
R530
R531
TP130
C820 C823
C819 C822
C827
R496
TP72 TP74
TP75
C824
JP2
JP4
C816
C832
TP76
R493C828
R492
R497
JP3
C814
C798
TP67
C804
C796
U23
C806
R287
C800
C805
C801
JP1
TP68
C811
C812C803
R491
R490
R488
R288
R489
R495
R494
U22
U26
C830
C829
C833
C834
C362
U24
C361
U28
TP77
C835
U25
C837
TP78
C825
C831 C836
U27
C838
TP73
C817
C809 C815
C818
U43
C810
C807
C813
C802 C808
TP69
TP70
C795
C826
C799
VDDA3P3
VDDA1P8_A_P
VDDA1P8_A_N
VDDA1P8_A
VDDA1P3_ANLG_B
VDDA3P3_VCXO
VDDA2P65_B
VDDA3P8
VDDA3P8
VDDA1P3_ANLG_B_N
VDDA3P8
VDDA3P8
VDDA3P8
VDDA3P8
VDDA1P65_ANLG_A
VDDA1P8_B
VDDA2P65_A
VDDA1P3_ANLG_A_N
VDDA3P3
VDDA1P3_ANLG_A
VDDA3P3_CLK
VDDA1P3_ANLG_SNS_A
VDDA1P65_ANLG_B
VDDA2P65_A
VDDA1P3_ANLG_B_P
VDDA3P3_VCO
VDDA1P65_ANLG_B
VDDA1P3_ANLG_SNS_B
VDDA1P3_ANLG_A_P
VDDA2P65_B
VDDA3P3_P
VDDA3P3_N
VDDA3P3_VCO_P
VDDA3P3_VCO_N
VDDA3P3_VCXO_P
VDDA3P3_VCXO_N
VDDA3P3_CLK_P
VDDA3P3_CLK_N
VDDA3P3_VCO
VDDA1P65_ANLG_A
VDDA3P8
VDDA3P8
VDDA3P3_CLK
VDDA3P3_VCXO
VDDA1P3_ANLG_B
VDDA1P8_B_P
VDDA1P8_B_N
VDDA1P8_B
VDDA1P8_A
VDDA1P3_ANLG_A
1
137
PAD
10
12
13
3 2
16
7
4
5
PAD4 6
8 23
1
2
15
16
7 PAD
5
14
8
1 2 3 4
9
11
6
13
15
4
7
5
14
8
1 2 3 4
9101112
6
PAD
68
8
PAD
3 2576
4
5
78
1
5
PAD
6
GND GND
EP
VINEN
REFREF_SENSE
GND
BYP VOUTVREG
GND
GND
GND
GND
GND
PAD
EN
PG
SS
SENSEVOUTVOUTVOUTVOUT
VADJ
GND
VREG
REFCAP
VIN
VIN
VIN
VIN
GND GND
GND
GND
EP
VINEN
REFREF_SENSE
GND
BYP VOUTVREG
GND
GND
GND
GND
GNDGND
GND
GND
EP
VINVIN
NC
EN
GND
VOUT_SENSEVOUTVOUT
GND
GND
EP
VINEN
REFREF_SENSE
GND
BYP VOUTVREG
GND
GND
GND
GND
GND
GND
GND
GND
GND
EP
VINEN
REFREF_SENSE
GND
BYP VOUTVREG
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
EP
VINVIN
VREG
REFREF_SENSE
EN
BYP
VOUT_SENSE
VOUTVOUT
GND
GNDGNDGND
GND
GND
GND
GND
GND
GND
PAD
EN
PG
SS
SENSEVOUTVOUTVOUTVOUT
VADJ
GND
VREG
REFCAP
VIN
VIN
VIN
VIN
D
THIS DRAWING IS THE PROPERTY OF ANALOG DEVICES INC.
IN PART, OR USED IN FURNISHING INFORMATION TO OTHERS,
OR FOR ANY OTHER PURPOSE DETRIMENTAL TO THE INTERESTS
THE EQUIPMENT SHOWN HEREON MAY BE PROTECTED BY PATENTS
AC
IT IS NOT TO BE REPRODUCED OR COPIED, IN WHOLE ORDRAWING NO.
2
SCALE
DDDSIZE
D
REV
SHEET
1
1
A
234
35
8
D
7
678
A
B
C C
D
5
4
APPROVED
B
6
DESCRIPTION
REVISIONS
OF
OL GE
OWNED OR CONTROLLED BY OWNED ANALOG DEVICES.
EAN
V
OF ANALOG DEVICES.
SCHEMATIC
S
PTD ENGINEER
DESIGN VIEW
REV DATE