J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 1 / 32
Tallinn Technical University :: May 4th 2009This presentation is available at http://www.slideshare.net/josemmf
Tallinn Technical University :: May 4th 2009This presentation is available at http://www.slideshare.net/josemmf
J. M. Martins Ferreira
FEUP / DEEC - Rua Dr. Roberto Frias
4200-537 Porto - PORTUGAL
Tel. 351 225 081 889 / Fax: 351 225 081 443
Boundary-scan test for structural fault detection
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 2 / 32
Part 1
Outline
1. Introduction to the IEEE 1149.1 boundary-scan test (BST) standard
2. The remote BST controller (MWS-TAP)
Break
3. The demonstration board
4. Open and short fault detection
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 3 / 32
• Why do we need it and for what?
• The test principle
• BS cells and test architecture
• The on-chip controller
• The test modes (instructions)
1: The IEEE 1149.1 std (boundary-scan test)
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 4 / 32
Why Boundary Scan Test?• The two main reasons that led in the mid-
80s to the development of BST were:– The complexity of ICs made it exceedingly
difficult to develop test programs for the functional test of complex PCBs
– Small outline surface mount devices and advanced mounting technologies almost disabled physical access to internal PCB nodes and made in-circuit test exceedingly difficult
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 5 / 32
The application domain of BST• BST addresses the structural test of
digital printed circuit boards
• Keywords: structural, digital, PCBs
• This embedded test infrastructure is now used for other purposes as well (e.g. in-system programming)
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 6 / 32
The BS test principle
• BS uses a Test Access Port (TAP) to decouple the internal IC logic from the pins and allows “direct” access to any PCB node without backdriving effects
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 7 / 32
The basic BS cell
• Three modes of operation:– Transparency– Controllability– Observability
RegistoBST
Serial input
Parallel input
Parallel output
Serial output
mux
mux
C/S L
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 8 / 32
The BS architecture• Main blocks:
– BST register– BP register– Instruction register– TAP controller– Other registers
User data reg.
Identific. reg.
BP reg.
Decoder
Instruction reg.
Data mux
Data / instr. mux
TAP contr.
TDI
/TRST
TMS
TCK
TDO
BST register
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 9 / 32
Serial input
Parallel input
Parallel output
Serial output
mux
mux
C/S L
TAP controller state transition diagram1
0
Shift DR
Capture DR
Select DR
Exit-1 DR
Pause DR
Exit-2 DR
Update DR
Test LogicReset
Run Test /Idle
Shift IR
Capture IR
Select IR
Exit-1 IR
Pause IR
Exit-2 IR
Update IR
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1 1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
User data reg.
Identific. reg.
BP reg.
Decoder
Instruction reg.
Data mux
Data / instr. mux
TAP contr.
TDI
/TRST
TMS
TCK
TDO
BST register
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 10 / 32
BST instructions
• Mandatory:– EXTEST– SAMPLE / PRELOAD– BYPASS
• Optional:– INTEST, RUNBIST,
CLAMP, IDCODE,USERCODE, HIGHZ
User data reg.
Identific. reg.
BP reg.
Data mux
Data / instr. mux
TDO
BST register
BST register
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 11 / 32
2: The remote BST controller (MWS-TAP)
• Why / What is it for?
• The hardware setup
• Configuration
• The MWS-TAP application
• The test program
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 12 / 32
Why / what for?
• To enable the students to write real test programs in SVF and to execute online
• To provide a tool for test program validation
• To facilitate hands-on sessions with real 1149.X hardware
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 13 / 32
Setup: The MWS board
• The micro web server TAP controller application uses a DSTINIm400 evaluation board (with a networked microcontrollerfrom Maxim-Dallas)
• The current prototype controls one BS chain
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 14 / 32
MWS board: the JTAG pinsT
MS
TC
KT
DO
TD
I
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 15 / 32
Setup: IP and connections• An RS232C port can be
used to program a valid IP address into the micro web server board
• The server application can then be loaded by FTP and launched via Telnet
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 16 / 32
Set up (cont.)
• If the current IP of the MWS is known, a quicker set up procedure is possible:– Connect the card directly to a computer using a
regular LAN cable and telnet to its IP address– Set up the new IP address (cuts the current
connection if in different subnets), e.g. ipconfig -a 158.36.164.12 -m 255.255.254.0 -g 158.36.164.1
– Set the current IP of the computer to the same subnet and reconnect (or use the LAN)
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 17 / 32
MWS-TAP – set IP address and connect
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 18 / 32
MWS-TAP – Open / write a new SVF test program
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 19 / 32
Short break!
Tallinn Technical University :: May 4th 2009
Boundary-scan test for structural fault detection
Tallinn Technical University :: May 4th 2009This presentation is available at http://www.slideshare.net/josemmf
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 20 / 32
Part 2
Outline of this talk
1. Introduction to the IEEE 1149.1 boundary-scan test (BST) standard
2. The remote BST controller (MWS-TAP)
Break
3. The demonstration board
4. Open and short fault detection
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 21 / 32
3: The demonstration board
• What’s in it?
• Schematic
• Integrity check
• BS in practice (led control)
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 22 / 32
Block diagram of the demonstration board
net 232Y3O7
O6
O5
O4
O3
O2
O1
O0
I7
I6
I5
I4
I3
I2
I1
I0
0
1
2
3
4
5
6
7
8
9
17
16
15
14
13
12
11
10
0
1
2
3
4
5
6
7
8
9
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
10
11
12
13
14
15
16
172Y2
2Y1
2Y0
/1Y3
/1Y2
/1Y1
/1Y0
A1
B1
A2
B2
A3
B3
A4
B4
Y1
Y2
Y3
Y4
net 22
net 21
net 20
net 19
net 18
net 17
net 16
net 7
net 6
net 5
net 4
net 3
net 2
net 1
net 0
net 11
net 10
net 9
net 8
net 14
net 15
Cluster 0BS Component 0 BS Component 1 Cluster 1
BS Component 2
TDI 0
TDO 0
TDO 1
TDI 1
net 13
net 12
A
B
/G1
/G2
S /G
(IC3) (IC1 and IC2) (IC4) (IC6)
(IC5)
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 23 / 32
Schematic diagram
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 24 / 32
Integrity check of the BS infrastructure• Detection of:
– Faulty TAP pins– Faulty / misplaced components
• Sequence of operations:– Reset (TRST or 5 x TMS1)– IR capture and scan– ID capture and scan (if supported)
XX...X01 XX...X01 XX...X01
TDI
TDO
TDI TDI
TDO TDO
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 25 / 32
Led control
• What BS instruction?
• What test vector (into the BS register)?
inst
ruct
ion
sB
S r
egis
ter
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 26 / 32
MWS-TAP – Example (led control)
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 27 / 32
4: Open and short fault detection
• Detection of an open fault
• Detection of a short-circuit
• Further recommended exercises
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 28 / 32
Detection of open circuit X1• What
conditions enable the detection of open circuit X1?
/G A B /Y0 /Y1 /Y2 /Y3
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 29 / 32
Detection of short-circuit X2
/G A B /Y0 /Y1 /Y2 /Y3
• What conditions enable the detection of short circuit X2?
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 30 / 32
Detection of short circuit X9• What conditions enable the detection of
short-circuit X9?
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 31 / 32
• What conditions enable the detection of short- circuit X16?
Detection of short circuit X16
J. M. Martins Ferreira - University of Porto (FEUP / DEEC)Tallinn Technical University :: May 4th 2009 32 / 32
Tallinn Technical University :: May 4th 2009This presentation is available at http://www.slideshare.net/josemmf
Tallinn Technical University :: May 4th 2009This presentation is available at http://www.slideshare.net/josemmf
Boundary-scan test for structural fault detection
Thanks for your attention!
J. M. Martins Ferreira [ [email protected] ]