May 1, 2013 1
Introduction toAnalog Ultra Low Power (AULP)
design
Tuvia LiranNano Retina Ltd.
May 2013
May 1, 2013 2
Definition of Ultra Low Power
A design methodology that enables implementing VLSI products with power consumption in the sub microwatt range
• Comment: Some applications provide very low power consumption by activation during short period of time, but it is not ULP
• How it is achieved:– Very low voltage - <1 OOM– Sub-threshold operation – 2-5 OOM– Micro-architecture
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Outline• Applications of ULP• Low voltage operation• Power sources• MOS operation at sub-threshold range• Challenges of ULP design:
– Architecture– Device modeling
• Analog circuits operating at ULP• Discrete Time Analog (DTA) circuits• ULP data converters• Summary
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Applications of low-voltage AULP
• Medical devices (implantable; wearable)• Remote controllers• Wireless sensors• Watches
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Why low voltage?
• For digital circuits: – Reduced dynamic power (P=C*V2*f)– Reduced electric fields in scaled devices
• For analog circuits:– Typically requires higher power for same BW– Low BW applications can operate with low voltage– Integration of low power digital + RF
Medical devices often require very low frequency
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Power sources• Batteries (size, duration)• Energy harvesting• Remote power transfer
Bio-Retina Implant
Retina
IR laser beam
1
2
53
4
Optical power transfer(Nano Retina)
Electromagnetic power transfer (Second Sight)
Examples of implementations of artificial retina
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MOS operation ranges• Operating in sub-threshold (weak
inversion)
• Voltages are scaled to nUT (32 mV for n = 1.2 )
• ∆Id/∆Vgs = 70÷80mV/decade • Weak inversion expression:
T
TGsDsat nU
VVII 0exp
C37at mV 7.26 Tq
kTUT
Power consumption in the nW range force the operation in sub-threshold
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Challenges in low voltage AULP• Limited dynamic range• Large process variance and mis-
match• Non-linear (logarithmic) Id/Vgs• Modeling of devices • Noises (flicker; coupling; substrate)• Limited bandwidth• Charge injection in SC circuits
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AULP design techniques• System level:
– Avoiding DC-DC up-converter – Optimized partitioning to digital/analog/DTA
• Circuit level:– Operation at moderate/weak inversion– Optimal Vt (low Vt devices; Vsb<0)– Use bulk driven MOS transistors– Avoiding stacking of transistors
DTA = Discrete Time Analog
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Device modeling for weak inversion
• BSIM (Berkley):– Parameters have physical meaning– Most widely used– Poor accuracy in moderate inversion
(non-monotonic)• EKV (EPFL):
– Charge based models– Only 18 parameters. Simpler to
generate– Works well in strong & weak inversion
• PSP (ASU & Philips):– Approved as “next industry standard”
by “compact modeling council”– Based upon looking at surface
potential
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Low voltage current mirrors - examples
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Bulk driven amplifiers
• Enables amplifying low/negative signals
• Lower gain and GBW• Requires isolated well• Higher noise
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Example of sub-threshold low voltage circuit – ULP amplifier
Presented by E. Vittoz
Amplifier with controlled offset
Amplifier with extended
dynamic range
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Static high value resistors• Often require >GΩ resistors• Alternative implementations:
– Polysilicon inverse direction diodes– PMOS inverse direction sub-threshold– Switched resistor
• Both options have poor accuracy & matching• Switched resistor is disturbed by charge injection
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Discrete Time Analog (DTA) circuits
• Switched capacitor filters• Chopped amplifiers• ULP ADC• ULP DAC
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Switched capacitor filters• Enables very low BW when frequency is low• Disturbed by charge injection (αCm/Cs)• Differential or CMOS implementations reduces the
charge injection significantly
NMOS CMOSDifferential
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Chopped Amplifier• Cancels offset almost completely• Relevant for differential amplifiers only• Ø1 – direct | Ø2 – inverted inputs and outputs• Vos is modulated at phase frequency and filtered by LPF
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ADC - Figure of Merit
Power=FoM*Fs*2ENOB [There are other definitions]
World record: 4.4fJM. van Elzakker, E. van Tuijl, P. Geraedts, D. Schinkel, E. Klumperink, and B. Nauta, “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s charge-redistribution ADC,” Proc. of IEEE Solid-State Circ. Conf. (ISSCC), San Francisco, California, pp. 244–245, Feb., 2008.
Example1: FOM=10fJ; Fs=1Msps; ENOB=10 -> Power=10µW
Example2: FOM=10fJ; Fs=1Ksps; ENOB=10 -> Power=10nW
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ULP DAC architecture
• R-2R architecture is an alternative architecture• Ratioed MOS transistors operating at weak inversion
act as linear resistive devices• Device matching degrades INL/DNL
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Summary
• ULP is enabler to many applications• ULP design is challenging but doable• Operation at low supply voltage is doable• ULP is processed with standard CMOS process flows