UC Regents Spring 2014 © UCBCS 152 L9: Memory
2014-2-18
John Lazzaro(not a prof - “John” is always OK)
CS 152Computer Architecture and Engineering
www-inst.eecs.berkeley.edu/~cs152/
TA: Eric Love
Lecture 9 -- Memory
Play:
UC Regents Spring 2005 © UCBCS 152 L14: Cache I
DRAM chip capacity: from 1Kb (1971) to 4Gb (2013)
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Gordon MooreUCB B.S. Chemistry 1950.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Today: State Storage Tools on Silicon ICs
VLSI == “Very Large Scale Integration”The tall thin designer, with feet
on the ground and head in the sky.
Carver Mead
The ground: Physics and IC FabricationThe sky: Architecture and Applications
Capacitance: Holds state as charge
Transistors: How to move charge
Architecture: Arrays and interfaces
DRAM: 1 Transistor + 1 Capacitor
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Today’s Lecture: DRAM
DRAM: Bottom-up
DRAM: Systems
DRAM: Top-down
UC Regents Spring 2005 © UCBCS 152 L14: Cache I
Capacitance and memory
Intel Micron 8 GB NAND flash device, 2 bit per cell, 25 nm minimum feature, 16.5 mm by 10.1 mm.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Recall: Building a capacitor
Conducts electricity well.(metal, doped polysilicon)
TopPlate
BottomPlate
Conducts electricity well(metal, doped polysilicon)
DielectricAn insulator. Does not conducts electricity at all.(air, glass (silicon dioxide))
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Recall: Capacitors in action
I = 0
Because the dielectric is an insulator, and does not conduct.
After circuit “settles” ...
Q = C V = C * 1.5 Volts (D cell)
Q: Charge stored on capacitor
C: The capacitance of the device: function of device shape and type of dielectric.
+++
+++
--- ---
After battery is removed:
+++
+++
--- ---Still, Q = C * 1.5 Volts
Capacitor “remembers” charge
1.5V
UC Regents Spring 2014 © UCBCS 152 L9: Memory
State is coded as the amount of energy stored by a device.
+++
+++
--- ---
Storing computational state as charge
State is read by sensing the amount
of energy
+++
+++
--- ---
1.5V
Problems: noise changes Q (up or down), parasitics leak or source Q. Fortunately,
Q cannot change instantaneously, but that only gets us in the ballpark.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
How do we fight noise and win?
Store more energy than we expect from the noise.
Q = CV. To store more charge, use a bigger V or make a
bigger C.Cost: Power, chip
size.Example: 1 bit per capacitor.Write 1.5 volts on
C.To read C, measure V.V > 0.75 volts is a “1”.V < 0.75 volts is a “0”.
Cost: Could have stored many bits on that capacitor.
Represent stateas charge in ways that are robust to noise.
Correct small state errors that are introduced by noise.
Ex: read C every 1 ms Is V > 0.75
volts?Write back 1.5V (yes) or 0V (no).Cost: Complexity.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
MOS Transistors
Two diodes and a capacitor in an interesting arrangement. So, we begin with a diode review ...
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Diodes in action ...
Light emitting
diode (LED)
Resistor
Light on?
Yes!
No!
Light on?
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Diodes: Current vs Voltage
Anode+
-Cathode
I V
Diode is onI ≈ Io
exp(V/Vo)
I = Io [exp(V/Vo) - 1]Io range: 1fA to 1nA Vo range: 25mV to 60 mV
Diode is offI ≈ - Io
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Making a diode on a silicon wafer
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A pure (”intrinsic”) silicon crystal ...
Conducts electricity better than an
insulator, worse than a conductor.Why? Most electrons
(dots) are in a full “valence” band.
Moving in the band is difficult.
Especially near 0 degrees K.
Many electrons, but packed too tight to move.
Lots of room, but few
electrons.
electron
energy
Valence band
Conduction band
Forbidden “band gap”
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Intrinsic silicon crystal as T rises ...
Some valence band electrons diffuse into the conduction band.
These electrons leave behind “holes” in the
valence band, allowing remaining electrons to
move easier.
We think of “holes” as positive carriers ...
More electrons,better
conduction
Valence band
Conduction band
electron
energy
UC Regents Spring 2014 © UCBCS 152 L9: Memory
We “engineer” crystal with impurities ...
UC Regents Spring 2014 © UCBCS 152 L9: Memory
N-type silicon: add donor atoms
Use diffusion or ion implantation to replace some of the Si atoms
with AsArsensic has an extra
electron that is “donates” to the conduction band.
Valence band
Conduction band
electron
energy
Electronsfrom donor
atoms.Improves
conductivy.
Donor energy
No change in the number of holes
n+ : heavy doping. n- : light doping.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
P-type silicon: add acceptor atoms
Use diffusion or ion implantation to replace some of the Si atoms
with BoronBoron has one fewer electron than Si. It can accept valence band electrons, creating
holes.
No change in conduction
band electron count
Acceptor energy
Number of holes increased, conductivity improves
Valence band
Conduction band
electron
energy
p+ : heavy doping. p- : light doping.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
How to make a silicon diode ...
Wafer cross-section
n+p-
Wafer doped p-type
n+ region
p- region
At V ≈ 0, “hill” too high for electrons to diffuse up.
V
Cathode: -
+
-
Anode: +
no carriers
depletion region
For holes, going “downhill” is hard.
V controls hill.
electron
energy
depletion region
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Diodes: Current vs Voltage
Anode+
-Cathode
I V
Diode is onI ≈ Io
exp(V/Vo)
I = Io [exp(V/Vo) - 1]Io range: 1fA to 1nA Vo range: 25mV to 60 mV
Diode is offI ≈ - Io
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Note: IC Diodes are biased “off”!
p-
n+
V1
0 V - “ground”
n+
V2V1 V2
V1, V2 > 0V. Diodes “off”, only current is Io “leakage”. I = Io [exp(V/Vo) - 1]Anodes of all diodes on wafer connected to ground.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
MOS Transistors
Two diodes and a capacitor in an interesting arrangement ...
UC Regents Spring 2014 © UCBCS 152 L9: Memory
What we want: the perfect switch.
p-
n+
V1
n+
V2Switch is off. V1 is not
connected to V2.
p-
V1
n+
V2Switch is on. V1 is
connected to V2.
We want to turn a p-type region into an n-type region under voltage
control.We need
electrons to fill valence holes
and add conduction
band electrons+++
+++
--- ---
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An n-channel MOS transistor (nFET)
p-
n+
Vd = 1V
n+
Vs = 0V Polysilicon gate,
dielectric, and substrate
form a capacitor.
nFet is off(I is
“leakage”)
dielectric
Vg = 0V
I ≈ nA
----------
p-
n+
Vd = 1V
n+
Vs = 0Vdielectric
Vg = 1V
+++++++++----------
Vg = 1V, small region
near the surface turns from p-type to
n-type.
nFet is on
I ≈ μA
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Mask set for an n-Fet (circa 1986)
p-
n+
Vd = 1V
n+
Vs = 0Vdielectric
Vg = 0V
I ≈ nA
#1: n+ diffusion
Top-down view:
Masks
#3: diff contact
#2: poly (gate)#4:
metalLayers to do p-Fet not shown. Modern processes have 6 to 10 metal layers (or more)(in 1986: 2).
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“Design rules” for masks, 1986 ...
#1: n+ diffusion
#3: diff contact#2: poly
(gate)#4:
metal
Poly overhang. So that if masks are misaligned, we still get “---” in channel.
Minimum gate length. So that the source and drain depletion regions do not meet!
length
Metal rules:Contact
separation from channel,
one fixed contact size, overlap rules
with metal, etc ...
UC Regents Fall 2013 © UCBCS 250 L1: Fab/Design Interface
Fabrication
UC Regents Fall 2006 © UCBCS 152 L11: VLSI
Mask set for an n-Fet ...
p-
n+
Vd = 1V
n+
Vs = 0Vdielectric
Vg = 1V
#1: n+ diffusion
Top-down view:
Masks
#3: diff contact
#2: poly (gate)#4:
metalHow does a fab use a mask set to make an IC?
Vg
Vd
Vs
Ids I ≈ μA
UC Regents Fall 2006 © UCBCS 152 L11: VLSI
Start with an un-doped wafer ...
Steps
p-
#1: dope wafer p-
#5: place positive poly mask and expose with UV.
UV hardens exposed resist. A wafer wash leaves only hard resist.
#2: grow gate oxide
oxide
#3: grow undoped polysilicon#4: spin on photoresist
UC Regents Fall 2006 © UCBCS 152 L11: VLSI
Wet etch to remove unmasked ...
p-
oxide
HF acid etches through poly and oxide, but not hardened resist.
p-
oxideAfter etch and resist removal
UC Regents Fall 2006 © UCBCS 152 L11: VLSI
Use diffusion mask to implant n-type
p-
oxide
accelerated donor atoms
n+
n+
Notice how donor atoms are blocked by gate and do not enter channel.
Thus, the channel is “self-aligned”,precise mask alignment is not needed!
CS 152 L11: VLSI UC Regents Fall 2006 © UCB
Metallization completes device
p-
oxide
n+
n+
Grow a thick oxide on topof the wafer.
p-
oxide
n+
n+
Mask and etch to make contact holes
p-
oxide
n+
n+
Put a layer of metal on chip.Be sure to fill in the holes!
UC Regents Fall 2006 © UCBCS 152 L11: VLSI
Final product ...
Top-down view:
p-
oxide
n+
n+
Vd Vs “The planar process”
Jean Hoerni,Fairchild Semiconductor1958
CS 152 L11: VLSI UC Regents Fall 2006 © UCB
p-channel Transistors
CS 152 L11: VLSI UC Regents Fall 2006 © UCB
p-Fet: Change polarity of everything
n-wellp+
Vwell
= Vs = 1V
p+
Vd = 0Vdielectric
Vg = 0V
I ≈ μA
p-
New “n-well” mask
Vg
Vs
Vd
Isd
“Mobility” of holes is slowerthan electrons.p-Fets drive less current than n-Fets, all else being equal
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Dynamic Memory Cells
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Recall: Capacitors in action
I = 0
Because the dielectric is an insulator, and does not conduct.
After circuit “settles” ...
Q = C V = C * 1.5 Volts (D cell)
Q: Charge stored on capacitor
C: The capacitance of the device: function of device shape and type of dielectric.
+++
+++
--- ---
After battery is removed:
+++
+++
--- ---Still, Q = C * 1.5 Volts
Capacitor “remembers” charge
1.5V
UC Regents Spring 2014 © UCBCS 152 L9: Memory
DRAM cell: 1 transistor, 1 capacitor
Vdd
Capacitor
“Word Line”“Bit Line”
p-
oxide
n+
n+
oxide------
“Bit Line”
Word Line and Vdd run on “z-axis”
Vdd
Diode leakag
ecurrent
.
Why Vcap values start out at ground.
Vcap
Word Line
Vdd
“Bit Line”
UC Regents Spring 2014 © UCBCS 152 L9: Memory
A 4 x 4 DRAM array (16 bits) ....
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Invented after SRAM, by Robert Dennard
UC Regents Spring 2014 © UCBCS 152 L9: Memory
DRAM Circuit Challenge #1: Writing
Vdd
VddVdd
Ids = k [Vgs -Vth]^2 , but “turns off” when Vgs
<= Vth!
Vgs
Vc
Vgs = Vdd - Vc. When Vdd - Vc == Vth, charging effectively stops!
Vdd - Vth. Bad, we store less charge. Q. Why do we not get Vdd?A. Because NFETs only pass “0” well.
+++++++
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DRAM Challenge #2: Destructive Reads
Vdd
Vc -> 0
+++++++
+++++++ (stored charge from cell)
0 -> Vdd
Word Line
Raising the word line removes the charge from every cell it connects to!DRAMs write back after each read.
Vgs
Bit Line
(initializedto a low voltage)
UC Regents Spring 2014 © UCBCS 152 L9: Memory
DRAM Circuit Challenge #3a: Sensing
Assume Ccell = 1 fFBit line may have 2000 nFet drains,assume bit line C of 100 fF, or 100*Ccell.Ccell holds Q = Ccell*(Vdd-Vth)
dV = [Ccell*(Vdd-Vth)] / [100*Ccell]dV = (Vdd-Vth) / 100 ≈ tens of millivolts! In practice, scale array to get a 60mV
signal.
When we dump this charge onto the bit line, what voltage do we see?
Ccell100*Ccell
UC Regents Spring 2014 © UCBCS 152 L9: Memory
DRAM Circuit Challenge #3b: Sensing
Compare the bit line against the voltage on a “dummy” bit line.
How do we reliably sense a 60mV signal?
...
“Dummy” bit line.Cells hold no charge.
?-+Bit line to sense
Dummy bit line
“sense amp”
UC Regents Spring 2014 © UCBCS 152 L9: Memory
DRAM Challenge #4: Leakage ...
Vdd
Bit Line+++++++
Word Line
p-
oxide
n+
n+
oxide------
Solution: “Refresh”, by rewriting cells at regular intervals (tens of milliseconds)
Parasitic currents leak away charge.
Diode leakage ...
UC Regents Spring 2014 © UCBCS 152 L9: Memory
DRAM Challenge #5: Cosmic Rays ...
Vdd
Bit Line+++++++
Word Line
p-
oxide
n+
n+
oxide------
Cosmic ray hit.
Solution: Store extra bits to detect and correct random bit flips (ECC).
This cell capacitor holds 25,000 electrons (today, less). Cosmic rays that constantly bombard us can release the charge!
UC Regents Spring 2014 © UCBCS 152 L9: Memory
DRAM Challenge 6: Yield
Solution: add extra bit lines (i.e. 80 when you only need 64). During testing, find the bad bit lines, and use high current to burn away “fuses” put on chip to remove them.
If one bit is bad, do we throw chip away?
...
Extra bit lines.Used for “sparing”.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
DRAM Challenge 7: Scaling
Recall: Process Scaling (“Moore’s Law”)
From: “Facing the Hot Chips Challenge Again”, Bill Holt, Intel, presented at Hot Chips 17, 2005.
Due to reducing V and C (length and width of Cs decrease, but plate distance gets smaller).
Recent slope more shallow because V is being scaled less aggressively.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
DRAM Challenge 7: Scaling
Each generation of IC technology, we shrink width and length of cell.
dV ≈ 60 mV= [Ccell*(Vdd-Vth)] / [100*Ccell]
Solution: Constant Innovation of Cell Capacitors!
Problem 1: Number of arrays per chip grows!
If Ccell and drain capacitances scale together, number of bits per bit line stays constant.
Problem 2: Vdd may need to scale down too!
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Poly-diffusion Ccell is ancient history
Vdd
Capacitor
“Word Line”“Bit Line”
p-
oxide
n+
n+
oxide------
“Bit Line”
Word Line and Vdd run on “z-axis”
Word Line
Vdd
“Bit Line”
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Early replacement: “Trench” capacitors
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The companies that kept scaling trench capacitorsfor commodity DRAM chipswent out of business.
Final generation of trench capacitors
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Modern cells: “stacked” capacitors
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Micron 50nm 1-Gbit DDR2 die photo
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Samsung 90nm stacked capacitor bitcell.
DRAM: the field for material and process innovationArabinda Das
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Cell access transistors for the 4 leading vendors
Chipmakers turn to new process for sub-nm DRAM cellsJeongdong Choe, TechInsights
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Samsung 30nm
From JSSC, and Arabinda Das
UC Regents Spring 2014 © UCBCS 152 L9: Memory
In the labs: Vertical cell transistors ...
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Break
Play:
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Today’s Lecture: DRAM
DRAM: Bottom-up
DRAM: Systems
DRAM: Top-down
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Memory Arrays
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Bit Line
“Column”
“Word Line”
“Row”
People buy DRAM
for the bits.
“Edge” circuits
are overhead.
So, we amortize the edge circuits over big arrays.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
8192 rows
16384 columns
134 217 728 usable bits(tester found good bits in bigger array)
1
of
8192
decoder
13-bitrow
address input
16384 bits delivered by sense amps
Select requested bits, send off the chip
A “bank” of 128 Mb (512Mb chip -> 4 banks)
In reality, 16384 columns are divided into 64 smaller
arrays.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Recall DRAM Challenge #3b: Sensing
Compare the bit line against the voltage on a “dummy” bit line.
How do we reliably sense a 60mV signal?
[...]
“Dummy” bit line.Cells hold no charge.
?-+Bit line to sense
Dummy bit line
“sense amp”
UC Regents Spring 2014 © UCBCS 152 L9: Memory
8192 rows
16384 columns
134 217 728 usable bits(tester found good bits in bigger array)
1
of
8192
decoder
13-bitrow
address input
16384 bits delivered by sense amps
Select requested bits, send off the chip
“Sensing” is row read into sense amps
Slow! This 2.5ns period DRAM (400 MT/s) can do row reads at only 55 ns (
18 MHz).DRAM has high latency to first bit out. A fact
of life.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
An ill-timed refresh may add to latency
Vdd
Bit Line+++++++
Word Line
p-
oxide
n+
n+
oxide------
Parasitic currents leak away charge.
Diode leakage ...
Solution: “Refresh”, by rewriting cells at regular intervals (tens of milliseconds)
UC Regents Spring 2014 © UCBCS 152 L9: Memory
8192 rows
16384 columns
134 217 728 usable bits(tester found good bits in bigger array)
1
of
8192
decoder
13-bitrow
address input
16384 bits delivered by sense amps
Select requested bits, send off the chip
Latency is not the same as bandwidth!
What if we want all of the 16384 bits? In row access time (55 ns) we can do
22 transfers at 400 MT/s. 16-bit chip bus -> 22 x 16 = 352 bits
<< 16384Now the row access time looks fast!
Thus, push to faster DRAM
interfaces
UC Regents Spring 2014 © UCBCS 152 L9: Memory
8192 rows
16384 columns
134 217 728 usable bits(tester found good bits in bigger array)
1
of
8192
decoder
13-bitrow
address input
16384 bits delivered by sense amps
Select requested bits, send off the chip
Sadly, it’s rarely this good ...
What if we want all of the 16384 bits? The “we” for a CPU would be
the program running on the CPU.Recall Amdalh’s law: If 20% of the
memory accesses need a new row access ... not good.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
DRAM latency/bandwidth chip features
Columns: Design the right interfacefor CPUs to request the subset of a column of data it wishes:
16384 bits delivered by sense amps
Select requested bits, send off the chipInterleaving: Design the right interface
to the 4 memory banks on the chip, soseveral row requests run in parallel.
Bank 1 Bank 2 Bank 3 Bank 4
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Off-chip interface for the Micron part ...
Note! This example is best-case!
To access a new row, a slow ACTIVE command must run
before the READ.
A clocked bus:200 MHz clock, data transfers on both edges
(DDR).
DRAM is controlled via commands(READ, WRITE, REFRESH, ...)
Synchronous data output.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Opening a row before reading ...
55 ns between row opens.
15 ns 15 ns
Auto-Precharge READ
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However, we can read columns quickly
Note: This is a “normal read” (not Auto-Precharge).
Both READs are to the same bank, but different columns.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
8192 rows
16384 columns
134 217 728 usable bits(tester found good bits in bigger array)
1
of
8192
decoder
13-bitrow
address input
16384 bits delivered by sense amps
Select requested bits, send off the chip
Column reads select from the 16384 bits here
Why can we read columns quickly?
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Interleave: Access all 4 banks in parallel
Can also do other commands on banks concurrently.
Interleaving: Design the right interface to the 4 memory banks on the chip, soseveral row requests run in parallel.
Bank a Bank b Bank c Bank d
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Only part of a bigger story ...
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Only part of a bigger story ...
UC Regents Spring 2014 © UCBCS 152 L9: Memory
DRAM controllers: reorder requests
From:
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Today’s Lecture: DRAM
DRAM: Bottom-up
DRAM: Systems
DRAM: Top-down
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Installing a Dual Inline Memory Module (DIMM)
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DDR2 SO-DIMM Module
DRAM chipsare wired in parallel and run in lockstep.
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From DRAM chip to DIMM module ...
Each RAM chip responsible for 8 lines of the 64 bit data bus (U5 holds the check bits).
Commands sent to all 9 chips, qualified by per-chip select lines.
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Integrated Memory Controller (IMC)On the same die as CPU.
SDRAMbus:Parallel bus with a single master.
How DIMMs talk to CPU
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Intel Core i5: Sandy BridgeAll on chip:
x86 cores
GPU
NorthBridge
DRAM controller
On chip ring network
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Lower levels of DRAM bus specification
Transaction Protocols
Signal Timing on Wires
Wires
Electrical Properties
Mechanical Properties
Ideally, DIMMs made by any manufacturer should fit into any compliant socket, and work.
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Upper levels of DRAM bus specification
Transaction Protocols
Signal Timing on Wires
Wires
Electrical Properties
Mechanical Properties
Collaboration between DRAM manufacturers(Samsung, Micron) and DRAM users (Intel, Cisco, ... ).
UC Regents Spring 2014 © UCBCS 152 L9: Memory
Bus wires shared between many DIMMS
Apple Xserve G5 - has 8 DIMM slots, to support 8GB.
Memory controller is the only “bus master” - it can start transactions on the bus, but the DIMMs cannot.
DIMMs respond to transaction requests. Since memory controller is the only bus master, and there are a small number of DIMM slots, bus sharing is easy: use DIMM-select signal wires to each slot.
4 core Jaguar
x86
4 core Jaguar
x86
1152 GPU Cores
1.84 TeraFLOP
5.5 GHz GDDR5
176 GB/s Mem BW Sony PS 4Uses graphics DRAM for all8GB of RAM(very high bandwidth).
Tradeoff:GDDR5 chipsconnect to CPU with dedicatedwires. Not viaa shared bus. More system pins, thus higher cost.
Focus is on “serious
gamer” not “media center”.
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MacBook Air ... too thin to use DIMMs
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Non-removable, “form-fit” battery ...Mainboard: fills about 25% of the laptop
35 W-h battery: Fills most of the volume ...
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Macbook AirTop
Bott
om
4GB DRAM soldered to the main board
Core i5: CPU + DRAM controller
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Original iPad (2010)
“Package-in-Package”
Cut-away side view
128MB SDRAM dies (2)Apple A4
SoC
Dies connect using bond wires and solder balls ...
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3-D memory stack
Thru-silicon-vias (TSVs)
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Sony Playstation Vita ...
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1 Gb Samsung Wide I/O DRAM + Toshiba/Sony ARM CPU.
1080 pads with 40 µm spacing, face-to-face.
“Face-to-face” limits this scheme to two chips, but avoids thru-silicon-vias (TSVs).
On Thursday
Caching, part one ...
Have fun in section !