Santa Clara University College of Engineering
Department of Electrical Engineering
Tutorial on Using Synopsys Verilog Simulator (VCS)
This tutorial describes how to use the Synopsys Verilog simulator to simulate a Verilog circuit and how
to display graphical waveforms.
Note : VCS is only accessible from a Linux machine in the design center. You can use NX to do this. More
information can be obtained from the design center (lab desk)
Note : You should be a little familiar with a Linux machine in order to be productive
In order to setup up VCS you must type in “setup vcs”
-bash-$ setup vcs
Now, verify your setup is done correctly
-bash-$ which vcs
Should return
/opt/vcs-2009.06/app/bin/vcs
-bash-$ vcs -ID
Should return
Warning-[LNX_OS_VERUN] Unsupported Linux version Linux version 'CentOS release 5.3 (Final)' is not supported on 'i686' officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE to linux or suse32 to override. Please refer to release notes for information on supported platforms. vcs script version : C-2009.06 machine name = linux60809 machine type = linux machine os = Linux 2.6.18-128.7.1.el5PAE The FLEXlm host ID of this machine is "001ec9486a58" Compiler version = VCS-MX C-2009.06 VCS Build Date = May 19 2009 22:04:22 If you need to renew your license, please email this information to your Account Manager. To obtain contact information for your Account Manager
please email [email protected]
Now, let’s try and simulated a simple Verilog design
-bash-$ cp –r $VCS_HOME/doc/examples/basic-hdl/verilog/syn-fifo .
-bash-$ cd syn-fifo
To compile your design with VCS do the following:
-bash-$ vcs tb_fifo.v fifo.v -debug_all +v2k
Warning-[LNX_OS_VERUN] Unsupported Linux version Linux version 'CentOS release 5.5 (Final)' is not supported on 'i686'
officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE to linux or suse32 to override. Please refer to release notes for information on supported platforms.
Chronologic VCS (TM)
Version C-2009.06 -- Sat Jan 8 10:02:39 2011 Copyright (c) 1991-2008 by Synopsys Inc.
ALL RIGHTS RESERVED This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement controlling such use and disclosure.
Parsing design file 'tb_fifo.v' Parsing design file 'fifo.v' Top Level Modules:
tb_fifo No TimeScale specified Starting vcs inline pass...
1 module and 0 UDP read.
recompiling module tb_fifo gcc -pipe -O -I/opt/vcs-2009.06/app/include -c -o rmapats.o rmapats.c
if [ -x ../simv ]; then chmod -x ../simv; fi g++ -o ../simv 5NrI_d.o 5NrIB_d.o Nf4K_1_d.o rmapats_mop.o rmapats.o SIM_l.o /opt/vcs-2009.06/app/linux/lib/libvirsim.a /opt/vcs-
2009.06/app/linux/lib/librterrorinf.so /opt/vcs-2009.06/app/linux/lib/libsnpsmalloc.so /opt/vcs-2009.06/app/linux/lib/libvcsnew.so /opt/vcs-
2009.06/app/linux/lib/vcs_save_restore_new.o /opt/vcs-2009.06/app/linux/lib/ctype-stubs_32.a -ldl -lm -lc -lpthread -ldl ../simv up to date
CPU time: .098 seconds to compile + .024 seconds to elab + .293 seconds to link
Some common VCS compile switches
+v2k : enable Verilog-2001 syntax
-debug_all : enable graphical debug capabilities
In order to run your simulation in “batch” mode, do the following
-bash-$ ./simv
Chronologic VCS simulator copyright 1991-2008 Contains Synopsys proprietary information.
Compiler version C-2009.06; Runtime version C-2009.06; Jan 8 10:12 2011 ********* FIFO : Underflow = 0, Overflow = 0 **********
************ WRITING INTO FIFO *************
FIFO WRITE: Data = 16, Address = 0
FIFO WRITE: Data = 15, Address = 1 FIFO WRITE: Data = 14, Address = 2
..
..
..
.. FIFO READ: Address = 1, FIFO READ: Data = 1
FIFO WRITE: Data = 2, Address = 2
FIFO WRITE: Data = 3, Address = 3 FIFO WRITE: Data = 8, Address = 4
FIFO READ: Address = 2, FIFO READ: Data = 2
$finish called from file "tb_fifo.v", line 116. $finish at simulation time 455
V C S S i m u l a t i o n R e p o r t Time: 455
CPU Time: 0.020 seconds; Data structure size: 0.0Mb
Sat Jan 8 10:12:34 2011
Let us now run the simulation in “interactive” mode and look at waveforms.
-bash-$ : ./simv –gui &
Don’t forget the “&”, it will allow you to enter other commands in the xterm later on.
The DVE graphical debugger should now open:
Now, to see the design hierarchy, click on the “plus” symbol in the hierarchy window to expand the
hierarchy :
To plot the signals in the DUT, click on the DUT instance in the hierarchy window, right click with the
mouse, then “Add to waves-> New Wave View”
This will open up a new wave window and plot all the signals in the window:
Now run the simulation, by clicking on the start button (down arrow)
You will see the values for the signals you have plotted:
You can close the console window to get more space:
Click on the “zoom full” button to see the entire simulation :
Let’s assume you need to change something in your code.
Now, you can re-compile this inside of the debugger: